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Myers, Michael D. "THE DEVELOPMENT OF A NONLINEAR PHASE-LOCK LOOP WITH ADAPTIVE GAIN CONTROL BASED ON MODERN CONTROL THEORY." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1204823575.
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UGAZIO, SABRINA. "High-performance velocity, frequency and time estimation using GNSS." Doctoral thesis, Politecnico di Torino, 2013. http://hdl.handle.net/11583/2513765.
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GNSS (Global Navigation Satellite System) receivers provide PVT solution,
where PVT stands for Position, Velocity and Time. In general, the main interest
of the common GNSS user is on the position solution and as a consequence the
main focus of the research is the improvement of the position solution accuracy.
However, many applications exist in which the measurement of both velocity
and/or time is crucial and this is the reason why the focus of this thesis is on
the Velocity and Time solution.
The PVT solution is computed through trilateration techniques, based on a TOA
(Time Of Arrival) ranging technique, therefore the PVT solution is correlated
to the measurement of time. In particular, the position solution is related to a
time measurement while the velocity solution is correlated to a frequency measurement.
Different factors that affect the velocity estimate on one side and the time estimate
on the other side are taken into account in this thesis, that in classic PVT
solution are usually neglected.
In the velocity/frequency estimate, the significant measurement is the change in
the user-satellite distance, i.e. a relative measurement, thus the measurements
errors that remain constant during the time interval over which the velocity is estimated
cancel out. Carrier-phase difference solution enables velocity accuracy in
the order of 1 mm/s, a high-level accuracy which is crucial for many applications,
including Inertial Measurement Unit (IMU) calibration, motion compensation for
Synthetic Aperture Radar (SAR) and flight reference systems. Thanks to the
cancellation of the common errors, that in the position solution represents the
very larger error sources, in the velocity solution other minor effects become the
limiting error sources. The first goal investigated in this thesis is to look for the
accuracy limit that can be achieved in the velocity/frequency solution.
The second objective is to investigate the problem of high- accuracy time solution.
As well as the position, the time is an absolute measurement, affected
by large error sources. Furthermore, the clock error is in common to all the
satellite measurements, and due to this, the common errors among the satellites
are not told apart and are in general attributed to the clock measurement. As a
result, lots of error sources that are not involved in the position solution become
dominant in the time solution. A main limiting factor in the timing accuracy is
represented by the errors in ionospheric delay estimate, where many error sources
are involved, in particular the unknown bias due to the receiver hardware.
After a part to introduce GNSS and its basic principles, with the focus on the
aspects that are more relevant for the dissertation and that allow one to outline
the motivations of the work, the thesis is divided in three main parts, two regarding
in particular the velocity/frequency solution and the last one focused on
the high-accuracy time solution.
The first step to improve the velocity solution was to notice how the performance
is much worse on the vertical solution than on the horizontal and how highly correlated
the vertical solution is to the local frequency estimate. This is due to the
geometry of GNSS, that implies that users on the Earth or close to the Earth
(as aircrafts) can see satellites all around them on the horizontal direction, but
they cannot see satellites under them, which is rejected in a poorer geometry on
the vertical direction. Due to this characteristic, an error on the pseudorange, as
the clock error is, reflects on the vertical solution more heavily than on the other
dimensions. As a result, the vertical solution can be about three times worse
than the horizontal and from the covariance matrix of the solution it can be
seen how the correlation is high in particular between the vertical and the clock
solution. This fact is true both for the position and for the velocity solution,
which means that the vertical velocity accuracy is highly correlated to the local
oscillator frequency. As a result, a way to improve the vertical velocity accuracy
is to obtain a better estimate of the local frequency. In this thesis, models for
the local oscillators and ways to integrate the frequency estimate in the GNSS
solution are investigated.
Another important aspect to improve the performance of the velocity measurement
is to improve the accuracy of the GNSS measurement. Since the measurement
used to obtain precise velocity is the carrier phase, which enables accuracy
in the order of 1 mm/s, the goal to improve the accuracy on the carrier-phase
measurement is crucial. With this objective, novel Digital Phase Lock Loops (DPLLs) has been designed, both of second and third order, with an adaptive
bandwidth algorithm. The objective was to tune the loop bandwidth according
to the input signal dynamics and noise, and use a bandwidth small enough to
reduce the noise effects as much as possible, but wide enough to properly track
the input dynamics. Since the PLL is designed for precise velocity measurement,
the performance in terms of dynamics tracking ability is crucial.
The last part of the analysis concerns the time solution. In most of cases in
GNSS, high importance is given to the position accuracy, while the residual
common biases are included in the receiver clock error. This approach makes
the time solution not very accurate. Since the main bias which affects the time
solution is the ionosphere delay, in this thesis the accuracy of the Total Electron
Content (TEC) estimate is investigated, with the focus on the measurement bias.
All the measurements which this thesis refers to are made using GPS (Global
Positioning System) only, nevertheless sometimes in the thesis it is talked about
GNSS in general. This is because the approaches considered in this thesis are
tested here using GPS, but they can be applied to all the GNSSs.
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Hussain, Zahir M. "Adaptive instantaneous frequency estimation: Techniques and algorithms." Thesis, Queensland University of Technology, 2002. https://eprints.qut.edu.au/36137/7/36137_Digitised%20Thesis.pdf.
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This thesis deals with the problem of the instantaneous frequency (IF) estimation of sinusoidal signals. This topic plays significant role in signal processing and communications.
Depending on the type of the signal, two major approaches are considered. For IF estimation of single-tone or digitally-modulated sinusoidal signals (like frequency shift keying signals) the approach of digital phase-locked loops (DPLLs) is considered, and this is Part-I of this thesis. For FM signals the approach of time-frequency analysis is considered, and this is Part-II of the thesis.
In part-I we have utilized sinusoidal DPLLs with non-uniform sampling scheme as this type is widely used in communication systems. The digital tanlock loop (DTL) has introduced significant advantages over other existing DPLLs. In the last 10 years many efforts have been made to improve DTL performance. However, this loop and all of its modifications utilizes Hilbert transformer (HT) to produce a signal-independent 90-degree phase-shifted version of the input signal. Hilbert transformer can be realized approximately using a finite impulse response (FIR) digital filter. This realization introduces further complexity in the loop in addition to approximations and frequency limitations on the input signal. We have tried to avoid practical difficulties associated with the conventional tanlock scheme while keeping its advantages. A time-delay is utilized in the tanlock scheme of DTL to produce a signal-dependent phase shift. This gave rise to the time-delay digital tanlock loop (TDTL). Fixed point theorems are used to analyze the behavior of the new loop. As such TDTL combines the two major approaches in DPLLs: the non-linear approach of sinusoidal DPLL based on fixed point analysis, and the linear tanlock approach based on the arctan phase detection. TDTL preserves the main advantages of the DTL despite its reduced structure. An application of TDTL in FSK demodulation is also considered. This idea of replacing HT by a time-delay may be of interest in other signal processing systems. Hence we have analyzed and compared the behaviors of the HT and the time-delay in the presence of additive Gaussian noise.
Based on the above analysis, the behavior of the first and second-order TDTLs has been analyzed in additive Gaussian noise.
Since DPLLs need time for locking, they are normally not efficient in tracking the continuously changing frequencies of non-stationary signals, i.e. signals with time-varying spectra. Nonstationary signals are of importance in synthetic and real life applications. An example is the frequency-modulated (FM) signals widely used in communication systems. Part-II of this thesis is dedicated for the IF estimation of non-stationary signals. For such signals the classical spectral techniques break down, due to the time-varying nature of their spectra, and more advanced techniques should be utilized.
For the purpose of instantaneous frequency estimation of non-stationary signals there are two major approaches: parametric and non-parametric. We chose the non-parametric approach which is based on time-frequency analysis. This approach is computationally less expensive and more effective in dealing with multicomponent signals, which are the main aim of this part of the thesis.
A time-frequency distribution (TFD) of a signal is a two-dimensional transformation of the signal to the time-frequency domain. Multicomponent signals can be identified by multiple energy peaks in the time-frequency domain. Many real life and synthetic signals are of multicomponent nature and there is little in the literature concerning IF estimation of such signals. This is why we have concentrated on multicomponent signals in Part-H.
An adaptive algorithm for IF estimation using the quadratic time-frequency distributions has been analyzed. A class of time-frequency distributions that are more suitable for this purpose has been proposed. The kernels of this class are time-only or one-dimensional, rather than the time-lag (two-dimensional) kernels. Hence this class has been named as the T -class. If the parameters of these TFDs are properly chosen, they are more efficient than the existing fixed-kernel TFDs in terms of resolution (energy concentration around the IF) and artifacts reduction. The T-distributions has been used in the IF adaptive algorithm and proved to be efficient in tracking rapidly changing frequencies. They also enables direct amplitude estimation for the components of a multicomponent
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Martin, Daniel. "Analysis and Design of Phase Lock Loop Based Islanding Detection Methods." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/32967.
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As distributed generation penetrates the electric power grid at higher power levels, grid interface issues with distributed generation must be addressed. The current power system consists of central power generators, while the future power system will include many more distributed resources. The centralized power generation system is controlled by utility operators, but many distributed resources will not be controlled by utility operators. Distributed generation must use smart control techniques for high reliability and ideal grid interface.
This thesis discusses the grid interface issue of anti-islanding. An electric island occurs when a circuit breaker in the electric power system trips. The distributed resource should disconnect from the electric grid for safety reasons. This thesis will give an overview of the possible methods. Each method will be analyzed using the ability to detect under the non-detection zone and the economic feasibility of the method.
This thesis proposes two addition cases for analysis that exist in the electric power system: the effect of multiple methods in parallel in the non-detection zone and the possibility of a false trip caused by a load step. Multiple methods in parallel are possible because the islanding detection method is patentable, so each grid interface inverter company is likely to implement a different islanding detection method. The load step represents a load change when a load is switched on.Master of Science
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Johannes, Michael T. "A fixed-point phase lock loop in a software defined radio." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2002. http://library.nps.navy.mil/uhtbin/hyperion-image/02sep%5FJohannes.pdf.
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Hardwicke, K. R. "A SELF TUNING PHASE-LOCKED LOOP." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608941.
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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, CaliforniaThe uncertainty in the gain of voltage controlled crystal oscillators (VCXOs) used in the implementation of certain analog phase-locked loops (PLLs) suggests some form of automatic tuning algorithm, both for pretuning and during operation. This paper proposes an adaptive PLL (APLL) algorithm to fill this need for PLLs used in the recovery of tones in noise. This algorithm makes use of a resonant error algorithm to remove the effects of VCXO noise, measurement noise, and parasitic poles. Both classical convergence theorems and robustness theorems that indicate the functionality of the proposed algorithm are given. Finally, the implementation of this algorithm is considered.
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Kokel, Samuel John. "Retrodirective phase-lock loop controlled phased array antenna for a solar power satellite system." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3047.
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This thesis proposes a novel technique using a phase-lock loop (PLL) style phase control loop to achieve retrodirective phased array antenna steering. This novel approach introduces the concept of phase scaling and frequency translation. It releases the retrodirective transmit-receive frequency ratio from integer constraints and avoids steering approximation errors.
The concept was developed to achieve automatic and precise beam steering for the solar power satellite (SPS). The testing was performed using a transceiver converting a pair of received 2.9 GHz signals down to 10 MHz, and up converting two 10 MHz signals to 5.8 GHz. Phase scaling and conjugation was performed at the 10 MHz IF using linear XOR phase detectors and a PLL loop to synthesize a 10 MHz signal with conjugate phase.
A phase control loop design is presented using PLL design theory achieving a full 2π steering range. The concept of retrodirective beam steering is also presented in detail. Operational theory and techniques of the proposed method are presented. The prototype circuit is built and the fabrication details are presented. Measured performance is presented along with measurement techniques. Pilot phase detectors and PCL achieve good linearity as required. The achieved performance is benchmarked with standards derived from likely performance requirements of the SPS and beam steering of small versus large arrays are considered.
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Bishop, Andrew J. "An adaptive phase-locked loop for a video CODEC /." Thesis, McGill University, 1992. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=69584.
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This dissertation will outline the integrated circuit design of an adaptive phase-locked loop that will be used to synchronize the sampling clock for a video speed analog to digital converter. The adaptive phase-locked loop (PLL) that will be described has not previously been used in the application of video synchronization. We shall demonstrate that this type of PLL will be able to out perform a static PLL in terms of its acquisition time, while still achieving a comparable noise performance. The PLL we shall describe will also be designed to be integrated on a single sub-micron BiCMOS chip. It is desired to place on this same chip a video-speed filter, and an analog to digital converter. For this reason we shall also provide some data to better evaluate the feasibility of designing a single chip that will perform these three functions.
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Tang, Yiwu. "Adaptive phase locked loop in multi-standard frequency synthesizers /." The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu1486401895208464.
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Rideout, Howard. "A true-time delay beamforming system incorporating a wavelength tunable optical phase-lock loop." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27550.
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This thesis presents the study of a frequency-discriminator-aided optical phase-lock loop (OPLL) and its application to a fiber-Bragg-grating-based true-time delay (TTD) module for the purpose of phased-array antenna (PAA) beamforming. The TTD module uses uniform fiber Bragg gratings (FBGs) to form the delay lines of an FBG prism. The wavelengths from two external cavity laser diodes are phase-locked by the OPLL and applied to the FBG prism to achieve tunable time delays.
The performance of the system is evaluated using a time-delay measurement experiment. The experimental time delays generated are compared with the theoretically designed values and are found to be in close agreement. Simulations of the radiation patterns generated from the measured time delays are found to closely match the steering angle designed for the system. To the best of our knowledge, this is the first time an OPLL has been used in conjunction with an FBG-based TTD beamforming module.
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Park, Joohwan. "Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter." Diss., Texas A&M University, 2005. http://hdl.handle.net/1969.1/4194.
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Phase locked loops (PLL) are used in a variety of RF integrated applications
because of their ability to generate precise clock signals. These applications include
clock recovery systems, frequency synthesizers and frequency multipliers.
In order to achieve small size and low cost targets, the PLLs must be fully
integrated on-chip with all the necessary components. Unfortunately, the filtering
requirement for the low pass filter (LPF) demands a large silicon area, or the use of
external capacitors. Moreover, high-density recording and high data rates for image
transfer systems in wireless communication require more fully integrated LSI.
The main goal of this study is to find area efficiency with fully on-chip design,
and to provide a solution to improve the phase noise level without occupying a large area
or using off-chip components. Moreover, to reduce the phase noise level, it is necessary
to desensitize the VCO control when the loop is in the "lock zone". The introduced
phase noise enhancement (PNE) will smartly reduce the phase noise without degrading
the settling time by reducing the loop gain in the lock conditions.
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Melester, M. T., and M. S. Geoghegan. "An Intelligent Digital Phase-Locked Loop with Integral Gain Control, Signal Quality and Lock Detection." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615089.
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International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, NevadaAn intelligent digital phase-locked loop with integral automatic gain control, signal quality and lock detection suitable for implementation using current digital signal processing devices is presented. By exploiting information derived from these functions operating in unison, it is possible to realize improved performance in an adverse environment where fading or abrupt signal outages are encountered. The system described consists of several functions operating under the direction of a stored program. The state diagram model of the program is discussed along with design considerations for the system elements. Various aspects of the system are simulated in the presence of noise and signal outage and compared to the performance of a conventional phase-locked loop.
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Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.
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Shen, Baike 1972. "Slip frequency phase lock loop (PLL) for decoupled P-Q control of doubly-fed induction generator (DFIG)." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=81568.
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The term "sensor-less" in power electronic drives refers to measurement of mechanical shaft position and/or speed from the currents and voltages of the electrical machine. This thesis presents innovative sensor-less means (a Slip Frequency Phase Lock Loop (PLL) and a gamma-delta Axes Aligner) for implementing decoupled P-Q control of a doubly-fed induction generator (DFIG) for wind-turbine application. Proofs of concepts are by digital simulations.The accuracy of the Slip Frequency Phase Lock Loop in speed estimation is evaluated; the origin of a shortcoming (small phase lag) located and compensated for.
The Slip Frequency Phase Lock Loop (PLL) and a gamma-delta Axes Aligner are then evaluated as parts of the decoupled P-Q control of a wind turbine driven doubly-ed induction generator. The research succeeds in realizing robust decoupled P-Q control, that is one in which the generator parameters do not have to be known precisely and can have minor variations such as drifts with temperature. The system has been successfully tested for optimal wind power acquisition.
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Fábik, Peter. "Zesilovač s fázovým závěsem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219941.
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The aim of the master thesis is on lock-in amplifiers. Amplifier's basic parts and lock-in circuits description is listed in introductory chapters. The thesis offers overview of parameters of chosen devices available on the market and their possible usage. We describe HF2LI device functions and usage of ziControl software. With the aim to verify properties of the device and ziControl software, one of the last chapters focuses on manipulation with HF2LI device. The conducted experiments and achieved results are presented in the last chapter.
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Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.
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The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry's characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc.
This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis.
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Hejlek, Pavel. "Návrh smyčky fázového závěsu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220085.
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This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.
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AraÃjo, Renato Guerreiro. "PLL (Phase-Locked Loop) structures for single phase and three phase systems with a high rejection capacity to sub and interharmonic." Universidade Federal do CearÃ, 2015. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=15882.
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CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel SuperiorIn applications related to power converters, such as inverters, rectifiers and the use of active filters, the synchronization method represent a very important element in the performance of the control strategy of this equipment. The estimated values of the synchronism angle, frequency and amplitude determined by the synchronization algorithms present, facing strongly distorted signals with the presence of sub and interharmonics, high errors. This study presents two algorithms: one applied on single-phase electrical systems and one applied on three-phase electrical systems, with high immunity to interharmonics and subharmonics. First are presented the main synchronization systems that are used in the electrical power systems. In addition, will be presented the main causes and consequences of the presence of subharmonics and interharmnics in the system, as well as the mathematical modeling of the two algorithms with high rejection to these disturbances. Will be presented the simulation and the experimental results of the proposed algorithms and the comparison between these synchronization methods with particular methods present in the literature. As a result of the study, it can be seen that the proposed structures present a higher response time, but the error of the estimated signal with respect the fundamental component of the input signal is lower when compared to structures such as EPLL and structures based on SOGI. It was observed that the proposed synchronization methods are enabled to estimate the synchronism angle, the frequency and the fundamental component of the input signal adequately and can be used in control strategies of power converters.
Em aplicaÃÃes relacionadas à EletrÃnica de PotÃncia, como inversores, retificadores e a utilizaÃÃo de filtros ativos, o mÃtodo de sincronizaÃÃo representa um elemento chave no desempenho da estratÃgia de controle destes equipamentos. Os valores do Ãngulo de sincronismo, frequÃncia e amplitude estimados com determinados algoritmos de sincronizaÃÃo apresentam, diante de sinais fortemente distorcidos com a presenÃa de sub e inter-harmÃnicos, erros elevados. Neste trabalho sÃo apresentados dois algoritmos: um aplicado a sistemas elÃtricos monofÃsicos e outro aplicado a sistemas elÃtricos trifÃsicos, com elevada imunidade a inter-harmÃnicos e sub-harmÃnicos. Primeiramente sÃo apresentados os principais sistemas de sincronizaÃÃo utilizados em sistemas elÃtricos de potÃncia. AlÃm disso, sÃo apresentadas as principais causas e consequÃncias da presenÃa de sub-harmÃnicos e inter-harmÃnicos no sistema, bem como a modelagem matemÃtica dos dois algoritmos com elevada rejeiÃÃo a estes distÃrbios. SÃo apresentados os resultados de simulaÃÃo e experimentais dos algoritmos propostos e a comparaÃÃo entre estes mÃtodos de sincronizaÃÃo com determinados mÃtodos presentes na literatura. Como resultado do estudo, pode-se observar que as estruturas de sincronizaÃÃo propostas apresentam um tempo de resposta mais elevado, porÃm o erro do sinal estimado em relaÃÃo a componente fundamental do sinal de entrada à inferior quando comparado a estruturas como o EPLL e estruturas baseadas no SOGI. Com isso, tem-se que as mesmas estÃo habilitadas para estimar o Ãngulo de sincronismo, a frequÃncia e a componente fundamental do sinal de entrada adequadamente e podem serem utilizadas eficientemente em estratÃgias de controle de conversores de potÃncia.
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Rejnuš, Milan. "Měřicí zesilovač využívající vektorové synchronní detekce." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221146.
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The master’s thesis describes known methods of signal measurement using principle of synchronous detection. Various methods are presented, their principles are examined and the problems when using them are analyzed. Further, procedures for reduction of adverse effects are described also. Second part of this thesis is focused on the instrument design. The instrument is intended for detection and processing of the output signals in a given optometric system. The proposed device is designed to operate on the principle of synchronous detection method using a vector signal evaluation. Advantages and disadvantages are discussed below.
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Poslušný, Marek. "Vícepásmový mikrovlnný vysílač pro studium šíření elektromagnetických vln v atmosféře." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219945.
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Master’s thesis describes the design of multi-band microwave transmitters to study the propagation of electromagnetic waves in the atmosphere with the possibility of modulation of the transmitted signal. Based transmitters are synchronized phase lock loop, frequency multipliers, double balanced diode mixers.
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Čada, David. "Spektrální analyzátor do 500 MHz." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221242.
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This project deals with design and realization of the spectrum analyser using double superheterodyne topology with frequency range up to 500MHz. This work solves hardware blocks like phase lock loops, intermediate frequency filters, saw filter, crystal filter, logarithmic detector. Content of work is also design description and tuning of spectrum analyzer parts.
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Hordeski, Theodore J. "Digital FSK/AM/PM Sub-Carrier Modulator on a 6U-VME-Card." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611475.
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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, CaliforniaAerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.
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Jung, Seok Min, and Seok Min Jung. "Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/621292.
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The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.
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Svoboda, Josef. "Přímý číslicový frekvenční syntezátor." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217986.
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Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform, usually a sine wave, by generating a time varying signal in digital form a then performing a digital to analog conversion. Because operations within a DDFS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution and operation over a broad spectrum of frequencies.
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Umansky, Alec. "HIGH BANDWIDTH PORTABLE TRANSMISSION SYSTEMS USE OF xDSL TECHNOLOGY IN MILITARY, INDUSTRIAL AND TELEMETRIC APPLICATIONS." International Foundation for Telemetering, 2001. http://hdl.handle.net/10150/606418.
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International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, NevadaThis paper introduces new telemetry (communications) equipment based on Digital Subscriber Loop DSL technology (high speed transmission over copper cables) for defense and industrial applications. A brief xDSL technology overview is followed with introduction of the new ‘P3’ product and its application, reviewing advantages of using copper as a communications medium whenever rapidly deployed data and voice links are essential. An Australian Army report, detailing a specific equipment deployment’s findings is reproduced as an independent reference material.
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Umansky, Alec. "HIGH BANDWIDTH PORTABLE TRANSMISSION SYSTEMS USE OF xDSL TECHNOLOGY IN MILITARY AND INDUSTRIAL TELEMETRIC APPLICATIONS." International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/606792.
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International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, CaliforniaThis paper introduces new telemetry equipment based on Digital Subscriber Loop DSL technology (high speed transmission over copper cables) for military and industrial applications. A brief xDSL technology overview is followed with introduction of the new ‘P3’ product. A number of new applications for remote data transmission are presented and further highlighted in the Australian Army report detailing their recent equipment operational deployments.
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Sagha, Hossein. "Development of innovative robust stability enhancement algorithms for distribution systems containing distributed generators." Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/91052/1/Hossein_Sagha_Thesis.pdf.
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This project was a step forward in improving the voltage profile of traditional low voltage distribution networks with high photovoltaic generation or high peak demand. As a practical and economical solution, the developed methods use a Dynamic Voltage Restorer or DVR, which is a series voltage compensator, for continuous and communication-less power quality enhancement. The placement of DVR in the network is optimised in order to minimise its power rating and cost. In addition, new approaches were developed for grid synchronisation and control of DVR which are integrated with the voltage quality improvement algorithm for stable operation.
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Al, Ghossini Hossam. "Contributions to the study of control for small-scale wind turbine connected to electrical microgrid with and without sensor." Thesis, Compiègne, 2016. http://www.theses.fr/2016COMP2310/document.
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L'objectif de cette thèse est de proposer l'approche la plus appropriée afin de minimiser le coût d'intégration de petite éolienne dans un micro-réseau DC urbain. Une petit éolienne basé sur un machine synchrone à aimant permanent (MSAP) est considéré à étudier. Un état de l'art concernant les énergies renouvelables, micro-réseau DC, et la production d'énergie éolienne, est fait. Comme le capteur mécanique de cette structure est relativement d'un coût élevé, les différents types de contrôle pour un système de conversion éolienne sont présentés afin de choisir une structure active de conversion d'énergie et un MSAP sans capteur. Par conséquent, un estimateur de vitesse/position est nécessaire pour contrôler le système. Ainsi, les méthodes différentes proposées dans la littérature sont considérées et classifiées à étudier dans les détails, puis les plus efficaces et largement utilisés sont à vérifier dans la simulation et expérimentalement pour le système étudié. Les méthodes choisies sont: estimation de la flux de rotor avec boucle à verrouillage de phase (PLL), observateur à mode glissement (SMO), observateur de Luenberger d'ordre réduit, et filtre de Kalman étendu (EKF). Face à d'autres méthodes, l'estimateur basé sur un modèle EKF permet une commande sans capteur dans une large plage de vitesse et estime la vitesse de rotation avec une réponse rapide. Le réglage des paramètres EKF est le problème principal à sa mise en œuvre. Par conséquent, pour résoudre ce problème, la thèse présente une méthode adaptative, à savoir réglage-adaptatif d’EKF. En conséquence, et grâce à cette approche, le coût total du système de conversion est réduite et la performance est garantie et optimiséeThe aim of this thesis is to propose the most appropriate approach in order to minimize the cost of integration of a wind generator into a DC urban microgrid. A small-scale wind generator based on a permanent magnet synchronous machine (PMSM) is considered to be studied. A state of the art concerning the renewable energies, DC microgrid, and wind power generation is done. As the mechanical sensor for this structure is relatively of high cost, various types of wind conversion system control are presented in order to choose an energy conversion active structure and a sensorless PMSM. Therefore, a speed/position estimator is required to control the system. Thus, different methods proposed in literatures are considered and classified to be studied in details, and then the most effective and widely used ones are to be verified in simulation and experimentally for the studied system. The methods which are chosen are: rotor flux estimation with phase locked loop (PLL), sliding mode observer (SMO), Luenberger observer of reduced order, and extended Kalman filter (EKF). Facing to other methods, the EKF model-based estimator allows sensorless drive control in a wide speed range and estimates the rotation speed with a rapid response. The EKF parameters tuning is the main problem to its implementation. Hence, to solve this problem, the thesis introduces an adaptive method, i.e. adaptive-tuning EKF. As a result and grace to this approach, the total cost of conversion system is reduced and the performance is guaranteed and optimized
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Lien, Chien Yung, and 簡永烈. "Design of Blind Adaptive Beamformer Combined with Phase Lock Loop." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/99394479721570467553.
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碩士國立海洋大學
電機工程學系
88
The conventional Frost beamformer is incapable of exacting desired signal in the multipath propagation environment. It is very sensitive to the position error among the sensors, and needs prior information about the direction of arrival (DOA) of the desired signal. To overcome the problems mentioned above, we propose a new method that exploits the cyclostationary property of communication signals, in the design of blind adaptive beamformer. The proposed beamformer uses the LMS algorithm to minimize the mean square error between the transformed array output signal and a complex exponential signal. In the case where DQPSK is the desired signal, the complex exponential signal, representing a spectral line at the carrier frequency of the DQPSK signal, is extracted from the transformed array output as a reference signal by the use of phase lock loop. To evaluate the performance of the proposed beamformer, computer simulations for the cases of Gaussian white noise, multiple interferences, and multipath propagation were carried out. Simulation results show that the proposed beamformer is rather effective to increase signal-to-noise ratio, cancel interferences, and remove intersymbol interference.
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LUO, ZHI-TONG, and 羅治同. "An adaptive digital phase lock loop under sinusoidal interference conditions." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/75058131604016916819.
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Chen, Yan Hao, and 陳彥豪. "1.09375GHz Delta Sigma Phase Lock Loop." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/5x857m.
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碩士國立清華大學
電機工程學系
103
There are two part in this paper. The first part in this paper is a discussion about delta sigma modulation phase lock loop circuit design and the second part in this pa- per is appendix about linear control oscillator circuit design . In delta sigma phase lock loop circuit design , the pur- pose and specific are described and overview of integer, fractional delta sigma phase lock loop . Final part of delta sigma phase lock loop is design and simulation. In linear control oscillator circuit design , the motive of design linear voltage control is described and intro- duce some knowledge about ring oscillator .Then , some linear voltage control oscillator introduction are pre- sent . Final part of linear control oscill- ator is design and simulation .
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Chiang, Yu-Chen, and 江宇晟. "Jitter Performance Study For Phase-Lock Loop." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/70476321354403064487.
Full textAbstract:
碩士國立清華大學
電機工程學系
93
In many circuits, PLL must provide an output clock to follow the input clock closely. Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch. This thesis proposes the prediction method of jitter performance, for estimate the output jitter comes from each noise source. Initially, Hspice and Spectre are used to estimate the output phase noise of each noise source in coordinate with phase-noise-to-jitter transfer function and noise transfer function (NTF) to estimate the PLL output jitter. This thesis primary considered the noise created by phase-locked loop. Include thermal analysis and the phase noise created by each block in PLL. Thermal Analysis: This part primarily analysis the phase noise created by each block in PLL. Then use the phase noise to jitter equation to estimate the PLL output jitter. PLL Each Block Phase Noise: This park primarily consider VCO phase noise、current mismatch created by PFD/CP and input clock phase noise.
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LIN, HONG-REN, and 林鴻任. "2.4-GHz Integer-N Phase-Lock Loop." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/374833.
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碩士國立臺北科技大學
電子工程系
107
This paper presents a fully-integrated 2.4 GHz phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the delay cell Ring Oscillator and high speed true single phase clock (TSPC) divider, the 2.4 GHz PLL achieves low power consumption of 9.45 mW. In addition, an inverter type buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noise is −92.6 dBc/Hz at 1 MHz frequency offsets, and Reference Spur is 40.9 dBc, respectively. The output frequency is 2.18−2.91 GHz. The second section uses a multi-modulus frequency divider, and the 2.4 GHz PLL achieves a wide frequency output frequency at the same reference frequency. Using a reference frequency of 37.5 MHz, the multimode divider is controlled to operate 16 states with control voltage and output a frequency range of 2.4 GHz to 2.9625 GHz. The phase noise measured at 1 MHz frequency offset is -92.6 dBc / Hz and the reference glitch is 40.9 dBc.
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Pitts, Wallace Shepherd. "Partially depleted silicon on insulator phase lock loop." 2005. http://www.lib.ncsu.edu/theses/available/etd-01042006-202434/unrestricted/etd.pdf.
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Dzung-Li, Lin, and 林宗立. "Small DC Brushless Motor Phase Lock Loop Control." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/30896957315215746420.
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Chen, Ming-Jing, and 陳銘金. "5 GHz Phase Lock Loop with Auto Band Selection." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/4m5s5u.
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碩士國立中山大學
資訊工程學系研究所
95
This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18μm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation.
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Tsai, Sheng-Chung, and 蔡勝中. "Design and Implementationof an All Digital Phase Lock Loop." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/56679715727627733504.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
93
ABSTRACT In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. A 16-bit digitally controlled CMOS oscillator uses a 4-stage ring of a modified differential delay cell. The DCO uses the even-stage skew dual-delay path scheme [11], which enables higher operating frequency. The frequency search and the phase tracking are major blocks in a control unit. We use a high sensitivity phase tracking and frequency search algorithm, which consists two D-type flip flop and some logical circuits. In our proposed ADPLL, we implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in the TSMC 0.18μm 1P6M technology. The supply voltage is 1.8V. The simulation results show that when DCO operates at 2.4GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 30 reference clock cycles (algorithm). The lock-in range is 2.07GHz to 2.56GHz. The power consumption is 106.1mW at 2.4GHz.
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Sheng-Chung, Tsai. "Design and Implementation of an All Digital Phase Lock Loop." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2607200513510400.
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Liu, Jen-Chieh, and 劉仁傑. "All Digital Phase Lock Loop Using Signal-Edge-Trigger DCO." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/25730471276305357522.
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碩士輔仁大學
電子工程學系
94
An all-digital phase locked-loop (ADPLL) is presented to achieve fast lock, high resolution and process immunity. A novel digitally controlled varactor (DCV) is used in fine-tuning delay cell design. The proposed DCO architecture uses Single-Edge-Trigger DCO. Thus, it has the characteristics of, high resolution, flexible operating range, and easy design. The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.6ps resolution and the proposed DCO can extend the controllable range easily. The ADPLL implemented in a 0.18um single-poly six-metal (1P6M) technology can operate from 150 to 450MHz and achieve worst case frequency acquisition in 32 reference clock cycles. The chip size was 850 850 um2 (core: 260 360 um2), and the power consumption was10mW at 400MHz.
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Wu, Chia-Tsun, and 吳嘉村. "Portable Fast Locking All-Digital Phase-Lock Loop Circuit Design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/60872547279439026303.
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碩士國立臺灣大學
電子工程學研究所
91
PLL circuits become more and more popular in different System on Chip (SOC) applications, since most ICs need precise clocking schemes. An All-Digital Phase-Lock Loop can be easy transferred during process migration. However, most existing ADPLL circuits use in-house cell libraries or full-custom techniques to design ADPLL. In order to guarantee the shortest transfer period during process migration and minimum design efforts. We develop a new architecture that employs standard-cell library to design ADPLL. All cell libraries that are used in ADPLL design are provided from foundry. Also, we develop new tracking algorithm for fast phase and frequency locking. The new algorithms can lock input reference clock with two input cycles in any case. The core area is 0.1 mm2 (0.25um technique).
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Chang, Chun-Chiang, and 張俊強. "A phase lock loop circuit design for thermal-actuated resonators." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/56006568999845025894.
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碩士國立交通大學
機械工程系所
101
This study applied a thermal-actuated resonator by using a piezo-resistive sensor and designed the measurement circuits for micro-resonator. The resonator’s frequency will change when the plane adsorbs the material. To measure the change of resonator’s natural frequency we can know the mass of the material. The resonator was vibrated by the thermal actuator and designed a piezo- resistive sensor in the form of Wheatstone bridge circuits to measure the signal. The phase difference between the resonator input signal and output signal can be locked on -180° by the theory of Phase lock loop. According to the method, we can obtain the natural frequency of resonator. Besides, the resonator’s output signal will generate a Feed through noise. In order to reject the noise the study propose the idea by demodulating the frequency through the circuits of multiplier to reduce the noise. The resonator was a three order dynamic system, and the natural frequency located when the phase was on -180°. The phase cannot be locked by traditional Phase lock loop because the Phase lock loop usually locked the phase difference on 90°. The study used the analog RC filter to make phase delay on reference signal before passing the Phase detector. Making the phase difference between resonator output signal and reference signal on -90°. The phase and natural frequency can be locked. The circuit was simulated by Hspice 0.35um 2PM4 3.3V process, and using the MATLAB&;SIMULINK to make the model of the system. Through the software, we can combine and discuss the system’s performance and data. And then the resonator and measurement circuit can be expected to present.
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Yeh, Nan-Liang, and 葉湳良. "Design of Phase Frequency Detector and Enhanced Lock-in for Phase-Locked Loop." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/22819986223927581840.
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碩士長庚大學
半導體研究所
90
The two main directions of study in this thesis include both the design of phase/frequency detector and the enhanced lock-in for phase-locked loop. We systematically analyze existing phase/frequency detectors from aspects of theoretical analysis and circuit operation. We also propose a phase/frequency detector which has simple structure, no glitch output as well as better phase characteristics. Based on simulation results, the proposed phase/frequency detector shows satisfactory circuit performance with higher operation frequency, low phase jitter and smaller die size. Furthermore, we present a simple enhanced lock-in system for phase-locked loop. The proposed mechanism can reduce the lock-time effectively by using the reference clock signal only. Besides, the whole enhanced lock-in circuit performs its operation in one reference clock cycle.
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吳育倫. "Study of Electromagnetic Interference Detection Using Embedded Phase-Lock Loop Microcontrollers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/22277794409092388371.
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博士逢甲大學
電機與通訊工程博士學位學程
102
This thesis has two parts. First part is to design a multi-band bandstop filter and miniaturize the circuit by bending stubs. In chapter 3, a general design methodology of a multi-band bandstop filter with compact and controllable multi stopband response is proposed. Second part presents a combined hardware–software mechanism for the detection of electromagnetic interference of a microcontroller (μC) in daily usage. This detection mechanism is based on the instability of phase-lock loop embedded in the target μC. The statistic results of PLL locked time in normal environment and disturbance environment. We find the statistic results are significantly different in normal and disturbance environment. Therefore, the phenomenon is used to be a foundation to detect EMI. It can detect the presence of EMI with higher sensitivity than polling the hardware status of the μC internal registers and thus provides a better detection margin within the 10 kHz to 1 GHz EMI frequency range. Despite its relative slowness and its resource consumption, it is very robust and can be implemented in virtually application software, and does not require any electromagnetic compatibility test equipment.
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LAI, WEI-JIE, and 賴暐傑. "The Circuits Design and Control of Phase Lock Loop On Servo Motor." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/9xr435.
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碩士明志科技大學
電機工程系碩士班
104
In the promotion of industrial automation, the motor is the driving force of the majority productivities; it depends on the power electronic to enhance the key technology of motor control. To improve the industrial automation, motor control technology and related theories are crucial. Therefore, this study using phase locked loop design servo motor drive, the phase lock loop (PLL) is one of the basic structures of modern electronic technology, and they have been widely used in communication, multimedia and other multiple uses. In this thesis, the design of the servo motor drive is used a speed control method to control servo motor. It is similar to the accuracy invertor for AC motor, and belonging to a part of the servo system, by adopting thing a high precision positioning method. Besides, using a the IC HEF4046B designed by NXP Semiconductors and IGBT PS21965-T designed by Mitsubishi Electric Corporation, to store a set of three groups d2764a EPROM IC inside and a three-phase waveforms of stator currents then to fulfill the design to control the servo motor-system.
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Tz-Cheng, Yang. "A 18.5GHz Fully Differential Phase Lock Loop for 40~48GHz UWB System." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200623454300.
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Yang, Tz-Cheng, and 楊子承. "A 18.5GHz Fully Differential Phase Lock Loop for 40~48GHz UWB System." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/20782977735775607780.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
With the rapid growing of the wireless communication system, the demands of high precision phase-locked loops (PLLs) increase significantly. Besides, output phase noise of PLLs is very important for local oscillator. It is because that the quality of phase noise would influence bith transmitting and receiving chain seriously. This thesis will aim to implement an 18.5 GHz PLL with improved phase noise for 40~48 GHz UWB system. We will propose two architectures which are a common high speed phase-locked loop and an improved fully differential phase-locked loop. The performance of both architectures will be compared.
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Luo, Ming-Chuang, and 羅銘銓. "A 3V, Fast lock-in Phase-locked Loop for High Speed System." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/03909307916994524511.
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碩士國立清華大學
電機工程學系
85
In this thesis, we propose a 3V, fast lock-in phase-locked loop with wide frequency range for high speed data systems. This PLL, which is used as a frequency synthesizer for clock/data recovery, is realized by a charge-pump PLL. The PLL consists of several components, a phase detector, a charge pump, a voltage- controlled oscillator, a loop filter, and a frequency divider. For fast lock-in, the phase detector is implemented by a phase- frequency detector. Furthermore, path delay is taken into consideration for higher speed operation. By comparing the phase and frequency difference of it''s inputs, the PFD generates four outputs in response to the difference. Then, accompanying the PFD by a charge-pump the four logic values are converted as an analog signal for controlling the voltage-controlled oscillator. The charge pump has the advantage of having current matching property and being as simple as 8 transistors only. Since the PLL is to generate multi-phase outputs, a 5-stafe differential VCO is used to generate 10 outputs. Since being differential, the VCO has better noise rejection.In addition, the VCO has the property of being nearly full-swing and sensitive to controlling voltage variation.The PLL is realized by 0.6 m DPPM CMOS technology. The HSPICE post-layout simulation results justify the feasibility of out proposed PLL.
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Nikkhoo, Nasim. "Phase-locked loop with adaptive supply noise cancellation." 2007. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=452844&T=F.
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Wei, Wang. "Portable All-Digital Phase-Lock Loop Circuit Design With Programmable Pulse Width Control." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1307200515550300.
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WANG, Yu-Chung, and 王裕忠. "The study of radio frequency voltage control oscillators for phase lock loop system." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74389854815678946061.
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碩士國立臺灣科技大學
電子工程系
93
Design of CMOS Voltage-Controlled Oscillator (VCO) will be investigated in this thesis. First, ring oscillator architecture is the complementary nMOS and pMOS cross-coupled pair to enhance the negative conductance with internal resonator. CMOS VCO’s are implemented using TSMC 0.35µm process with 3.3V supply voltage and frequency tuning range 1.7616GHz~2.466GHz. Otherwise, LC tank voltage control oscillator includes LC cross coupled VCO、dual band LC VCO、complementary Colpitts VCO and complementary Colpitts VCO with back gate coupling. The LC tank VCO is implemented using TSMC 0.18µm process with 1.8V supply voltage. The simulation results with Cadence Spectre RF aid the design of these VCO’s.