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Florentín, Matthieu. "Irradiation impact on optimized 4H-SiC MOSFETs." Doctoral thesis, Universitat Politècnica de Catalunya, 2016. http://hdl.handle.net/10803/395187.
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Silicon (Si) power device’ technologies have reached a high maturity level, but current
limitations on mechanic, temperature operation and electric performances require to investigate other semiconductor materials that can potentially compete with and overcome those border issues. This is the case of Silicon Carbide (SiC) and Gallium Nitride (GaN) which are becoming serious competitors to the Si due to their superior physical properties. Concerning SiC, the 4Hpolytype seems to be the best suitable candidate for high power MOSFETs according to its band gap, electric field strength, electron bulk mobility, and attainable threshold voltage, among others. But still, technological processes must be optimized in order to SiC MOSFETS can compete with their Si counterparts. This is the case of the gate oxidation process. A reduction of interface charge density is required for threshold voltage stability, and further improvements of the interface quality are also needed for high inversion mobility values. Once solved these problems, a path toward new perspectives of high power applications will be opened.
This work is the direct continuation of the Aurore Constant’s work. It is focused on 4HSiC
based devices, more specifically on the gate oxidation processes and their behaviour under
different harsh environments. Up to now, most of the works carried out were focused on the
improvement of the Silicon Dioxide-Silicon Carbide (SiO2/SiC) interface quality. Solving those
problems would allow designing high-speed and low-switching losses MOSFETs. In the past
work, the main strength was focused on a new surface pre-treatment and on a gate oxidation
process. Results showed improved electrical performances. However, we are convinced that
better values can be obtained by optimizing the post-oxidation annealing step, by performing
surface counter doping or by performing special irradiation treatments. All the efforts of this
work will oriented to the development of reliable SiC MOSFETs with improved electrical
parameters, which can operate under harsh environments (like high temperature or
proton/electron irradiated environment). Thus, the mains guidelines of this Ph. D. Thesis are in accordance with the following lines:
1. State of the art on various SiC related fields.
2. Electrical characterization processes.
3. Proton irradiation impact on 4H-SiC MOSFETs and charge build-up mechanisms theory at
the SiO2/SiC interface.
4. Electron irradiation impact on 4H-SiC MOSFETs.
5. Gate oxidation and implantation processes optimization.
6. Robustness limit of the improved processes under irradiation environments.Las tecnologías de dispositivos de potencia en silicio (Si) han alcanzado una gran madurez. Sin embargo, las limitaciones del Si debidas a sus restricciones mecánicas, térmicas y eléctricas hacen necesario otros materiales semiconductores que puedan competir con el Si y superar sus limitaciones. Este es el caso del Carburo de Silicio (SiC) y del Nitruro de Galio (GaN) que ya comienzan a ser serios competidores del Si debido a sus mejores propiedades físicas. En lo que respecta al SiC, el politipo 4H es el candidato más adecuado para la integración de MOSFETs de potencia debido, entre otros, a los valores del bandgap, campo eléctrico crítico, movilidad volumíca de los electrones y tensión umbral alcanzable. A pesar de estas ventajas teóricas del material, es necesario optimizar cada uno de los procesos tecnológicos involucrados en la fabricación de un MOSFET en SiC para que realmente pueda competir con su contrapartida en Si. Este es el caso del proceso de oxidación para la formación del dieléctrico de puerta. Concretamente, una buena estabilidad de la tensión umbral del componente requiere disminuir la densidad de cargas en la interfase óxido/semiconductor, y mejoras adicionales en la calidad de esta interfase son también necesarias para obtener altos valores de la movilidad de los portadores en el canal de inversión. La solución de los problemas tecnológicos anteriormente enunciados abrirá nuevas perspectivas a las aplicaciones de alta potencia. Este trabajo es una continuación directa del de Aurore Constant. Se centra en dispositivos basados en 4H-SiC, y más específicamente en los procesos de oxidación de puerta, y de sus comportamientos eléctricos en diferente ambientes de trabajo hostiles. Hasta la fecha, la mayor parte de la investigación se ha centrado en la mejora de la calidad de la interfase dióxido de silicio/carburo de silicio (SiO2/SiC). La solución de estos problemas debería permitir el diseño de MOSFETs muy rápidos y con pérdidas de conmutación muy bajas. El objetivo del trabajo previo de Aurore Constant fue encontrar un nuevo procedimiento de limpieza de la superficie antes de realizar la oxidación, y en definir un nuevo proceso de oxidación para la formación del dieléctrico de puerta. Los resultados obtenidos mostraron claras mejoras del comportamiento eléctrico de los componentes. Sin embargo, estamos convencidos que la mejora podría ser aún mayor optimizando la etapa del recocido post-oxidación, utilizando un proceso adicional de dopaje superficial, o realizando un adecuado proceso de irradiación. Todos los esfuerzos de este trabajo se han dirigido al desarrollo de MOSFETs en SiC fiables, con mejores características eléctricas, y capaces de trabajar en ambientes de alta temperatura y de irradiación protónica o electrónica. En resumen, las principales líneas de esta Tesis son las siguientes: 1. Estado del arte de los diferentes dominios de trabajo del SiC. 2. Procesos y técnicas de caracterización eléctrica. 3. Impacto de la irradiación de protones en MOSFETs fabricados en 4H-SiC, y descripción teórica de los mecanismos de creación de carga en la interfase SiO2/SiC. 4. Impacto de la irradiación electrónica en MOSFETs fabricados en 4H-SiC. 5. Optimización de los procesos de oxidación y de implantación. 6. Límite de robustez de los procesos tecnológicos optimizados en ámbitos irradiados.
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Robert, Teddy. "Spectroscopie des fautes d'empilement dans 4H-SiC." Montpellier 2, 2009. http://www.theses.fr/2009MON20166.
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Li, Mingyu Williams John R. "Ohmic contacts to implanted (0001) 4H-SiC." Auburn, Ala., 2009. http://hdl.handle.net/10415/1960.
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Haasmann, Daniel Erwin. "Active Defects in 4H–SiC MOS Devices." Thesis, Griffith University, 2015. http://hdl.handle.net/10072/367037.
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The research findings presented in this thesis have provided several key contributions towards a better understanding of the SiC–SiO2 interface in SiC MOS structures. The electrically active defects directly responsible for degrading the channel-carrier mobility in 4H–SiC MOSFETs have been identified and a novel technique to detect these defects in 4H–SiC MOS capacitors has been proposed and experimentally demonstrated. With a better understanding of defects at the SiC–SiO2 interface two alternative gate oxide growth processes have been proposed to overcome the practical limitations associated with current NO-nitridation techniques in high-volume, production based oxidation furnaces. This work therefore contributes to the wider research effort towards improving the performance of SiC MOSFETs in several ways. The following paragraphs summarise the key conclusions that have been obtained as a result of this study.
Electrically Active Defects and the Channel-Carrier Mobility (Chapter 3)
A critical review of defects at the SiC–SiO2 interface exposed a few key discrepancies in both the current understanding of the dominant defects responsible for channel-carrier mobility degradation in 4H–SiC MOSFETs and in the current approach to characterise and evaluate the SiC–SiO2 interface. Firstly, it was recognised that the Shockley-Read-Hall statistical model, based on thermally activated transport for traps spatially located at the semiconductor-oxide interface, cannot be directly applied to describe the transfer mechanism between free conduction band electrons and the shallow NITs near EC. This implication tends to suggest that the NITs near EC in SiC MOS structures cannot be accurately examined using traditional MOS characterisation techniques that are based on this statistical model. Secondly, in accordance with the studies conducted by Saks et. al. [1-3], it was realized that channel-carrier mobility degradation in 4H–SiC MOSFETs is primarily due to the significantly reduced free electron density in the inversion channel. In light of this understanding, the interfacial defects that actively trap channel electrons under strong inversion conditions were considered to be dominant in these devices as opposed to the NITs near EC that are typically examined using conventional MOS characterisation techniques on N-type MOS capacitors in depletion. To further support this hypothesis, a theoretical analysis of the inversion carrier concentration using the charge sheet model was conducted to demonstrate that the NITs with energy levels corresponding to strong inversion are of key importance to the channel-carrier mobility.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
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Horita, Masahiro. "Isopolytypic Growth of Nonpolar 4H-AlN on 4H-SiC and Its Device Applications." 京都大学 (Kyoto University), 2009. http://hdl.handle.net/2433/81830.
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Sejil, Selsabil. "Optimisation de l'épitaxie VLS du semiconducteur 4H-SiC : Réalisation de dopages localisés dans 4H-SiC par épitaxie VLS et application aux composants de puissance SiC." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSE1170/document.
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L'objectif du projet VELSIC a été de démontrer la faisabilité de jonctions p+/n- profondes dans le semiconducteur 4H-SiC, de haute qualité électrique, comprenant une zone p++ réalisée par un procédé original d'épitaxie localisée à basse température (1100 – 1200°C), en configuration VLS (Vapeur - Liquide - Solide). Cette technique innovante de dopage par épitaxie utilise le substrat de SiC mono cristallin comme un germe de croissance sur lequel un empilement enterré de Al - Si est porté à fusion pour constituer un bain liquide, lequel est alimenté en carbone par la phase gazeuse. Cette méthode se positionne comme une alternative avantageuse à l'implantation ionique, actuellement utilisée par tous les fabricants de composants en SiC, mais qui présente des limitations problématiques encore non résolues à ce jour. Les travaux de thèse ont exploré toutes les facettes du processus complet de fabrication de diodes de test, avec une attention particulière portée sur l'optimisation de la gravure de cuvettes dans le substrat SiC. Le cœur des travaux a été concentré sur l'optimisation de l'épitaxie VLS localisée. L'étude a confirmé la nécessité de limiter la vitesse de croissance vers 1 µm/h pour conserver une bonne cristallinité du matériau épitaxié. Elle a également mis en évidence l'action directe du champ électromagnétique radiofréquence sur la phase liquide, conduisant à une très forte influence du diamètre des cuvettes gravées sur l'épaisseur du SiC déposé. Un remplissage quasiment complet des cuvettes de 1 µm de profondeur à très fort dopage p++ a été démontré. À partir des couches VLS optimisées, des démonstrateurs de types diodes p+/n- ont été fabriqués. Sur les meilleurs échantillons, sans passivation ni protection périphérique, des tensions de seuil en régime direct (entre 2,5 et 3 V) ont, pour la première fois, été mesurées, sans recourir à un recuit haute température après épitaxie. Elles correspondent aux valeurs attendues pour une vraie jonction p-n sur 4H-SiC. Des densités de courant de plusieurs kA/cm2 ont également pu être injectées pour des tensions situées autour de 5 - 6 V. En régime de polarisation inverse, aucun claquage n'est observé jusqu'à 400 V et les densités de courant de fuite à faible champ électrique dans la gamme 10-100 nA/cm2 ont été mesurées. Toutes ces avancées si situent au niveau de l'état de l'art pour des composants SiC aussi simples, toutes techniques de dopage confonduesThe objective of the VELSIC project has been to demonstrate the feasibility of 1 µm deep p+/n- junctions with high electrical quality in 4H-SiC semiconductor, in which the p++ zone is implemented by an original low-temperature localized epitaxy process ( 1100 - 1200 °C ), performed in the VLS (Vapor - Liquid - Solid) configuration. This innovative epitaxy doping technique uses the monocrystalline SiC substrate as a crystal growth seed. On the substrate (0001-Si) surface, buried patterns of Al - Si stack are fused to form liquid islands which are fed with carbon by C3H8 in the gas phase. This method is investigated as a possible higher performance alternative to the ion implantation process, currently used by all manufacturers of SiC devices, but which still experiences problematic limitations that are yet unresolved to date. Although the main focus of the study has been set on the optimization of localized VLS epitaxy, our works have explored and optimized all the facets of the complete process of test diodes, from the etching of patterns in the SiC substrate up to the electrical I - V characterization of true pn diodes with ohmic contacts on both sides.Our results have confirmed the need to limit the growth rate down to 1 µm/h to maintain good crystallinity of the epitaxial material. It has also highlighted the direct action of the radiofrequency electromagnetic field on the liquid phase, leading to a very strong influence of the diameter of the etched patterns on the thickness of the deposited SiC. A nearly complete filling of the 1 µm deep trenches with very high p++ doping has been demonstrated. Using optimized VLS growth parameters, p+/n- diode demonstrators have been processed and tested. On the best samples, without passivation or peripheral protection, high direct-current threshold voltages, between 2.5 and 3 V, were measured for the first time without any high-temperature annealing after epitaxy. These threshold voltage values correspond to the expected values for a true p-n junction on 4H-SiC. Current densities of several kA/cm2 have also been injected at voltages around 5 - 6 V. Under reverse bias conditions, no breakdown is observed up to 400 V and low leakage current densities at low electric field, in the range 10 - 100 nA/cm2, have been measured. All these advances align with or exceed state-of-the-art results for such simple SiC devices, obtained using any doping technique
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Usman, Muhammad. "Impact of Ionizing Radiation on 4H-SiC Devices." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-60763.
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Electronic components, based on current semiconductor technologies and operating in radiation rich environments, suffer degradation of their performance as a result of radiation exposure. Silicon carbide (SiC) provides an alternate solution as a radiation hard material, because of its wide bandgap and higher atomic displacement energies, for devices intended for radiation environment applications. However, the radiation tolerance and reliability of SiC-based devices needs to be understood by testing devices under controlled radiation environments. These kinds of studies have been previously performed on diodes and MESFETs, but multilayer devices such as bipolar junction transistors (BJT) have not yet been studied. In this thesis, SiC material, BJTs fabricated from SiC, and various dielectrics for SiC passivation are studied by exposure to high energy ion beams with selected energies and fluences. The studies reveal that the implantation induced crystal damage in SiC material can be partly recovered at relatively low temperatures, for damag elevels much lower than needed for amorphization. The implantation experiments performed on BJTs in the bulk of devices show that the degradation in deviceperformance produced by low dose ion implantations can be recovered at 420 oC, however, higher doses produce more resistant damage. Ion induced damage at the interface of passivation layer and SiC in BJT has also been examined in this thesis. It is found that damaging of the interface by ionizing radiation reduces the current gain as well. However, for this type of damage, annealing at low temperatures further reduces the gain. Silicon dioxide (SiO2) is today the dielectric material most often used for gate dielectric or passivation layers, also for SiC. However, in this thesis several alternate passivation materials are investigated, such as, AlN, Al2O3 and Ta2O5. These materials are deposited by atomic layer deposition (ALD) both as single layers and in stacks, combining several different layers. Al2O3 is further investigated with respect to thermalstability and radiation hardness. It is observed that high temperature treatment of Al2O3 can substantially improve the performance of the dielectric film. A radiation hardness study furthermore reveals that Al2O3 is more resistant to ionizing radiation than currently used SiO2 and it is a suitable candidate for devices in radiation rich applications.QC 20120117
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Zeng, Yutong. "Tailored Al2O3/4H-SiC interface using ion implantation." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-90233.
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The effects of ion implantation of Al2O3interface to 4H-SiC epitaxial n- and p-type layers are presented. Different fluencies of carbon and nitrogen ions are used, as well as different annealing processes, with the aim to study the effects of implanted ions at the Al2O3/SiC interface. Capacitance-Voltage (C-V) behavior for fabricated MOS capacitors is studied before and after implantation to determine the effect of the implantation. Terman‟s method was employed to extract the density of interface traps (Dit) present at the Al2O3/SiC interface. Effective oxide charges density (Neff), present inside the Al2O3,was also evaluated by comparing the theoretical (ideal) C-V curve with the experimental C-V curves. It is generally known, and also proved by this study, that Al2O3 on n-type 4H-SiC shows significantly higher effective oxide charges density (Neff) and density of interface traps (Dit=3-4×1012 eV-1cm-2) compared to n-type SiO2/SiC MOS capacitors. However, the analysis of the collected data from N and C implanted n-type Al2O3/SiC samples show Dit values around 2-9×1011 eV-1cm-2, i.e., an effective reduction has been achieved by the ion implantation. The values of Neff for N ion implanted n-type Al2O3/SiC is as high as 1013 cm-2 in some cases, but C implanted n-type Al2O3/SiC sample shows exceptionally low Neff =1.8×1011 cm-2, which is comparable to SiO2/SiC based MOS capacitor. This result suggest that using C ion implantation before the formation of the oxide layer could be a promising approach to improving both oxide and interface properties of n-type 4H-SiC MOS capacitors.
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Karalas, Charilaos-Kimonas. "Process optimization for the 4H-SiC/SiO2 interface." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174842.
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This thesis aims to optimize the process for the 4H-SiC/SiO2 interface formations. The experiments are made on metal-oxide-semiconductor (MOS) structures, where the semiconductor is an n-type epitaxially grown 4H-SiC thin film. The oxide is fabricated either with thermal oxidation, or by using plasma-enhanced chemical vapour deposition (PeCVD), utilising two different tools, Precision 5000 Mark II (P5000) and Plasmalab 80Plus system (Pekka). The deposition temperature is varied for the thermally grown oxide, while power, pressure and gas ratio of N2O/SiH4 is investigated for the PeCVD method. Also the post deposition annealing (PDA) temperature is studied for both techniques. The oxide formation and PDA is done in N2O ambient in order to study the effect of nitrogen passivation of the traps that exist at the interface of 4H-SiC/SiO2. After the dielectric formation the structures are electrically and structurally characterized. The electrical characterization is done by capacitance-voltage (CV) and current-voltage (IV) measurements while the structural characterization is done with atomic force microscopy (AFM). The density of interface traps (Dits) is extracted using the Terman method from CV data. It is observed that the flatband voltage drops almost to zero when the samples are annealed in nitrogen rich ambient, resulting in a more electrically uniform oxide. Also, Dits can also be reduced by nitrogen treatment when the oxide is deposited by the PeCVD technique. However, it appears that the Terman method cannot determine the amount of traps along the entire bandgap and it is clear that a large amount of Dits are still present closer to the conduction band. Finally, it is found that there is a larger spread in the data extracted from the samples deposited by P5000 in comparison to Pekka, indicating that Pekka is a more reliable tool for oxide deposition in SiC substrate.
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Suvanam, Sethu Saveda. "Radiation Hardness of 4H-SiC Devices and Circuits." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-199907.
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Advances in space and nuclear technologies are limited by the capabilities of the conventional silicon (Si) electronics. Hence, there is a need to explore materials beyond Si with enhanced properties to operate in extreme environments. In this regards, silicon carbide (4H-SiC), a wide bandgap semiconductor, provides suitable solutions. In this thesis, radiation effects of 4H-SiC bipolar devices, circuits and dielectrics for SiC are investigated under various radiation types. We have demonstrated for the first time the radiation hardness of 4H-SiC logic circuits exposed to extremely high doses (332 Mrad) of gamma radiation and protons. Comparisons with previously available literature show that our 4H-SiC bipolar junction transistor (BJT) is 2 orders of magnitude more tolerant under gamma radiation to existing Si-technology. 4H-SiC devices and circuits irradiated with 3 MeV protons show about one order of magnitude higher tolerance in comparison to Si. Numerical simulations of the device showed that the ionization is most influential in the degradation process by introducing interface states and oxide charges that lower the current gain. Due to the gain reduction of the BJT, the voltage reference of the logic circuit has been affected and this, in turn, degrades the voltage transfer characteristics of the OR-NOR gates. One of the key advantages of 4H-SiC over other wide bandgap materials is the possibility to thermally grow silicon oxide (SiO2) and process device in line with advanced silicon technology. However, there are still questions about the reliability of SiC/SiO2 interface under high power, high temperature and radiation rich environments. In this regard, aluminium oxide (Al2O3), a chemically and thermally stable dielectric, has been investigated. It has been shown that the surface cleaning treatment prior to deposition of a dielectric layer together with the post dielectric annealing has a crucial effect on interface and oxide quality. We have demonstrated a new method to evaluate the interface between dielectric/4H-SiC utilizing an optical free carrier absorption technique to quantitative measure the charge carrier trapping dynamics. The radiation hardness of Al2O3/4H-SiC is demonstrated and the data suggests that Al2O3 is better choice of dielectric for devices in radiation rich applications.QC 20170119
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Padavala, Balabalaji. "Epitaxy of boron phosphide on AIN, 4H-SiC, 3C-SiC and ZrB₂ substrates." Diss., Kansas State University, 2016. http://hdl.handle.net/2097/32808.
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Doctor of PhilosophyDepartment of Chemical Engineering
James H. Edgar
The semiconductor boron phosphide (BP) has many outstanding features making it attractive for developing various electronic devices, including neutron detectors. In order to improve the efficiency of these devices, BP must have high crystal quality along with the best possible electrical properties. This research is focused on growing high quality crystalline BP films on a variety of superior substrates like AIN, 4H-SiC, 3C-SiC and ZrB₂ by chemical vapor deposition. In particular, the influence of various parameters such as temperature, reactant flow rates, and substrate type and its crystalline orientation on the properties of BP films were studied in detail. Twin-free BP films were produced by depositing on off-axis 4H-SiC(0001) substrate tilted 4° toward [1-100] and crystal symmetry matched zincblende 3C-SiC. BP crystalline quality improved at higher deposition temperature (1200°C) when deposited on AlN, 4H-SiC, whereas increased strain in 3C-SiC and increased boron segregation in ZrB₂ at higher temperatures limited the best deposition temperature to below 1200°C. In addition, higher flow ratios of PH₃ to B₂H₆ resulted in smoother films and improved quality of BP on all substrates. The FWHM of the Raman peak (6.1 cm⁻¹), XRD BP(111) peak FWHM (0.18°) and peak ratios of BP(111)/(200) = 5157 and BP(111)/(220) = 7226 measured on AlN/sapphire were the best values reported in the literature for BP epitaxial films. The undoped films on AlN/sapphire were n-type with a highest electron mobility of 37.8 cm²/V·s and a lowest carrier concentration of 3.15x1018 cm⁻ᶟ. Raman imaging had lower values of FWHM (4.8 cm⁻¹) and a standard deviation (0.56 cm⁻¹) for BP films on AlN/sapphire compared to 4H-SiC, 3C-SiC substrates. X-ray diffraction and Raman spectroscopy revealed residual tensile strain in BP on 4H-SiC, 3C-SiC, ZrB₂/4H-SiC, bulk AlN substrates while compressive strain was evident on AlN/sapphire and bulk ZrB₂ substrates. Among the substrates studied, AlN/sapphire proved to be the best choice for BP epitaxy, even though it did not eliminate rotational twinning in BP. The substrates investigated in this work were found to be viable for BP epitaxy and show promising potential for further enhancement of BP properties.
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Moghadam, Hamid Amini. "Quantified Characterization of Active Defects in 4H–SiC MOS Devices." Thesis, Griffith University, 2016. http://hdl.handle.net/10072/366432.
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According to the U.S. Energy Information Administration (EIA), global energy demand is expected to increase considerably in the coming years as the result of population growth and economic development [1]. The vast majority of the world’s energy is generated from non-renewable sources, specifically oil, coal and natural gas. The increased volumes of carbon dioxide and other greenhouse gases released by burning these fossil fuels are believed to be the primary sources of global warming and the long term climate changes [2]. Furthermore, global warming is considered to be the greatest humanitarian crisis of our time, responsible for raising sea levels, raging storms, ferocious fires, and severe drought [3]. Electricity is mainly considered to be an environmentally friendly source of energy. However, electricity is largely generated by burning fossil fuels in power plants. This process releases substantial amounts of carbon dioxide in the earth’s atmosphere. Therefore, it is very important to utilize the generated electricity in an efficient way in order to reduce greenhouse gas emissions and ultimately the climate change effects.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
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Lin, Huang-De Hennessy. "Low-temperature halo-carbon homoepitaxial growth of 4H-SiC." Diss., Mississippi State : Mississippi State University, 2008. http://library.msstate.edu/etd/show.asp?etd=etd-10142008-150935.
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Ektarawong, Annop. "Growth and characterization of graphene on 4H-SiC(0001)." Thesis, Linköpings universitet, Halvledarmaterial, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-82014.
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Thermal annealing 4H-SiC(0001) substrates to produce epitaxial graphene on Si-terminated SiC was performed using five different procedures, i.e. direct and indirect current heating at different based pressures and a temperature of about 1300 . The aim is to study the effects of graphene growth under different conditions and also to produce large homogeneous graphene. To investigate the prepared samples, two surface analytical techniques, i.e. low energy electron microscopy (LEEM) and photoelectron spectroscopy (PES) have been used. LEEM was first used to observe the surface morphologies of the prepared samples. In combination with LEEM instrument, low energy electron diffraction (LEED) was used to verify the existence of graphene on SiC substrate. The number of graphene layer was determined by collecting electron reflectivity at different electron energies. The number of dips observed in the electron reflectivity curve corresponds to the number of graphene layer. The experimental results obtained from LEEM and LEED have demonstrated that a film consisting of fairly large domains of 1 and 2 monolayer (ML) graphene was obtained by direct current heating of SiC under high vacuum (HV) condition with the based pressure of 10-6 Torr. A domain size in the range of up to about 5 to 10 μm have been observed. Meanwhile another graphene film prepared by the same method and the same temperature but under ultra high vacuum (UHV) condition with the based pressure of 10-10 Torr has much smaller domain size of 1 ML graphene compared to that grown under HV condition. We therefore suggested that the based pressure during the graphene growth has a strong influence on the morphology of graphene. This is because the Si evaporation rate is suppressed when heated in a high pressure environment, which normally leads to the improvement of the surface quality. The suppression of the Si evaporation rate has also been verified by a result obtained from the other sample directly heated under much higher based pressure, i.e. in an argon (Ar) environment of 1 atm. In addition to LEEM and LEED, the existence of graphene on SiC substrate has also been verified by the PES measurement. The C1s spectrum of graphene sample grown on SiC(0001) substrate showed three components, i.e. bulk SiC, graphene (G) and the buffer layer (B) located at 283.7 eV, 284.5 eV and 285.1 eV, respectively. The intensity ratios of the three components in the C1s spectrum were also used to estimate the number of graphene layer. The estimated number of graphene layer corresponds to the result obtained from LEEM.
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Kwasnicki, Pawel. "Evaluation of doping in 4H-SiC by optical spectroscopies." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20145/document.
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Ce travail porte sur la caractérisation optique d'échantillons de 4H-SiC. Les échantillons étudiés ont été répartis en deux groupes : type-n et type-p. La croissance des épitaxies a été réalisée par CVD technique utilisant horizontal, paroi chaude, chauffée par résistance, en utilisant de l'hydrogène comme gaz porteur silane et/propane en tant que précurseurs de Si/C respectivement. Pour atteindre différents dopages : N2 pour le n-type et TMA pour de type p ont été utilisés. Les échantillons ont été étudiés par photoluminescence en basse température, micro-Raman and spectroscopies de masse d'ions secondaires. Pour les échantillons de type-p mesures d'effet Hall ont été utilisés pour déterminer la concentration de porteurs. Avec l'aide de ces techniques, il a été possible de déterminer le niveau de dopage dans une très large gamme pour les deux types. Les deux spectroscopies : Raman et LTPL peut donner des informations sur la concentration, polytype, qualité du cristal et concentration de porteurs, mais seulement LTPL fournit des informations sur la compensation et est indispensable de définir la polarité. Pour les échantillons faiblement dopés les meilleures façons de déterminer le niveau de dopage semble être des mesures LTPL. Pour les échantillons fortement dopés on a remarqué l'avantage de Raman, qui permet de déterminer la concentration en porteurs jusqu'à 10^20cm-3. Enfin en utilisant les mesures électriques et de Fano-paremeters obtenus grâce à micro-Raman, nous avons fait la courbe d'étalonnage pour type p 4H-SiCThe main topic of this thesis is the optical characterization of 4H-SiC samples. The samples were divided in 2 groups: type-n doped with nitrogen and type-p doped with aluminum. Samples were grown by CVD method performed in a horizontal, hot wall, resistively heated, using hydrogen as a carrier gas and silane/propane as Si/C precursors respectively. To achieve different doping N2 for n-type and TMA for p-type were used. The samples were studied by three different spectroscopies techniques: low temperature photoluminescence, micro-Raman and secondary ion mass spectroscopies. For p-type samples Hall effect measurements were used to determine carrier concentration. With the help of this techniques it was possible to determine doping level in a very large range for both types. Both LTPL and Raman spectroscopy can give information about the polytype, crystal quality and carrier concentration but only LTPL provides information about compensation and is indispensable to define the polarity. For low doped samples since the LOPC & FTA modes of Raman spectra do not exhibit any significant changes the best ways seems to be LTPL measurements. For the highest doped samples notice the advantage of Raman which allows to determine the carrier concentration up to 10^20cm-3. Finally due to electrical measurements and fano-paremeters obtained by micro-Raman spectra we made calibration curve for p –type 4H-SiC
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Domeij, Martin. "Dynamic avalanche in Si and 4H-SiC power diodes /." Stockholm, 1999. http://www.lib.kth.se/abs99/dome0604.pdf.
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Solomon, Ruth Reena. "Fabrication and characterization of Cu/4H-SiC Schottky diodes." Connect to this title online, 2007. http://etd.lib.clemson.edu/documents/1193079981/.
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Benjamin, Helen N. "Non-contact characterization of dielectric conduction on 4H-SiC." [Tampa, Fla] : University of South Florida, 2009. http://purl.fcla.edu/usf/dc/et/SFE0002984.
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Jiang, Chennan. "Damage accumulation and recovery in Xe implanted 4H-SiC." Thesis, Poitiers, 2018. http://www.theses.fr/2018POIT2251/document.
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Le carbure de silicium (SiC) est un matériau qui est considéré comme un semi-conducteur à large bande interdite ou une céramique suivant ses applications en microélectronique ou comme matériau nucléaire. Dans ces deux domaines d'application les défauts générés par l'implantation/irradiation d'ions (dopage, matériau de structure) doivent être contrôlés. Ce travail est une étude des défauts générés par l'implantation de gaz rares suivant les conditions d'implantation (fluence et température). La déformation élastique a plus particulièrement été étudiée dans le cas d'implantation de xénon à des températures pour lesquelles la recombinaison dynamique empêche la transition amorphe. Un modèle phénoménologique basé sur le recouvrement des cascades a été proposé pour comprendre l'évolution de la déformation maximale avec la dose. Des observations complémentaires en particulier par microscopie électronique à transition nous ont permis de préciser la nature des défauts créés et d'étudier leur évolution sous recuit. La formation de cavités a été observée pour des conditions sévères d'implantation/recuit ; ces cavités sont de nature différente (vide ou pleine) suivant la répartition du xénon. Cette étude est également reliée aux propriétés de gonflement sous irradiation, gonflement qui doit être anticipé dans les domaines d'application du SiCSilicon carbide is a material that can be considered as a wide band gap semiconductor or as a ceramic according to its applications in microelectronics and in nuclear energy system (fission and fusion). In both fields of application defects or damage induced by ion implantation/ irradiation (doping, material structure) should be controlled. This work is a study of defects induced by noble gas implantation according to the implantation conditions (fluence and temperature). The elastic strain buildup, particularly in the case of xenon implantation, has been studied at elevated temperatures for which the dynamic recombination prevents the amorphization transition. A phenomenological model based on cascade recovery has been proposed to understand the strain evolution with increasing dose and for different noble gases. In addition, with the help of transmission electron microscopy the evolution of defects under subsequent annealing was studied. The formation of nanocavities was observed under severe implantation/annealing conditions. These cavities are of different nature (full of gas or empty) according to the xenon and damage distribution. This study is also linked to swelling properties under irradiation that should be projected in the SiC application fields
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Freda, Albanese Loredana. "Characterization, modeling and simulation of 4H-SiC power diodes." Doctoral thesis, Universita degli studi di Salerno, 2011. http://hdl.handle.net/10556/217.
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2009 - 2010Exploring the attractive electrical properties of the Silicon Carbide (SiC) for power devices, the characterization and the analysis of 4H-SiC pin diodes is the main topic of this Ph.D. document. In particular, the thesis concerns the development of an auto consistent, analytical, physics based model, created for accurately replicating the power diodes behavior, including both on-state and transient conditions. At the present, the fabrication of SiC devices with the given performances is not completely obvious because of the lack of knowledge still existing in the physical properties of the material, especially of those related to carrier transport and of their dependences on process parameters. Among these, one can cite the degree of doping activation, the carrier lifetime into epitaxial layers that will be employed and the sensitivity of some physical parameters to temperature changes. Therefore, a set of investigative tools, designed especially for SiC devices, cannot be regarded as secondary objective. It will be useful both for process monitoring, becoming essential to the tuning of technological processes used for the implementation of the final devices, and for a proper diagnostics of the realized devices. Following this need, in our research activity firstly a predictive, static analytical model, including temperature dependence, is developed. It is able to explain the carrier transport in diffused regions as function of the injection level and turns also useful for better understanding the influence of physical parameters, which depend in a significant way from the processed material, on device performances. The model solves the continuity equation in double carrier conditions, taking into account the effects due to varying doping profile of the junction, the spatial dependence of physical parameters on both doping and injection level and the modification of the electric field of the region with the injection regime. The model includes also the device characterization at high temperatures to analyze the influence of thermal issues on the overall behavior up to temperature of 250°C. The accuracy of the static model has been extensively demonstrated by numerous comparisons with numerical results obtained by the SILVACO commercial simulator. Secondly, with the aim to properly account for the dynamic electrical behavior of a diode with generic structure, the static model has been incorporated in a more general, self-consistent model, allowing the analysis of the device behavior when it is switched from an arbitrary forward-bias condition. In particular, the attention is focused on an abrupt variation of diode voltage due to an instantaneous interruption of the conduction current: although this situation is notably interesting for the study of the switching behavior of diodes, the voltage transitory is also traditionally used in different techniques of investigation to extract more information about the mean carrier lifetime. This occurs, for example, in the conventional Open Circuit Voltage Decay (OCVD) technique, where the voltage decay due to the current interruption is useful for an indirect measure of minority carrier lifetime in the epitaxial layer. Because of its heavy dependence on processes, the carrier lifetime is an important parameter to be monitored, especially in the case of bipolar devices, and it cannot be neglected. Due to the existent uncertainty about this parameter in SiC epi-layers, the OCVD method reveals itself a practical way to overcoming this limit. In detail, by using our self-consistent model, that exploits an improved method of the traditional OCVD technique, it is possible to characterize the carrier lifetime into 4H-SiC epitaxial layer of a generic diode under test, obtaining the spatial distributions of the minority carrier concentration and carrier lifetime at any injection regime. The overall model performances are compared to both device simulations and experimental results performed on Si and 4H-SiC rectifier structures with various physical and electrical characteristics. From the comparisons, the model results to have good predictive capabilities for describing the spatial–temporal variation of carriers and currents along the whole epi-layer, proving contextually the validity of the used approximations and allowing also to resolve some ambiguities reported in the literature, such as the stated inapplicability of the OCVD method on thick epitaxial layers, the reasons of the observed non linear decay of the voltage with time, and the effects of junction properties on voltage transient. Finally, with the imposition of right boundary conditions, it is possible to use the versatility of the developed model for extending the analysis and obtaining a physical insight of any arbitrary switching condition of 4H-SiC power diodes. [edited by author]
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Song, Xi. "Activation des dopants implantés dans le carbure de silicium (3C-SiC et 4H-SiC)." Thesis, Tours, 2012. http://www.theses.fr/2012TOUR4019/document.
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Ces travaux de thèse sont consacrés à l’étude de l’activation des dopants implantés dans le carbure de silicium. L’objectif est de proposer des conditions d’implantation optimisées pour réaliser le dopage de type n dans le 3C-SiC et de type p dans le 4H-SiC.Nous avons tout d’abord étudié les implantations de type n dans le 3C-SiC. Pour cela, des implantations de N, de P et une co-implantation N&P avec les recuits d’activation associés ont été étudiés. L’implantation d’azote suivie d’un recuit à 1400°C-30min a permis une activation proche de 100% tout en conservant une bonne qualité cristalline. Une étude sur les propriétés électriques des défauts étendus dans le 3C-SiC a également été réalisée. A l’aide de mesures SSRM, nous avons mis en évidence l’activité électrique de ces défauts, ce qui rend difficile la réalisation de composants électroniques sur le 3C-SiC.Nous avons ensuite réalisé une étude du dopage de type p par implantation d’Al dans le 4H-SiC, en fonction de la température d’implantation et du recuit d’activation. Nous avons pu montrer qu’une implantation à 200°C suivie d’un recuit à 1850°C-30min donne les meilleures résultats en termes de propriétés physiques et électriquesThis work was dedicated to the activation of implanted dopants in 3C-SiC and 4H-SiC. The goal is to propose optimized process conditions for n-type implantation in 3C-SiC and for p-type in 4H-SiC.We have first studied the n-type implantation in 3C-SiC. To do so, N, P implantations, N&P co-implantation and the associated annealings were performed. The nitrogen implanted sample, annealed at 1400°C-30 min evidences a dopant activation rate close to 100% while maintaining a good crystal quality. Furthermore, the electrical properties of extended defects in 3C-SiC have been studied. Using the SSRM measurements, we have evidenced for the first time that these defects have a very high electrical activity and as a consequence on future devices.Then, we have realized a study on p-type doping by Al implantation in 4H-SiC with different implantation and annealing temperatures. Al implantation at 200°C followed by an annealing at 1850°C-30min lead to the best results in terms of physical and electrical properties
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Shin, Yun ji. "Étude du procédé de croissance en solution à haute température pour le développement de substrats de 4H-SiC fortement dopes." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAI058/document.
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Le carbure de silicium est un semi-conducteur à grand gap qui s’est récemment imposé comme un matériau clé pour l’électronique de puissance. Les cristaux massifs ainsi que les couches épitaxiales actives sont aujourd’hui obtenus par des procédés en phase gazeuse, comme la croissance par sublimation (ou PVT) et le dépôt chimique en phase gazeuse (CVD), respectivement. Le procédé de croissance en solution à haute température est actuellement revisité en raison de sa capacité à atteindre des qualités cristallines exceptionnelles. Ce travail est une contribution au développement du procédé de croissance en solution à partir d’un germe (TSSG), avec comme objectif principal l’accès à des cristaux de 4H-SiC fortement dopés de type p. Le dopant p le plus utilisé est l’Aluminium. Différentes étapes élémentaires du procédé sont étudiées, avec pour chaque étape l’évaluation de l’effet de l’Al. Après un bref rappel historique sur le SiC, les données fondamentales du SiC sont introduites dans le chapitre 1 et discutées par rapport aux applications en électronique de puissance. Dans le chapitre 2, le réacteur de croissance est détaillé. Les trois principaux aspects techniques du procédé sont exposés : i) l’apport en carbone par dissolution à l’interface entre le creuset en graphite et le liquide, ii) le transport du carbone de la zone de dissolution à la zone de cristallisation, et iii) la cristallisation sur le germe. Ces trois aspects ont été étudiés et améliorés par l’ajout de métaux de transition (Fe ou Cr) au solvant de façon à augmenter la solubilité en carbone, en favorisant le transport du carbone par l’optimisation de la convection forcée (i.e. la rotation du cristal) et en stabilisant le front de croissance. Après optimisation, un cristal de 4H-SiC a pu être obtenu à une vitesse supérieure à 300 µm/hr et avec un élargissement du diamètre d’environ 41% par rapport au diamètre initial du germe. Le chapitre 3 porte sur l’étude de l’interaction entre le solvant et la surface du 4H-SiC à l’équilibre, sans croissance, en utilisant la méthode de la goutte posée. L’effet du temps, de la température et de l’ajout d’Al ont été étudiés. L’interface liquide/solide présente une évolution en trois étapes : i) dissolution, ii) step-bunching et iii) facettage, la surface initiale en marches et terrasses se décomposant en facettes de type (0001), (10-1n) et (01-1n). L’augmentation de la température de 1600°C à 1800°C provoque le même effet que l’ajout d’aluminium : une accélération de la deuxième étape ainsi qu’une limitation de la troisième étape. Dans le chapitre 4, des phénomènes transitoires ont été étudiés lorsque le substrat touche la surface du liquide. A l’instant du contact, il a été démontré par simulation numérique que le liquide au voisinage du substrat est sujet à de très fortes fluctuations de températures et donc à de fortes fluctuations de sursaturation. Ceci est à l’origine d’une germination transitoire de 3C-SiC sur la surface du cristal et ce, même à très haute température. Ce phénomène peut être évité soit en préchauffant le cristal avant le contact soit en ajoutant de l’aluminium dans le liquide. L’amélioration de la convection forcée est un moyen efficace pour augmenter la vitesse de croissance. Cependant, au-delà d’une certaine vitesse de rotation du cristal, un type d’instabilité spécifique se développe. Elle est basée sur l’interaction entre la direction d’avancée de marches à la surface du cristal et la direction locale du flux de liquide au voisinage de la surface. Ceci fait l’objet du chapitre 5. Finalement, la concentration de porteurs ainsi que la concentration totale en azote (N) et en aluminium (Al) sont étudiées en fonction de différents paramètres de croissance dans le chapitre 6. Une concentration en Al aussi élevée que 5E+20 at/cm3 a pu être obtenue à 1850°C. Cette valeur est très prometteuse pour le futur développement de substrats de 4H-SiC de type p+Silicon Carbide is a wide band gap semiconductor which has recently imposed as a key material for modern power electronics. Bulk single crystals and active epilayers are industrially produced by vapor phase processes, namely seeded sublimation growth (PVT) and chemical vapor deposition (CVD) respectively. The high temperature solution growth is currently being revisited due to its potential for achieving high structural quality. This work is a contribution to the development of the top seeded solution growth (TSSG) process, with a special focus on heavily p-type doped 4H-SiC crystals. Aluminum (Al) is the most commonly used acceptor in SiC. Different elementary steps of the process are studied, and for every cases, the effect of Al is considered and discussed. After a brief history of SiC material, basic structural and physical properties of silicon carbide are introduced in chapter 1 and discussed with respect to power electronics applications. In chapter 2, the crystal growth puller is detailed and the three most important technical issues of the SiC solution growth process are discussed : i) carbon supply by dissolution at the graphite crucible/liquid interface, ii) carbon transport from the dissolution area to the growth front, and iii) crystallization on the seed substrate. These three steps are studied and improved by adding transition metals (Fe or Cr) to the solvent in order to increase the carbon solubility, by increasing the carbon transport with the optimization of the forced convection (i.e. rotation of the crystal) and by stabilizing the growth front. After optimization, a 4H-SiC crystal is demonstrated with a growth rate of over 300 µm/h and a diameter enlargement of about 41% compared to the original seed size. Chapter 3 is dedicated to the investigation of the interaction between the liquid solvent and the 4H-SiC surface under equilibrium conditions, i.e. without any growth, using a sessile drop method. Effect of time, temperature and the addition of Al to pure liquid silicon are investigated. It is shown that the liquid/solid exhibits a three stages evolution: i) dissolution, ii) step bunching and iii) faceting, the original step and terrace structure being decomposed into (0001), (10-1n) and (01-1n) facets. Increasing the temperature from 1600°C to 1800°C or adding Al drastically enhances the second stage, but reduces the third one. In chapter 4, transient phenomena during the seeding stage of the growth process on the seed crystal are investigated. With the help of numerical modeling, it is shown that strong temperature fluctuations during the contact between the seed and the liquid can give rise to transient 3C-SiC nucleation on the crystal surface, even at high temperatures. This phenomenon can be avoided by either pre-heating the seed or by adding Al. Increasing forced convection (rotation rate of the crystal) is a good way to increase the growth rate. However, above a critical rotation rate, a special surface instability develops. It is based on the interaction between the step flow at the growing surface and the local fluid flow directions close to the surface. This is investigated in Chapter 5. Finally, carrier concentrations and total dopant (nitrogen and aluminum) concentrations are investigated as a function of different process parameters in chapter 6. Al incorporation as high as 5E+20 at/cm3 has been achieved in layers grown at 1850°C. This value is very promising for the future development of p+ 4H-SiC substrates
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Österman, John. "Characterization of electrical properties in 4H-SiC by imaging techniques." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-64.
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4H-SiC has physical properties supremely suited for a variety of high power, high frequency and high temperature electronic device applications. To fully take advantage of the material's potential, several problems remain to be solved. Two of the most important are (1) the characterization and understanding of crystallographic defects and their electrical impact on device performance, and (2) the introduction of acceptor dopants, their activation and control of the final distribution of charge carriers. Two main experimental methods have been employed in this thesis to analyze 4H-SiC material with respect to the issues (1) and (2): electron beam induced current (EBIC) and scanning spreading resistance microscopy (SSRM), respectively.
EBIC yields a map of electron-hole-pairs generated by the electron beam of a scanning electron microscope and collected in the depleted region around a junction. EBIC is conducted in two modes. In the first mode the EBIC contrast constitutes a map of minority carrier diffusion lengths. Results from these measurements are compared to white beam syncrotron x-ray topography and reveal a one-to-one correlation between lattice distortions and the electron diffusion length in n+p 4H-SiC diodes. In the second EBIC mode, the junction is highly reverse biased and local avalanche processes can be studied. By correlating these EBIC results with other techniques it is possible to separate defects detrimental to device performance from others more benign.
SSRM is a scanning probe microscopy technique that monitors carrier distributions in semiconductors. The method is for the first time successfully applied to 4H-SiC and compared to alternative carrier profiling techniques; spreading resistance profiling (SRP), scanning electron microscopy (SEM) and scanning capacitance microscopy (SCM). SCM successfully monitors the doping levels and junctions, but none of these techniques fulfill the requirements of detection resolution, dynamic range and reproducibility. The SSRM current shows on the other hand a nearly ideal behavior as a function of aluminum doping in epitaxially grown samples. However, the I-V dependence is highly non-linear and the extremely high currents measured indicate a broadening of the contact area and possibly an increased ionization due to sample heating. Finite element calculations are performed to further elucidate these effects.
SSRM is also applied to characterize Al implantations as a function of anneal time and temperature. The Al doping profiles are imaged on cleaved cross-sections and the measured SSRM current is integrated with respect to depth to obtain a value of the total activation. The evaluation of the annealing series shows a continuous increase of the activation even up to 1950 °C. Other demonstrated SSRM applications include local characterization of electrical field strength in passivating layers of Al2O3, and lateral diffusion and doping properties of implanted boron.
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Rong, Hua. "Development of 4H-SiC power MOSFETs for high voltage applications." Thesis, University of Warwick, 2015. http://wrap.warwick.ac.uk/79426/.
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Silicon carbide is a promising wide bandgap semiconductor for high-power, high-temperature and high frequency devices, owing to its high breakdown electric field strength, high thermal conductivity and ability to grow high quality SiO2 layers by thermal oxidation. Although the SiC power MOSFET (metal-oxide-semiconductor field effect transistor) is preferred as a power switch, it has suffered from low channel mobility with only single digit field effect mobility achieved using standard oxidation process (1200◦C thermal oxidation). As such, this thesis is focussed on the development of 4H-SiC MOSFETs (both lateral and vertical MOSFETs) to improve the channel mobility and breakdown characteristics of these devices. In this work, high temperature nitridation using N2O has been investigated on MOS capacitors and MOSFETs, both with gate oxides grown directly in N2O environment or in a O2 ambient followed by a N2O post-oxidation annealing process. Results have demonstrated that at high temperature (>1200◦C) there is a significant improvement in the interface trap density to as low as (1.5x10^11cm-2eV-1) and field effect channel mobility (19cm2/V.s) of 4H-SiC MOSFET compare with a lower temperature (between 800 and 1200◦C) oxidation (1x10^12cm-2eV-1 and 4cm2/V.s). Nitridation temperatures of 1300◦C was found to be the most effective method for increasing the field effect channel mobility and reducing threshold voltage. The number of working devices per sample also increased after N2O nitridation at 1300◦C as observed for both lateral and vertical MOSFETs. Other post oxidation techniques have also been investigated such as phosphorous passivation using solid SiP2O7 planar diffusion source (PDS). The peak value of the field effect mobility for 4H-SiC MOSFET after phosphorus passivation is approximately 80cm2/V.s, which is four times more than the valued obtained using high temperature N2O annealing. Different JTE structures have been designed and simulated including single-zone JTE, space modulated JTE (SMJTE) and the novel two-step mesa JTE structures. It was found that for the same doping concentration the SM two-zone JTE and SMJTE have higher breakdown voltage than the single zone JTE. With SMJTE, the device could achieve more than 90% of the ideal parallel plane voltage from simulations and 86% from the breakdown test of the fabricated devices.
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Wolborski, Maciej. "Characterization of dielectric layers for passivation of 4H-SiC devices." Doctoral thesis, Stockholm : Laboratory of Solid State Electronics, Department of Microelectronics and Applied Physics, Royal Institute of Technology (KTH), 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4229.
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Virojanadara, Chariya. "Studies of surface and interface properties of 4H-SiC/SiO₂ /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek890s.pdf.
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Morrison, Dominique Johanne. "The fabrication and characterisation of 4H-SiC Schottky barrier diodes." Thesis, University of Newcastle Upon Tyne, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.324784.
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Mohammadi, Zohreh. "Design, simulation, fabrication and characterisation of 4H-SiC trench MOSFETs." Thesis, University of Warwick, 2018. http://wrap.warwick.ac.uk/109953/.
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For solid-state power devices, there exists need for a material with a higher band gap which will result in a higher critical electric field, improved power efficiency and thermal performance. This has resulted in the use of Silicon Carbide (SiC) as a serious alternative to Silicon for power devices. SiC trench MOSFETs have attracted major attention in recent years because of 1) lower on resistance by eliminating the JFET effect which exists in lateral MOSFETs, 2) higher channel density which lowers the threshold voltage and 3) reduction of the required surface area because of the vertical channel. These advantages allow faster switching speeds and the potential for a higher density of devices leading to more compact modules. This work was focused on fabrication of the first generation of 4H-SiC trench MOSFETs in Warwick University. Two main goals were achieved in this work: a comprehensive understanding of fabrication of trenches in 4H-SiC and fabrication of first generation of 4H-SiC trench MOSFET with mobility as high as 35.
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Fisher, Craig A. "Development of 4H-SiC PiN diodes for high voltage applications." Thesis, University of Warwick, 2014. http://wrap.warwick.ac.uk/62126/.
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Despite the excellent electrical and thermal properties of 4H-silicon carbide (SiC), the fabrication of high-voltage SiC power devices is still proving problematic, being hindered by material defects resulting in low carrier lifetimes and forward voltage drift, and suboptimum ohmic contacts to p-type material. The PiN diode is one such device that suffers from the aforementioned problems, though at the same time is sought after for high voltage power electronics applications due to the prospect of greatly reduced power losses and increased power handling capability than the Si devices currently in use. As such, this thesis is focussed on the development of these devices, investigating various device structures to achieve high reverse blocking voltages as well as developing novel fabrication processes to improve the electrical performance of the devices. Electrical characterisation of ohmic contacts to p-type 4H-SiC showed that Ti/Al-based metal schemes offered the lowest specific contact resistivity of approximately 2.2 x 10-6 Ω-cm2, which was achieved after annealing at 1000°C for 2 minutes. Physical analysis showed that these annealing conditions were optimum for formation of the Ti3SiC2 alloy at the metal-semiconductor interface, the presence of which was found to correlate with lower specific contact resistivity values. Electrical characterisation of first generation PiN diodes designed for blocking 3.3 kV showed that the fabricated devices had a differential on-resistance (Ron,dif f) of 17 Ωm -cm2 at 100 A/cm2 and 25°C, and near-ideal (η = 1.3) characteristics in the diffusion current regime. Based on the measured reverse saturation currents, the carrier lifetime of the fabricated devices was estimated to be 480 ns. Reverse leakage currents were found to vary significantly across the devices, from 5 nA/cm2 up to 200 μA/cm2 at 100 V reverse bias and 25°C. Second generation 3.3 kV PiN diodes, which featured a B-implanted JTE structure, were found to block a maximum reverse voltage of 2.8 kV, which was around 85% of the target value. PiN diodes fabricated with a drift region designed for blocking 10 kV underwent thermal oxidation processes at temperatures ranging from 1400°C to 1600°C in order to increase the carrier lifetime. Devices having undergone no lifetime enhancement treatment were found to have a Ron,dif f of 11.6 mΩ-cm2 at 100 A/cm2 and 25°C, and an ideality factor η = 1.5 in the diffusion current regime. PiN diodes that had undergone thermal oxidation were found to have improved forward characteristics, with devices oxidised at 1500°C exhibiting a Ron,dif f of around 9 mΩ-cm2 at 100 A/cm2 and 25°C, an improvement of nearly 25%. A novel combined thermal oxidation and annealing process was developed and applied to second generation 10 kV PiN diodes; a mean Ron,dif f of 4.45 mΩ-cm2 was achieved, and a carrier lifetime of 1.21 μs was extracted from reverse recovery characteristics; these were both significant improvements on both the second generation control sample and the first generation thermally oxidised PiN diodes.
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Rajgopal, Srihari. "FABRICATION AND CHARACTERIZATION OF 4H-SiC JFET-BASED INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case154350167704502.
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Elahipanah, Hossein. "Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors." Doctoral thesis, KTH, Elektronik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-211659.
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4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development. To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized. Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process. Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated. This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.QC 20170810
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Tsirimpis, Athanasios [Verfasser], and Heiko [Gutachter] Weber. "Investigation of Implanted Boron in 4H-SiC and Iron in 3C-SiC and Experimental/Theoretical Analysis of the Depletion Zone in 4H-SiC MOS Capacitors / Athanasios Tsirimpis ; Gutachter: Heiko Weber." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2018. http://d-nb.info/1155590627/34.
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Chanda, Sashi Kumar. "INVESTIGATION OF DEFECTS IN N-TYPE 4H-SIC AND SEMI-INSULATING 6H-SIC USING PHOTOLUMINESCENCE SPECTROSCOPY." MSSTATE, 2005. http://sun.library.msstate.edu/ETD-db/theses/available/etd-07072005-102232/.
Full textAbstract:
Photoluminescence spectroscopy is one of the most efficient and sensitive non-contact techniques used to investigate defects in SiC. In this work, room temperature photoluminescence mapping is employed to identify different defects that influence material properties. The correlation of the distribution of these defects in n-type 4H-SiC substrates with electronic properties of SiC revealed connection between the deep levels acting as efficient recombination centers and doping in the substrate. Since deep levels are known to act as minority carrier lifetime killers, the obtained knowledge may contribute to our ability to control important characteristics such as minority carrier lifetime in SiC. In semi-insulating (SI) 6H-SiC, the correlation between room temperature infrared photoluminescence maps and the resistivity maps is used to identify deep defects responsible for semi-insulating behavior of the material. Different defects were found to be important in different families of SI SiC substrates, with often more than one type of defect playing a significant role. The obtained knowledge is expected to enhance the yield of SI SiC fabrication and the homogeneity of the resistivity distribution across the area of large SiC substrates.
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Alexandru, Mihaela. "4H-SiC Integrated circuits for high temperature and harsh environment applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2013. http://hdl.handle.net/10803/129635.
Full textAbstract:
Silicon Carbide (SiC) has received a special attention in the last decades thanks to its superior electrical, mechanical and chemical proprieties. SiC is mostly used for applications where Silicon is limited, becoming a proper material for both unipolar and bipolar power device able to work under high power, high frequency and high temperature conditions. Aside from the outstanding theoretical and practical advantages still to be proved in SiC devices, the need for more accurate models for the design and optimization of these devices, along with the development of integrated circuits (ICs) on SiC is indispensable for the further success of modern power electronics.
The design and development of SiC ICs has become a necessity since the high temperature operation of ICs is expected to enable important improvements in aerospace, automotive, energy production and other industrial systems. Due to the last impressive progresses in the manufacturing of high quality SiC substrates, the possibility of developing ICs applications is now feasible. SiC unipolar transistors, such as JFETs and MESFETs show a promising potential for digital ICs operating at high temperature and in harsh environments.
The reported ICs on SiC have been realized so far with either a small number of elements, or with a low integration density. Therefore, this work demonstrates that by means of our SiC MESFET technology, multi-stage digital ICs fabrication containing a large number of 4H-SiC devices is feasible, accomplishing some of the most important ICs requirements. The ultimate objective is the development of SiC digital building blocks by transferring the Si CMOS topologies, hence demonstrating that the ICs SiC technology can be an important competitor of the Si ICs technology especially in application fields in which high temperature, high switching speed and harsh environment operations are required.
The study starts with the current normally-on SiC MESFET CNM complete analysis of an already fabricated MESFET. It continues with the modeling and fabrication of a new planar-MESFET structure together with new epitaxial resistors specially suited for high temperature and high integration density. A novel device isolation technique never used on SiC before is approached. A fabrication process flow with three metal levels fully compatible with the CMOS technology is defined. An exhaustive experimental characterization at room and high temperature (300ºC) and Spice parameter extractions for both structures are performed.
In order to design digital ICs on SiC with the previously developed devices, the current available topologies for normally-on transistors are discussed. The circuits design using Spice modeling, the process technology, the fabrication and the testing of the 4H-SiC MESFET elementary logic gates library at high temperature and high frequencies are performed. The MESFET logic gates behavior up to 300ºC is analyzed. Finally, this library has allowed us implementing complex multi-stage logic circuits with three metal levels and a process flow fully compatible with a CMOS technology.
This study demonstrates that the development of important SiC digital blocks by transferring CMOS topologies (such as Master Slave Data Flip-Flop and Data-Reset Flip-Flop) is successfully achieved. Hence, demonstrating that our 4H-SiC MESFET technology enables the fabrication of mixed signal ICs capable to operate at high temperature (300ºC) and high frequencies (300kHz). We consider this study an important step ahead regarding the future ICs developments on SiC.
Finally, experimental irradiations were performed on W-Schotthy diodes and mesa-MESFET devices (with the same Schottky gate than the planar SiC MESFET) in order to study their radiation hardness stability. The good radiation endurance of SiC Schottky-gate devices is proven. It is expected that the new developed devices with the same W-Schottky gate, to have a similar behavior in radiation rich environments.
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Lades, Martin. "Modeling and simulation of wide bandgap semiconductor devices 4H/6H-SiC /." [S.l. : s.n.], 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=962057827.
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Pourbagheri, Mahabadi Haniyeh. "Optical studies of surface recombination velocity in 4H-SiC epitaxial layer." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37225.
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In this work optical studies of the effect of surface passivation for surface recombination velocity at the interface between 4H-SiC epitaxial layer and various passivation layers are presented. Four samples have been used consisting of three main parts: thin film oxide layer, 4H-SiC epitaxial layer and 4H-SiC substrate. The substrates for all samples are the same, highly doped n-type. The doping and thickness of the epitaxial layers are different; three samples have n-type epilayer, doping around 3-5×1015cm-3and one sample, the thinnest one, has a p-type doping of 1×1017cm-3.Two types of oxide are used as passivation layer: Al2O3on the n-type and p-type with 80 nm thickness, which is prepared by the ALD method, and SiO2– grown layer with 50 nm thickness, which is produced by thermal growth technique at 1250 ºC in N2O ambient for 8 hours. The forth epilayer was bombarded with 30 keV energy argon ion implanted with different doses through a native oxide. Free carrier absorption (FCA) technique was used to extract effective lifetime of excess carriers. The excess carriers are created by a high energy laser (355 nm) pulse, exiting electrons to the conduction band. The decay of these carriers is then studied by a second laser at 861nm. The carriers in the substrate recombine quickly, but in the thin epilayer the lifetime is long enough to be influenced by surface recombination at the epi-passivation layer interface. By fitting the experimental results, the surface recombination velocity (SRV) at the interfaces of epi/oxide can be extracted. The SRV of substrate/epi is assumed constant at 1×106cm/s value. The highest SRV, 5.7×104cm/s, is found in the n-type epitaxial layer with 50 nm SiO2and the slowest value, 1.07 ×103cm/s, is found in the p-type epitaxial layer with 80 nm Al2O3. For the argon implanted sample, we did not find the anticipation results. Although the highest dose gives the most defects, the SRV, 1.41×103 cm/s, was not very different for other doses.
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Cristiano, Marco. "Design considerations for a high temperature image sensor in 4H-SiC." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-185268.
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This thesis is part of a project, Working on Venus, funded by the Knut and Alice Wallenberg Foundation (one of the largest Swedish funders of research) and developed by KTH in collaboration with Linkӧping University. The goal of this project is to create a lander able to investigate the planet Venus and to work under extreme conditions, i.e. it has to be able to withstand at high levels of radiation and high temperatures such as that of Venus surface (that is about 460 °C) without integrating a dedicated bulky cooling system to reduce the overall weight and volume of the system. In this thesis it will be investigated in detail the 4H-SiC performances to realize a CMOS image sensor for UV photography that operates at high temperature. This work will include discussions and proposals on possible future applications, such as the realization of 4H-SiC phototransistors
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Bouhafs, Chamseddine. "Structural and Electronic Properties of Graphene on 4H- and 3C-SiC." Doctoral thesis, Linköpings universitet, Halvledarmaterial, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132408.
Full textAbstract:
Graphene is a one-atom-tick carbon layer arranged in a honeycomb lattice. Graphene was first experimentally demonstrated by Andre Geim and Konstantin Novoselov in 2004 using mechanical exfoliation of highly oriented pyrolytic graphite (exfoliated graphene flakes), for which they received the Nobel Prize in Physics in 2010. Exfoliated graphene flakes show outstanding electronic properties, e.g., very high free charge carrier mobility parameters and ballistic transport at room temperature. This makes graphene a suitable material for next generation radio-frequency and terahertz electronic devices. Such applications require fabrication methods of large-area graphene compatible with electronic industry. Graphene grown by sublimation on silicon carbide (SiC) offers a viable route towards production of large-area, electronic-grade material on semi-insulating substrate without the need of transfer. Despite the intense investigations in the field, uniform wafer-scale graphene with very high-quality that matches the properties of exfoliated graphene has not been achieved yet. The key point is to identify and control how the substrate affects graphene uniformity, thickness, layer stacking, structural and electronic properties. Of particular interest is to understand the effects of SiC surface polarity and polytype on graphene properties in order to achieve large-area material with tailored properties for electronic applications. The main objectives of this thesis are to address these issues by investigating the structural and electronic properties of epitaxial graphene grown on 4HSiC and 3C-SiC substrates with different surface polarities. The first part of the thesis includes a general description of the properties of graphene, bilayer graphene and graphite. Then, the properties of epitaxial graphene on SiC by sublimation are detailed. The experimental techniques used to characterize graphene are described. A summary of all papers and contribution to the field is presented at the end of Part I. Part II consists of seven papers.Research Funders not listed under Research funders and strategic development areas: Marie Curie actions under the Project No.264613-NetFISiC, the centre of Nano Science and Nano technology (CeNano).
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Zhu, Xingguang Williams John R. "Alternative growth and interface passivation techniques for SiO2 on 4H-SiC." Auburn, Ala, 2008. http://hdl.handle.net/10415/1494.
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Chen, Zengjun Williams John R. "Electrical properties of MOS devices fabricated on 4H carbon-face SiC." Auburn, Ala, 2009. http://hdl.handle.net/10415/1858.
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Omotoso, Ezekiel. "Electrical characterization of process- and radiation-induced defects in 4H-SiC." Thesis, University of Pretoria, 2015. http://hdl.handle.net/2263/53547.
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Devices for operation in aerospace, manufacturing industries, defence and radiation-harsh environments need to be manufactured from materials that are resistant to the frequent damage caused by irradiation and high-temperature environments. Silicon carbide (SiC) is a wide-bandgap semiconductor material that promises to provide solutions to these problems based on its capability to operate under extreme conditions of temperature and radiation. These conditions introduce defects in the materials. Such defects play an important role in determining the properties of devices, albeit beneficial or detrimental. Therefore it is very important to characterize the defects present in as-grown material as well as defects introduced during processing and irradiation.
In this research, resistive evaporation (RE) as well as electron-beam deposition was employed for the fabrication of ohmic and Schottky barrier contacts on nitrogen-doped, n-type 4H-SiC substrate. The quality of the Schottky barrier diodes (SBDs) deposited was confirmed by current-voltage (I-V) and capacitance-voltage (C-V) measurements. Deep level transient spectroscopy (DLTS) and high-resolution Laplace DLTS were successfully used to characterize the electrically active defects present in the 4H-SiC SBDs before and after bombarding them with high-energy electrons and alpha-particles as well as after exposing the sample to electron beam deposition conditions. I-V and C-V measurements showed that the SBDs deposited by RE were of good quality with an ideality factor close to unity, a low series resistance and low reverse leakage current. After irradiation, the electrical properties deviated significantly based on the irradiation types and fluences. Thermionic emission dominated at high temperatures close to room temperature, while other current transport mechanisms became dominant at lower temperatures. The ideality factor increased and Schottky barrier heights decreased with decreasing temperature, which has been attributed to barrier inhomogeneities at the metal 4H-SiC interface. Irradiation by high-energy particles had no effect on mean barrier height, but influenced the modified Richardson constant of the devices.
Results obtained from the DLTS and LDLTS measurements revealed the presence of four electrically active deep levels in the as-grown 4H-SiC, and the presence of two and three extra defects after bombardment with alpha-particle and high-energy electron (HEE) irradiation, respectively. The irradiation by both alpha-particle and HEE caused an increase in concentration of electrically active defects attributed to nitrogen impurities as well as the Z1/Z2 intrinsic defect attributed to the carbon vacancy. However, the structure of two of the defects observed with energies EC 0.22 and EC 0.76 eV were unknown.
Electron-beam deposition as well as exposure to electron-beam deposition conditions introduced two additional electrically active defects in 4H-SiC These two defects were close to the metal-semiconductor junction, but the process did not cause any noticeable increase in the concentration of defects previously observed in the as-grown 4H-SiC SBDs deposited by resistive evaporation technique. These electrically active defects with energies EC 0.42 and EC ~0.70 eV were probably caused by the product of elastic collisions between 10 keV electrons and residual vacuum gases which were ionized around the filament and accelerated by the electric field towards the substrate.Thesis (PhD)--University of Pretoria, 2015.
Physics
PhD
Unrestricted
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Stone, Stephen E. "A Study of the Effects of Neutron Irradiation and Low Temperature Annealing on the Electrical Properties of 4H Silicon Carbide." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1211898142.
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Short, Eugene L. "Sequential afterglow processing and non-contact Corona-Kelvin metrology of 4H-SiC." [Tampa, Fla] : University of South Florida, 2009. http://purl.fcla.edu/usf/dc/et/SFE0003102.
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Negoro, Yuki. "Ion implantation and embedded epitaxial growth for 4H-SiC power electronic devices." 京都大学 (Kyoto University), 2005. http://hdl.handle.net/2433/144921.
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Short, Eugene L. III. "Sequential Afterglow Processing and Non-Contact Corona-Kelvin Metrology of 4H-SiC." Scholar Commons, 2009. https://scholarcommons.usf.edu/etd/19.
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Silicon carbide (SiC) is a wide band-gap semiconductor with advantageous electrical and thermal properties making it attractive for high temperature and power applications. However, difficulties with oxide/SiC structures have posed challenges to the development of practical MOS-type devices. Surface conditioning and oxidation of 4H-SiC were investigated using a novel sequential afterglow processing approach combined with the unique capabilities of non-contact corona-Kelvin metrology. The use of remote plasma assisted thermal oxidation facilitated film growth at low temperature and pressure with the flexibility of sequential in-situ processing options including pre-oxidation surface conditioning. Corona-Kelvin metrology (C-KM) provided a fast, non-destructive method for electrical evaluation of oxide films and semiconductor surfaces. Non-contact C-KM oxide capacitance-voltage characteristics combined with direct measurement of SiC surfaces using C-KM depletion surface barrier monitoring and XPS analysis of surface chemistry were interpreted relating the impact of afterglow conditioning on the surface and its influence on subsequent oxide thin film growth. Afterglow oxide films of thicknesses 50-500 angstroms were fabricated on SiC epi-layers at low growth temperatures in the range 600-850°C, an achievement not possible using conventional atmospheric oxidation techniques. The inclusion of pre-oxidation surface conditioning in forming gas (N2:H2)* afterglow was found to produce an increase in oxide growth rate (10-25%) and a significant improvement in oxide film thickness uniformity. Analysis of depletion voltage transients on conditioned SiC surfaces revealed the highest degree of surface passivation, uniformity, and elimination of sources of charge compensation accomplished by the (N2:H2)* afterglow treatment for 20 min. at 600-700°C compared to other conditioning variations. The state of surface passivation was determined to be very stable and resilient when exposed to a variety of temporal, electrical, and thermal stresses. Surface chemistry analysis by XPS gave evidence of nitrogen incorporation and a reduction of the C/Si ratio achieved by the (N2:H2)* afterglow surface treatment, which was tied to the improvements in passivation, uniformity, and growth rate observed by non-contact C-KM measurements. Collective results were used to suggest a clean, uniform, passivated, Si-enriched surface created by afterglow conditioning of 4H-SiC as a sequential preparation step for subsequent oxidation or dielectric formation processing.
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Di, Benedetto Luigi. "Analysis and design of 4H-SiC bipolar mode field effect power (BMFET)." Doctoral thesis, Universita degli studi di Salerno, 2013. http://hdl.handle.net/10556/894.
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2011 - 2012Analysis and design of a new Silicon Carbide polytype 4H (4H-SiC) bipolar power transistor are the main topics of this Ph.D. thesis. The device is the Bipolar Mode Field Effect Transistor (BMFET) and exploits the electric field due to the channel punching-through in order to have a normally-off behavior and the minority carrier injection from the gate regions into the channel in order to obtain the channel conductivity modulation. The structure of the transistor is oxide-free and its advantages are due to the lower conduction resistance, to the higher output current density and blocking voltage and to the elevated switching frequency, which make it competitive with commercial 4H-SiC Junction Field Effect Transistors or Bipolar Junction Transistors. These activities, which have been completed with the definition of the main process steps and of the mask layouts, are supported by a technology activity and by an intense modeling activity of BMFET electrical characteristics, which has been validated by comparisons with the results of numerical simulator (ATLAS Silvaco) and the measures of commercial devices having a similar structure, like Vertical-JFETs. In the former activity, in order to obtain an integrated free-wheeling diode in anti-parallel configuration to BMFET, an original 4H-SiC Schottky rectifier has been fabricated; precisely, for the first time in the literature, DiVanadium PentOxide (V2O5), a Transition Metal Oxide, has been used as anode contact of the rectifier. The device is a heterojunction between a thin V2O5 layer, which is thermally evaporated and has a thickness of around 5nm, and a 4H-SiC n-type low doped epilayer. By analyzing the JD-VD and CD-VD curves, the structure has a rectifier behavior with a high/low current ratio higher than seven order of magnitude and its transport mechanism is described by the thermionic emission theory characterized by a Schottky barrier height and an ideality factor between 0.78eV and 0.85eV and between 1.025 and 1.06, respectively, at T=298K. Because the gate doping concentration greatly influences the BMFET performances, as input resistance, DC current gain and blocking voltage, Aluminum ion implantation process, used to realize the Gate regions, is strongly analyzed in terms of the dose concentrations and of the annealing temperature. It will show as the necessity of a low BMFET on-resistance, which is possible with highly conductive gate regions in order to permit high injection levels of the minority carriers, is counteracted by the Aluminum incomplete ionization in 4H-SiC. This phenomenon together with the band-gap narrowing effect limits the hole carrier density from gate to channel. The analysis, in collaboration with the Institute for the Microelectronics and Microsystems (IMM) of CNR in Bologna, Italy, consists to reveal the effects of various different doses at different temperature annealing (1920K and 2170K) on the gate injection efficiency and on the input current density. Since the introduction of the first normally-off Si JFET in ‘80 years, the description of the potential barrier height into the channel has been unresolved due to the complex relations with the channel geometry and bias conditions. In the second activity an analytical model of the potential barrier height in the channel is proposed and compared with the numerical simulation results by changing the channel length and width, respectively in the range 0.1÷6μm e 0.5÷3μm, the channel doping concentration, between 1014÷1017cm-3, and the output and input bias voltages. Moreover, it has been also validated by using Silicon as semiconductor material, permitting to extend it to other devices with similar structures, like BSITs, VJFETs and SITs. From a further improvement of this model, another has been developed, which is able to describe the trans-characteristics of the transistor both in sub-threshold condition and in unipolar conduction, and the comparisons with numerical simulations and experimental data validated the results. Finally, the analysis of the input diode during the switching-off has been performed because the switching capability of the BMFET depends on the storage charge into the channel during the “on” state. The result is the development of an analytical model that describes the spatial distributions of the electric field, of the minority carrier concentration and of the carrier current densities into the epilayer at each instant during the switching, in addition obviously to the current and voltage transients. It is shown as the combination of this model with another static model just developed in a previous Ph.D. thesis is an useful instrument to understand how physical parameters, which are dependent on the manufacturing processes, as carrier life-time and doping concentrations, can affect the dynamic behavior. [edited by author]
XI n.s.
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Maslougkas, Sotirios. "Gate oxide characterization of 4H-SiC MOS capacitors : A study of the effects of electrical stress on the flat-band voltage of n-type substrate 4H-SiC MOS capacitors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-301848.
Full textAbstract:
Silicon is the main material used in electronics. The evolution of power electronics and the need for more power efficient semiconductor devices led silicon to its limits. Silicon carbide is a promising material for electronic applications with a wide band-gap, high critical electric field, high thermal conductivity and saturation velocity. Except from its superiority to silicon, silicon carbide comes with a drawback of about two orders of magnitude more interface traps in the SiC/SiO2 interface compared with silicon. A result of this drawback is a flat-band voltage shift when applying a stress to the gate of MOS capacitors and power MOSFETs. In order to study the pure characteristics of the SiC/SiO2 interface, two stress methods, a current pulse stress and gate voltage upsweep, have been applied on 4H-SiC capacitors with nitrided thermal oxides at room temperature and at higher temperatures. The flat-band voltage recovery was examined. The flat-band voltage could be restored at room temperature with a gate voltage downsweep while a restoration is not needed at higher temperatures. The maximum voltage (initial voltage) and the voltage rate of the downsweep were investigated and higher initial voltages and lower voltage rates showed to lead to better VFB restoration. A 200 millisecond long current pulse stress was implemented and it had almost similar effects as the voltage upsweep which lasts 50 seconds.Kisel är det viktigaste materialet som används i elektronik. Utvecklingen av kraftelektronik och behovet av mer energieffektiva halvledarkomponenter ledde kisel till sina gränser. Kiselkarbid är ett lovande material för elektroniska applikationer med ett brett bandgap, högt kritiskt elektriskt fält, hög värmeledningsförmåga och hög mättningshastighet. Förutom dess överlägsenhet gentemot kisel, kommer kiselkarbid med en nackdel med cirka två storleksordningar fler gränssnittsfällor i SiC / SiO2-gränssnittet jämfört med kisel. Ett resultat av denna nackdel är en förskjutning av flatbands-spänningen, VFB, när man applicerar en spänning på gaten till MOS-kondensatorer och kraft- MOSFETar. För att studera de rena egenskaperna hos SiC/SiO2-gränssnittet har två spänningsmetoder, en strömpulsstress och ett uppåtriktat gate-spänningssvep, applicerats på 4H-SiC- kondensatorer med nitriderade termiska oxider vid rumstemperatur och vid högre temperaturer. Återställning av VFB undersöktes. VFB kan återställas vid rumstemperatur med ett nedåtriktat gate-spänningssvep medan en återställning inte behövs vid högre temperaturer. Den maximala spänningen (initialspänningem) och svephastigheten för det nedåtriktade svepet undersöktes och högre initialspänningar och lägre svephastigheter visade sig leda till bättre VFB-återställning. En 200 millisekund lång strömpuls-stress implementerades och den hade nästan samma effekter som ett uppåtriktat spänningssvep
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Nguyen, Tuan Khoa. "Piezoresistive Effect in 4H Silicon Carbide towards Mechanical Sensing in Harsh Environments." Thesis, Griffith University, 2018. http://hdl.handle.net/10072/381509.
Full textAbstract:
The fast-growing demand for mechanical sensors in harsh environments (e.g. mining/deep oil explorations, power/chemical plants and space explorations) urges the
development of advanced materials which can replace silicon to work in these conditions. The superior mechanical properties of 4H silicon carbide (4H-SiC) combined
with the physical stability at high temperatures offer new capabilities to develop
MEMS sensors for those challenging situations. The piezoresistive effect is positioned
as one of the most significant sensing mechanisms used in MEMS/NEMS sensors to
detect or monitor mechanical signals, such as pressure, inertia, acceleration and deflection. Additionally, the use of micromachined sensors enables the miniaturization
and integration capabilities while requiring low power consumption and simple readout circuitries.
The main goals of this thesis are to investigate the piezoresistive effect in p-type
4H-SiC and to develop 4H-SiC based sensors which can be utilised for mechanical
sensing in harsh environments. First, a literature review of developments and current research interests in the piezoresistive effect and silicon carbide materials for
mechanical sensing are presented. Next, theoretical analyses on the strain induced
effect in the silicon carbide energy band structure are thoroughly conducted. Moreover, the calculation of the coordinate transformation is performed to determine
the fundamental piezoresistive coefficients in the (0001) plane of 4H-SiC. To verify
the theoretical results, the fabrication of 4H-SiC sensing devices and experimental
measurements are carried out. As such, the piezoresistive effect in p-type 4H-SiC at
room and high temperatures is discovered by measuring the effect in longitudinal and
transverse piezoresistor configurations. Additionally, the piezoresistive coefficients in
the (0001) plane of 4H-SiC are investigated, providing insight into the orientation
dependence of the piezoresistive effect in p-type 4H-SiC for the optimization of the
sensing design. Subsequently, 4H-SiC based sensing devices are fabricated and characterised including a 4H-SiC based van der Pauw strain sensor and a 4H-SiC based
pressure sensor. The excellent linearity, good repeatability, and stability of these
sensors are favourable for mechanical sensing applications. Additionally, the 4H-SiC
based pressure sensor exhibits high sensitivity and good reliability in cryogenic and
high temperatures, indicating the potential for hostile environmental sensing.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Eng & Built Env
Science, Environment, Engineering and Technology
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Grivickas, Paulius. "Optical studies of carrier transport and fundamental absorption in 4H-SiC and Si." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3695.
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The Fourier transient grating (FTG) technique and a novelspectroscopic technique, both based on free carrier absorption(FCA) probing, have been applied to study the carrierdiffusivity in 4H-SiC and the fundamental absorption edge in4H-SiC and Si, respectively.
FTG is a unique technique capable of detecting diffusioncoefficient dependence over a broad injection interval rangingfrom minority carrier diffusion to the ambipolar case. In thiswork the technique is used for thin epitaxial 4H-SiC layers,increasing the time- and spatial-resolution of the experimentalsetup by factors of ~100 and ~10, respectively, in comparisonto the established Si measurements. It is found that thediffusion coefficient within the detected excitation range inn-type 4H-SiC appears to be lower than the analyticalprediction from Hall-mobility data. To explain this, it issuggested that the minority hole mobility is reduced withrespect to that of the majority one or that the hole mobilityvalue is in general lower than previously reported. Observeddifferences between the temperature dependency of the ambipolardiffusion and the Hall-prediction, on the other hand, areattributed to the unknown Hall factor for holes and theadditional carrier-carrier scattering mechanism in Hallmeasurements. Furthermore, at high excitations a substantialdecrease in the ambipolar diffusion is observed andadditionally confirmed by the holographic transient gratingtechnique. It is shown that at least half of the decrease canbe explained by incorporating into the theoretical fittingprocedure the calculated band-gap narrowing effect, taken fromthe literature. Finally, it is demonstrated that numerical datasimulation can remove miscalculations in the analytical Fourierdata analysis in the presence of Auger recombination.
Measurements with variable excitation wavelength pump-probeare established in this work as a novel spectroscopic techniquefor detecting the fundamental band edge absorption in indirectband-gap semiconductors. It is shown that the techniqueprovides unique results at high carrier densities in doped orhighly excited material. In intrinsic epilayers of 4H-SiC,absorption data are obtained over a wide absorption range, atdifferent temperatures and at various polarizations withrespect to the c-axis. Experimental spectra are modeled usingthe indirect transition theory, subsequently extracting thedominat phonon energies, the approximate excitonic bindingenergy and the temperature induced band-gap narrowing (BGN)effect in the material. Measurements in highly dopedsubstrates, on the other hand, provide the first experimentalindication of the values of doping induced BGN in 4HSiC. Thefundamental absorption edge is also detected in highly dopedand excited Si at carrier concentrations exceeding theexcitonic Mott transition by several orders of magnitude. Incomparison to theoretical predictions representing the currentunderstanding of absorption behavior in dense carrier plasmas,a density dependent excess absorption is revealed at 75 K.Summarizing the mainfeatures of the subtracted absorption, itis concluded that an excitonic enhancement effect is present inSi.
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Wutikuer, Otkur. "Fabrication and Characterization of 4H-SiC MOS Capacitors with Different Dielectric Layer Treatments." Thesis, Linköpings universitet, Halvledarmaterial, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-144984.
Full textAbstract:
4H-SiC based Metal-Oxide Semiconductor(MOS) capacitors are promising key components for next generation power devices. For high frequency power applications, however, there is a major drawback of this type of devices, i.e. they have low inversion channel mobility that consequently affects the switching operation in MOS Field-Effect Transistors (MOSFETs). Carbon clusters or excess carbon atoms in the interface between the dielectric layer and SiC is commonly considered to be the carrier trapping and scattering centers that lower the carrier channel mobility. Based on the previous work in the research group, a new fabrication process for forming the dielectric layer with a lower density of the trap states is investigated. The process consists of standard semiconductor cleaning, pre-treatments, pre-oxidation, plasma enhanced chemical vapor deposition (PECVD) and post oxidation annealing. I-V measurements of the dielectric strength showed that the resulting layers can sustain proper working condition under an electric field of at least 5MV/cm. C-V characteristics measurements provided the evidence that the proposed method can effectively reduce the interfacial states, which are main culprit for a large flat band voltage shift of C-V characteristics, in particular under annealing at 900°C in nitrogen atmosphere.