Academic literature on the topic '40~nm'
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Journal articles on the topic "40~nm"
Durkan, C., and I. V. Shvets. "40 nm resolution in reflection-mode SNOM with λ = 685 nm." Ultramicroscopy 61, no. 1-4 (December 1995): 227–31. http://dx.doi.org/10.1016/0304-3991(95)00114-x.
Full textPezeshki, B., M. Zelinski, H. Zhao, and V. Agrawal. "40-mW 650-nm distributed feedback lasers." IEEE Photonics Technology Letters 10, no. 1 (January 1998): 36–38. http://dx.doi.org/10.1109/68.651093.
Full textOno, M., M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai. "A 40 nm gate length n-MOSFET." IEEE Transactions on Electron Devices 42, no. 10 (1995): 1822–30. http://dx.doi.org/10.1109/16.464413.
Full textPark, Chaeeun, and Munkyo Seo. "A 140 GHz Low-Noise Amplifier in 40 nm CMOS." Journal of Korean Institute of Electromagnetic Engineering and Science 33, no. 4 (April 2022): 312–17. http://dx.doi.org/10.5515/kjkiees.2022.33.4.312.
Full textWandt, D., M. Laschek, K. Przyklenk, A. Tünnermann, and H. Welling. "External cavity laser diode with 40 nm continuous tuning range around 825 nm." Optics Communications 130, no. 1-3 (September 1996): 81–84. http://dx.doi.org/10.1016/0030-4018(96)00171-x.
Full textZaghib, Karim, Alain Mauger, Monika Kopec, Francois Gendron, and C. M. Julien. "Intrinsic Properties of 40 nm-sized LiFePO4 Particles." ECS Transactions 16, no. 42 (December 18, 2019): 31–41. http://dx.doi.org/10.1149/1.3112726.
Full textAppenzeller, J., R. Martel, Ph Avouris, J. Knoch, J. Scholvin, J. A. del Alamo, P. Rice, and P. Solomon. "Sub-40 nm SOI V-groove n-MOSFETs." IEEE Electron Device Letters 23, no. 2 (February 2002): 100–102. http://dx.doi.org/10.1109/55.981319.
Full textHomulle, Harald, Fabio Sebastiano, and Edoardo Charbon. "Deep-Cryogenic Voltage References in 40-nm CMOS." IEEE Solid-State Circuits Letters 1, no. 5 (May 2018): 110–13. http://dx.doi.org/10.1109/lssc.2018.2875821.
Full textHofmann, W., M. Müller, P. Wolf, A. Mutig, T. Gründl, G. Böhm, D. Bimberg, and M. C. Amann. "40 Gbit/s modulation of 1550 nm VCSEL." Electronics Letters 47, no. 4 (2011): 270. http://dx.doi.org/10.1049/el.2010.3631.
Full textTakeuchi, Issei, Yosuke Shimamura, Yuki Kakami, Tsunenori Kameda, Keitaro Hattori, Seiji Miura, Hiroyuki Shirai, et al. "Transdermal delivery of 40-nm silk fibroin nanoparticles." Colloids and Surfaces B: Biointerfaces 175 (March 2019): 564–68. http://dx.doi.org/10.1016/j.colsurfb.2018.12.012.
Full textDissertations / Theses on the topic "40~nm"
Hubert, Quentin. "Optimisation de mémoires PCRAM pour générations sub-40 nm : intégration de matériaux alternatifs et structures innovantes." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01061795.
Full textKromer, Christian. "10 Gb/s to 40 Gb/s receiver for high-density optic interconnects in 80-nm CMOS /." Zürich : ETH, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16347.
Full textShu, Ran [Verfasser], Georg [Akademischer Betreuer] Böck, and Reinhold [Akademischer Betreuer] Orglmeister. "Analysis and design of 40 GHz frequency generation circuits in 90 nm CMOS technology / Ran Shu. Gutachter: Reinhold Orglmeister. Betreuer: Georg Böck." Berlin : Technische Universität Berlin, 2014. http://d-nb.info/1065669682/34.
Full textLecat-Mathieu, de Boissac Capucine. "Developing radiation-hardening solutions for high-performance and low-power systems." Electronic Thesis or Diss., Aix-Marseille, 2021. http://www.theses.fr/2021AIXM0413.
Full textNew actors have accelerated the pace of putting new satellites into orbit, and other domains like the automotive industry are at the origin of this development. These new actors rely on advanced technologies, such as UTBB FD-SOI in order to be able to achieve the necessary performance to accomplish the tasks. Albeit disruptive in terms of intrinsic soft-error resistance, the growing density and complexity of spaceborne and automotive systems require an accurate characterization of technologies, as well as an adaptation of traditional hardening techniques. This PhD focuses on the study of radiation effects in advanced FD-SOI and bulk silicon processes, and on the research of innovative protection mechanisms. A custom, self-calibrating transient measurements structure with automated design flow is first presented, allowing for the characterization of four different technologies during accelerated tests. The soft-error response of 28~nm FD-SOI and 40~nm bulk logic and storage cells is then assessed through beam testing and with the help of TCAD simulations, allowing to study the influence of voltage, frequency scaling and the application of forward body biasing on sensitivity. Total ionizing dose is also investigated through the use of an on-chip monitoring block. The test results are then utilized to propose a novel hardening solution for system on chip, which gathers the monitoring structures into a real-time radiation environment assessment and a power management unit for power mode adjustments. Finally, as an extension of the SET sensors capability, an implementation of radiation monitors in a context of secure systems is proposed to detect and counteract laser attacks
Wang, Chun, and 王淳. "A 100-GHz Power Amplifier Design in 40-nm CMOS Process." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/12539437183740398588.
Full text國立中央大學
電機工程學系
105
This thesis proposes a 100-GHz power amplifier design in TSMC 40-nm CMOS process. The power amplifier applies to the 200-GHz transmitter circuit. To avoid braking the next stage circuit, the power amplifier does not add the power combiner design which is designed for increasing the output power. The first part is the basic theories related to the design of power amplifiers, including the DC bias point of transistor and the load line theory. The second part is the design of the 100-GHz two stage power amplifiers. The common source mode is chosen in this design for its high gain characteristic. To increase the stability and gain , the cross couple capacitors is added for resonating the parasitic capacitors of the transistors. The transformers in this power amplifier are worked as the impedance matching network and balun. The power amplifier exhibits saturation output power of 9.49 dBm, maximum power-added efficiency (PAE) of 6.95%, and the output power at 1-dB gain compression point of 7.42 dBm. The 3-dB bandwidths is 31%. The third part is the design of the 200-GHz transmitter. This circuit consists of a voltage control oscillator (VCO), a driver amplifier, a power amplifier, a doubler, and an ASK modulator. The VCO generates the 100-GHz signal, and then it gets enough output power by driver amplifier and power amplifier. The operating frequency will be raised up to 200-GHz by doubler. The signal will be modulated with a digital data signal by ASK modulator in the end. This transmitter provides output power of -0.95 dBm and a data rate of 20 Gb/s at 200 GHz.
Lin, Chen-Lun, and 林振倫. "A 40-Gb/s Wireline Backplane Receiver in 65-nm CMOS Technology." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/83437373053440643737.
Full text國立臺灣大學
電子工程學研究所
101
In this thesis, a 40-Gb/s receiver has been implemented in 65-nm CMOS technology, which composed of three critical components of a wireline backplane receiver – an analog equalizer, a clock and data recovery circuit (CDR), and a demultiplexer (DMUX). The analog equalizer consists of two gain stages and two filter stages, totally providing at most 14.9-dB boosting and 4.8-dB dc gain. It compensates sufficiently for the loss of the 5-cm channel on a Rogers board, and has a 35-mV input sensitivity. The following is a 40-Gb/s full-rate CDR, constructed with a linear phase detector (PD) and a frequency detector (FD) without an external reference clock. Both the PD and the FD operate only with the data signal and the clock signal from the voltage-controlled oscillator (VCO), and thus detect the phase error and the frequency error automatically. The last part of the receiver is a DMUX. Like most typical structures, this DMUX is implemented with flip-flops to sample the desired output data. Further, in this design, the 40-Gb/s data is sampled by the quarter-rate clock signal and thus the DMUX produces the 10-Gb/s data signal. This circuit occupies 1.1 × 1 mm^2 including pads, consumes 427 mW from a 1.2-V supply, and achieves BER < 10^-12 for 2^31 – 1 PRBS.
Wang, Tai-sheng, and 王泰盛. "Lead Free Bump Assembly Material and Structure Study for 40 nm Wafer Technology." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/94066162279246754576.
Full text國立中山大學
機械與機電工程學系研究所
98
Solder bump is used to connect organic substrate with chip to form Flip Chip package. Comparing to wire bond package, the path is reduced so the electrical performance is much better. Due to the environmental concern, eutectic bump is replaced by lead-free bump gradually. Meanwhile, since wafer technology is improved from 55 nm to 40 nm, the material for dielectric layers is also changed so the material for the package need to revised to meet the characteristic of wafer. Now the laser grooving is adopted before blade sawing to accommodate the brittleness of new 40nm wafer. Also, one extra polyimide is added in the wafer fabrication to reinforce the robustness of the circuit. The stress inside the lead-free bump can be reduced by optimizing the temperature of the reflow process and the speed of cooling. Different UBM structure is also reviewed to find out its affect on the strength of bump and low-K circuit so the failure mode of bump can be predicted. The selection of underfill need to be well considered so, the warpage of package can be reduced, the maximum protection of bump and low-K circuit can be achieved, and the process is easier to control. (The four underfills are reviewed) The reliability test is utilized to decide the best bump composition, the structure of UBM, the selection of underfills and the process parameter. By adding the laser grooving in the wafer sawing process, the chance of crack on die low-K layer is reduced during the reliability test. As for the UBM structure, the POU is better than RPI to reduce the crack of die low-K layer. The result is verified on the package with no underfill by Temperature cycle. Last, the matching of SnCu0.7 bump with SAC305 C4 pad has the best result. During the research, the variance of CTE for the core of substrate contributes less warpage of package, comparing to the difference of Tg for underfills. The adhesion of underfills varies and the underfill UA9 has the best result. The flip chip package with underfill UA9 can passes TCB1000. The optimization of UBM structure for lead-free bump is researched and discussed. Composition of the lead-free bump, process parameter, and cost, those factors are also studied.
Lo, Chi-Kuang, and 羅啟光. "Design of A Fast Lock-In All-Digital Phase-Locked Loop in 40-nm CMOS Technology." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/3aq725.
Full text國立中正大學
資訊工程研究所
103
In recent years, biomedical electronic applications, spread-spectrum clock generators, implantable medical devices, and frequency hopping wireless applications are widely used in system-on-a-chip (SoC). In an SoC, it requires different clock sources for different I/O interfaces. Thus, phase-locked loops play an important role in SoC in order to generate different clock sources. Besides, the primary concern of these applications are low energy and low cost. While the operation voltage is scaling down with the latest CMOS process, analog PLLs encounter great design challenges. According to time to market, in order to minimize the design time and the design efforts, all-digital phase-locked loops (ADPLLs) are adopted in digital design approaches. In addition, ADPLLs implemented with standard cells can not only speed up the design time, but also improve the portability. As compared with analog PLLs, ADPLLs are more suitable for SoC Analog PLLs are usually not to be stopped due to the long lock-in time. When the system is in sleeping mode, the PLL power consumption dominates the standby power consumption of the system. Therefore, if PLLs can lock the frequency and phase quickly, the lock-in time can be reduced so that PLLs can be turned off in low power modes. As a result, fast lock-in ADPLLs become more and more popular. Therefore, in this thesis, we proposed a fast lock-in ADPLL with a calibration method in order to decrease the chip area and improve the accuracy in frequency estimation. In addition, the test chip is implemented and verified in TSMC 40-nm CMOS process with standard cells.
Liu, Chin-Tang, and 劉欽堂. "Yield Improvement of 40 nm NAND Flash Technology by Using a CHF3 Free Dry Etching Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/99418420112926166960.
Full text國立暨南國際大學
光電科技碩士學位學程在職專班
102
Semiconductor industry is new advance of industry , The semiconductor pace of development is very fast in recent years , As Moore’s law forecast , component size changed smaller gradually by produce that the integrated circuit process technology also complex now . For upgrade capacity of computer , communication and consumer electronics products with pursue cost lower of wafer unit , so electronic components produced smaller as complementary metal –oxide -semiconductor：CMOS which the target in the future . For component smaller that process also using by SiO2 as gate dielectric , in 45 nm and 32 nm of sub-nanometer process that the thickness must be lower 1 nm for component spec , also component between from peripheral and cell of contact hole critical dimension , CD must be smaller , but according to process requirement not cause thin film reduce too much , and depth also the same by etching , therefore , the process cause contact hole of critical dimension , CD smaller that wire problem un-open and punch .etc easier， the issue create a big challenge in etching process . This paper is talking about yield improvement of 40 nm NAND flash technology by using a CHF3 free dry etching process. It’s about an equipment of Applied etch which uses Reactive Ion Etching to adjust different parameters by CHF3 free dry etching process that the etch could get the better Etch profile to solve the problems for Critical Dimension，CD , such as WC/WE uniformity. Besides, it also get the better defect performance and yield improvement.
Cheng, Chia-Kai, and 鄭家凱. "A 1/2.5-Rate Clock and Data Recovery Circuit for 100Gb/s Ethernet in 40 nm Technology." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/42045406149607511904.
Full text國立臺灣大學
電子工程學研究所
104
In June, 2010, IEEE P802.3ba is generated officially. It defines the specification of 40GbE and 100GbE. The purpose is to extend the operation speed of the IEEE 802.3 agreement to 40Gbps and 100Gbps, and at the same time it also accords the current agreement and the demand of the transmission distance. At the definition of IEEE P802.3ba, the 100GbE is used four channels of 25Gbps output of with wavelength division multiplexing to achieve the purpose of high speed transmission. At optical communication systems, since the cost of the transmission line channel is very expensive, in order to reduce the cost, we usually hope we can transmit higher frequency data in single channel. At the 100GbE receiver system, we need to deserialize four channel 25Gbps signal into ten channel 10Gbps. Unlike the conventional power of 2 deserializer, the 2:5 data ratio would suffer from more complicate design, and consume more area and have more power dissipation. A 1/2.5-rate clock and data recovery (CDR) circuit is proposed in this thesis. We can deserialize the signal without 2:5 deserializer to reduce the hardware resource. This CDR is implemented in TSMC 40nm CMOS technology. At 1V power supply, it only consumes 51.5mW/Channel.
Books on the topic "40~nm"
Ruppé, Patricia A. Prehistoric households along the Chuska slope: Phase III data recovery at five sites (NM-H-49-98 [LA 107461], NM-H-50-112 [LA 107466], NM-H-50-113 [LA 107467], NM-H-46-40 [LA 115884], and NM-H-46-35 [LA 7551]), along Navajo Route N500(1), Toadlena to Newcomb, San Juan County, New Mexico. Zuni, N.M: Zuni Cultural Resource Enterprise, 2000.
Find full textRuppé, Patricia A. Prehistoric households along the Chuska slope: Phase III data recovery at five sites (NM-H-49-98 [LA 107461], NM-H-50-112 [LA 107466], NM-H-50-113 [LA 107467], NM-H-46-40 [LA 115884], and NM-H-46-35 [LA 7551]), along Navajo Route N500(1), Toadlena to Newcomb, San Juan County, New Mexico. Zuni, N.M: Zuni Cultural Resource Enterprise, 2000.
Find full text10 Gb/s to 40 Gb/s receiver for high-density optical interconnects in 80-nm CMOS. Konstanz: Hartung-Gorre, 2006.
Find full textTransportation Safety Board of Canada. Engine power loss in flight, Cathay Pacific Airways, Airbus A340-300 B-HXN, Timmins, Ontario, 40 nm W, 20 October 2002. Gatineau, Qué: Transportation Safety Board, 2004.
Find full textTransportation Safety Board of Canada. Engine power loss in flight, Cathay Pacific Airways, Airbus A340-300 B-HXN, Timmins, Ontario, 40 nm W, 20 October 2002. [Gatineau, Québec]: TSB, 2005.
Find full textDello-Russo, Robert D. Results of data recovery efforts at sites LA 109307 (NM-T-28-03) and LA 109309 (NM-T-28-05) and nature and extent testing efforts at site LA 115306 (NM-T-28-10) along Navajo route N55(1), Alamo Navajo Reservation to U.S. Interstate 40, Socorro County, New Mexico. Zuni, N.M: Pueblo of Zuni Cultural Resource Enterprise, 1999.
Find full textCanada, Bureau de la sécurité des transports du. Perte de puissance moteur de l'Airbus A340-300 B-HXN exploité par Cathay Pacific Airways à 40 nm à l'ouest de Timmins (Ontario), le 20 octobre 2002. Gatineau, Qué: Bureau de la sécurité des transports du Canada, 2004.
Find full textAraújo, Ana Cláudia Vaz de. Síntese de nanopartículas de óxido de ferro e nanocompósitos com polianilina. Brazil Publishing, 2021. http://dx.doi.org/10.31012/978-65-5861-120-2.
Full textBook chapters on the topic "40~nm"
Khalaf, Khaled, Vojkan Vidojkovic, John R. Long, and Piet Wambacq. "Digitally-Modulated Polar Transmitters in 40 nm CMOS." In Low-Power Millimeter Wave Transmitters for High Data Rate Applications, 55–96. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-16653-3_4.
Full textMoudgil, Aditi, and Jaiteg Singh. "LVCMOS-Based Frequency-Specific Processor Design on 40-nm FPGA." In Advances in Intelligent Systems and Computing, 513–19. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3373-5_51.
Full textToyoda, M., Y. Tamaru, S. Mori, K. Sawada, Y. Fu, E. J. Takahashi, A. Suda, F. Kannari, K. Midorikawa, and M. Yanagihara. "Multilayer Mirrors for Focusing Objective in 40-nm Wavelength Region." In Springer Proceedings in Physics, 287–90. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-73025-7_42.
Full textRadulov, Georgi, Patrick Quinn, Hans Hegt, and Arthur van Roermund. "A 16 bit 16-core Flexible 40 nm DAC Platform." In Smart and Flexible Digital-to-Analog Converters, 269–89. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0347-6_19.
Full textTan, Hongbing, Haiyan Chen, Sheng Liu, Xikun Ma, and Yaqing Chi. "A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS." In Communications in Computer and Information Science, 35–44. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7844-6_4.
Full textWen, Liang, Zhentao Li, and Yong Li. "A Comparison Analysis of Single-Ended Bit-Line Leakage Reduction Techniques at 40 nm Node." In Lecture Notes in Electrical Engineering, 1761–69. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4981-2_193.
Full textKaithal, Poonam, Rajiv Kant, Rohit Lall, Archana Verma, and Preetam Verma. "Green Synthesis of Silver Nanoparticles from Madhuca longifolia and Its Antibiofilm Potential." In Proceedings of the Conference BioSangam 2022: Emerging Trends in Biotechnology (BIOSANGAM 2022), 156–67. Dordrecht: Atlantis Press International BV, 2022. http://dx.doi.org/10.2991/978-94-6463-020-6_16.
Full textAggarwal, Arushi, Bishwajeet Pandey, Sweety Dabbas, Achal Agarwal, and Siddharth Saurabh. "Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA." In System and Architecture, 107–13. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8533-8_11.
Full textNuyts, Pieter A. J., Patrick Reynaert, and Wim Dehaene. "A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D PAs Using Baseband and RF PWM." In Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission, 219–54. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03925-1_6.
Full textIlakal, Anand, and Anuj Grover. "Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies." In Communications in Computer and Information Science, 414–20. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_41.
Full textConference papers on the topic "40~nm"
Pellegrini, S., B. Rae, A. Pingault, D. Golanski, S. Jouan, C. Lapeyre, and B. Mamdy. "Industrialised SPAD in 40 nm technology." In 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017. http://dx.doi.org/10.1109/iedm.2017.8268404.
Full textPsycharis, Ioannis Dimitrios, and Grigorios Kalivas. "A 40 GHz Low Phase Noise VCO in 40 nm CMOS." In 2022 Panhellenic Conference on Electronics & Telecommunications (PACET). IEEE, 2022. http://dx.doi.org/10.1109/pacet56979.2022.9976322.
Full textWang, Huei, Yuan-Hung Hsiao, Kuang-Sheng Yeh, Yu-Ting Chou, Jun-Kai Wang, and Yu-Hsuan Lin. "Millimeter-wave amplifiers in 40-nm CMOS." In 2016 Asia-Pacific Microwave Conference (APMC). IEEE, 2016. http://dx.doi.org/10.1109/apmc.2016.7931345.
Full textKim, Dae-Hyun, and Jesus A. del Alamo. "Logic Performance of 40 nm InAs HEMTs." In 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4419018.
Full textTanaka, Yuusuke, Takao Tamura, Masashi Fujimoto, Kyoichi Tsubata, Naka Onoda, and Kiyoshi Fujii. "Flare management for 40-nm logic devices." In SPIE Advanced Lithography, edited by Will Conley. SPIE, 2013. http://dx.doi.org/10.1117/12.2010082.
Full textLi, Lianming, and Tianze Wu. "A 40-nm CMOS 90-GHz Power Amplifier." In 2019 3rd International Conference on Circuits, System and Simulation (ICCSS). IEEE, 2019. http://dx.doi.org/10.1109/cirsyssim.2019.8935610.
Full textHo, Jonathan, Yan Wang, and Benjamin Lin. "Test structures for 40 nm design rule evaluation." In SPIE Advanced Lithography, edited by Vivek K. Singh and Michael L. Rieger. SPIE, 2009. http://dx.doi.org/10.1117/12.813448.
Full textEdgecumbe, John P., Verle W. Aebi, and Gary A. Davis. "GaAsP photocathode with 40% QE at 550 nm." In SPIE/IS&T 1992 Symposium on Electronic Imaging: Science and Technology, edited by C. Bruce Johnson and Bruce N. Laprade. SPIE, 1992. http://dx.doi.org/10.1117/12.60336.
Full textYeo, Jeongho, Hoyeon Kim, and Ben Eynon. "Full-field imprinting of sub-40 nm patterns." In SPIE Advanced Lithography, edited by Frank M. Schellenberg. SPIE, 2008. http://dx.doi.org/10.1117/12.775115.
Full textMachinet, Guillaume, Jérôme Lhermite, and Eric Cormier. "40 W picosecond fiber laser at 976 nm." In CLEO: Science and Innovations. Washington, D.C.: OSA, 2011. http://dx.doi.org/10.1364/cleo_si.2011.cms2.
Full textReports on the topic "40~nm"
Weissinger, Rebecca. Evaluation of hanging-garden endemic-plant monitoring at Southeast Utah Group national parks, 2013–2020. Edited by Alice Wondrak Biel. National Park Service, October 2022. http://dx.doi.org/10.36967/2294868.
Full text