Relevant bibliographies by topics / 3D ReRAM

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic '3D ReRAM'

Author: Grafiati
Published: 19 July 2023

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Journal articles on the topic "3D ReRAM"

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Hudec, Boris, I.-Ting Wang, Wei-Li Lai, Che-Chia Chang, Peter Jančovič, Karol Fröhlich, Matej Mičušík, Mária Omastová, and Tuo-Hung Hou. "Interface engineered HfO2-based 3D vertical ReRAM." Journal of Physics D: Applied Physics 49, no. 21 (April 29, 2016): 215102. http://dx.doi.org/10.1088/0022-3727/49/21/215102.

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Lee, Edward, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (January 31, 2022): 1–20. http://dx.doi.org/10.1145/3466681.

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We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.
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Walden, Candace, Devesh Singh, Meenatchi Jagasivamani, Shang Li, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, and Donald Yeung. "Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache." ACM Transactions on Architecture and Code Optimization 18, no. 4 (December 31, 2021): 1–26. http://dx.doi.org/10.1145/3462632.

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Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests. We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core’s LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3× and 1.7× over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system’s energy by 6.0× and 1.7×, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.
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Kim, Bokyung, Edward Hanson, and Hai Li. "An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 5 (May 2021): 1600–1604. http://dx.doi.org/10.1109/tcsii.2021.3067840.

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Sun, Chao, Kousuke Miyaji, Koh Johguchi, and Ken Takeuchi. "A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 2 (February 2014): 382–92. http://dx.doi.org/10.1109/tcsi.2013.2268111.

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Hassanpour, Mehdi, Marc Riera, and Antonio González. "A Survey of Near-Data Processing Architectures for Neural Networks." Machine Learning and Knowledge Extraction 4, no. 1 (January 17, 2022): 66–102. http://dx.doi.org/10.3390/make4010004.

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Data-intensive workloads and applications, such as machine learning (ML), are fundamentally limited by traditional computing systems based on the von-Neumann architecture. As data movement operations and energy consumption become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as Near-Data Processing (NDP), machine learning, and especially neural network (NN)-based accelerators has grown significantly. Emerging memory technologies, such as ReRAM and 3D-stacked, are promising for efficiently architecting NDP-based accelerators for NN due to their capabilities to work as both high-density/low-energy storage and in/near-memory computation/search engine. In this paper, we present a survey of techniques for designing NDP architectures for NN. By classifying the techniques based on the memory technology employed, we underscore their similarities and differences. Finally, we discuss open challenges and future perspectives that need to be explored in order to improve and extend the adoption of NDP architectures for future computing platforms. This paper will be valuable for computer architects, chip designers, and researchers in the area of machine learning.
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Gugnani, Shashank, Arjun Kashyap, and Xiaoyi Lu. "Understanding the idiosyncrasies of real persistent memory." Proceedings of the VLDB Endowment 14, no. 4 (December 2020): 626–39. http://dx.doi.org/10.14778/3436905.3436921.

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High capacity persistent memory (PMEM) is finally commercially available in the form of Intel's Optane DC Persistent Memory Module (DCPMM). Researchers have raced to evaluate and understand the performance of DCPMM itself as well as systems and applications designed to leverage PMEM resulting from over a decade of research. Early evaluations of DCPMM show that its behavior is more nuanced and idiosyncratic than previously thought. Several assumptions made about its performance that guided the design of PMEM-enabled systems have been shown to be incorrect. Unfortunately, several peculiar performance characteristics of DCPMM are related to the memory technology (3D-XPoint) used and its internal architecture. It is expected that other technologies (such as STT-RAM, memristor, ReRAM, NVDIMM), with highly variable characteristics, will be commercially shipped as PMEM in the near future. Current evaluation studies fail to understand and categorize the idiosyncratic behavior of PMEM; i.e., how do the peculiarities of DCPMM related to other classes of PMEM. Clearly, there is a need for a study which can guide the design of systems and is agnostic to PMEM technology and internal architecture. In this paper, we first list and categorize the idiosyncratic behavior of PMEM by performing targeted experiments with our proposed PMIdioBench benchmark suite on a real DCPMM platform. Next, we conduct detailed studies to guide the design of storage systems, considering generic PMEM characteristics. The first study guides data placement on NUMA systems with PMEM while the second study guides the design of lock-free data structures, for both eADR- and ADR-enabled PMEM systems. Our results are often counter-intuitive and highlight the challenges of system design with PMEM.
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Qolbi, M. Mahbub Jauhar, and Mochammad Choirur Roziqin. "Desain Ruang Unit Kerja Rekam Medis Berdasarkan Aspek Ergonomi Di Puskesmas Senduro." J-REMI : Jurnal Rekam Medik dan Informasi Kesehatan 4, no. 1 (December 29, 2022): 24–31. http://dx.doi.org/10.25047/j-remi.v4i1.3347.

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Kenyamanan lingkungan kerja dapat membantu dalam meningkatkan produktivitas kerja parapetugas dalam memberi pelayanan di Puskesmas, sehingga pasien mendapatkan pelayananmaksimal. Ruang kerja unit rekam medis di Puskesmas Senduro belum memenuhi aspekkenyamanan dikarenakan keadaan ruangan yang sempit hanya berukuran 9 m2sehinggaberdampak terhadap pelayanan dan ruang filing yang berukuran 7,5 m2tidak sesuai denganstandar minimal yaitu sebesar 20 m2. Meja, kursi dan rak filing memiliki ukuran yang tidaksesuai dengan antropometri petugas serta sarana dan prasana lain yang masih belum sesuaidengan kebutuhan petugas. Jenis penelitian ini menggunakan metode kualitatif dengan teknikpengumpulan data melalui hasil observasi, wawancara, dokumentasi dan brainstorming. Hasilpenelitian menunjukkan bahwa perlu adanya desain ruang unit kerja rekam medis baru yangdisesuaikan dengan standar pedoman dan alur pengolahan berkas rekam medis serta desainmeja, kursi dan rak filing yang disesuaikan dengan antropometri petugas. Desain ruang unitkerja rekam medis baru berukuran 10m x 6m yang sudah disesuaikan dengan standar/teori dandidesain menggunakan aplikasi SketchUp 3D 2020 sesuai dengan aspek ergonomi yangmeliputi efisiensi, kesehatan, keselamatan, kemanan dan kenyamanan. Saran untuk Puskesmas
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Amaral, Creusa Sayuri Tahara, Oreonnilda De Souza, Leiraud Hilkner de Souza, Gilson José da Silva, and Lucas Noboru Fatori Trevizan. "Novos caminhos da biotecnologia: As inovações da indústria 4.0 na saúde humana." Revista Brasileira Multidisciplinar 23, no. 3 (September 1, 2020): 203–31. http://dx.doi.org/10.25061/2527-2675/rebram/2020.v23i3.889.

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As aplicações da Biotecnologia na área da saúde humana são amplas e têm despertado o interesse de cientistas, da indústria e de investidores em todo o mundo. A Biotecnologia é uma das áreas que mais vem sendo impactada pelas novas tecnologias da indústria 4.0. Este trabalho tem como objetivo explorar as tendências registradas em patentes, incluindo bioimpressão 3D e genética humana, além de analisar os impactos que a indústria 4.0 tem repercutido na Biotecnologia, especificamente, na área da saúde humana e os impactos provocados na formação dos profissionais. Dentre os resultados foi possível comprovar o crescimento de pesquisas na Biotecnologia, evidenciando seu caráter multidisciplinar e a variedade de oportunidades na área da saúde humana, tanto no cenário econômico quanto na melhoria da qualidade de vida humana. Quanto às patentes em genética humana, as possibilidades comerciais derivadas do genoma humano abrem um novo campo (social e econômico), mas o assunto requer discussão e análise dos limites a essa exploração pela Bioética em conjunto ao Biodireito. Identificou-se também que a inteligência artificial, a robótica e a impressão 3D são tecnologias com grande potencial de soluções inovadoras na Biotecnologia. Essas novas soluções tecnológicas devem mudar o cenário de profissionais, requeridos tanto para o desenvolvimento de inovações quanto para a aplicação de novos serviços e produtos decorrentes desses avanços. A introdução de uma nova trajetória tecnológica, registrada pelas patentes, proporciona oportunidades para o reposicionamento de empresas e, mais amplamente, de países na competição internacional.
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Gomes Cardoso Gastaldi, Gabriela, Juliana Paula de Oliveira, Jorge Vicente Lopes da Silva, Rodrigo Alvarenga Rezende, and André Capaldo Amaral. "PHOTOBIOMODULATORY EFFECT OF LOW-INTENSITY LASER RADIATION ON MULTICELLULAR SPHEROIDS." Revista Brasileira Multidisciplinar 24, no. 2 (May 1, 2021): 156–67. http://dx.doi.org/10.25061/2527-2675/rebram/2021.v24i2.1136.

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Photobiomodulatory effects of low-intensity laser radiation (LILR) in cells cultured in standard, two-dimensional conditions are well established. Conversely, the characteristics of this effect in three-dimensional (3D) cultures, which are currently recommended due to the greater similarity with cellular behavior in vivo, have not yet been widely investigated. The objective of this work was to analyze the biomodulator effect of LILR, on the wavelength (λ) of 685 nm, on the constitution process and on the viability of cells cultured as multicellular spheroid (MSs). For this, agarose molds containing microwells were seeded (2x105 cell/ml) with osteogenic precursor cells (OPCs - MC3T3-E1) and kept under ideal culture conditions. The molds were irradiated for five consecutive days with doses of 0.5, 1.0 and 1.5 J/cm², the first irradiation being performed immediately after sowing. The process of constitution of MSs was analyzed and the cultures were submitted to the cell viability test. The results demonstrated that the LILR at λ 685 nm exerted a dose-dependent biomodulatory effect on cell metabolism and on the process of constituting the MSs of OPCs. These results demonstrate the potential of photobiomodulation to contribute to the process of constituting MSs, which can be explored in the strategies of multicellular spheroids therapy used in regenerative medicine and bioprinting.
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Dissertations / Theses on the topic "3D ReRAM"

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Ezzadeen, Mona. "Conception d'un circuit dédié au calcul dans la mémoire à base de technologie 3D innovante." Electronic Thesis or Diss., Aix-Marseille, 2022. http://theses.univ-amu.fr.lama.univ-amu.fr/221212_EZZADEEN_955e754k888gvxorp699jljcho_TH.pdf.

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Avec le développement de l'internet des objets et de l'intelligence artificielle, le "déluge de données" est une réalité, poussant au développement de systèmes de calcul efficaces énergétiquement. Dans ce contexte, en effectuant le calcul directement à l'intérieur ou à proximité des mémoires, le paradigme de l'in/near-memory-computing (I/NMC) semble être une voie prometteuse. En effet, les transferts de données entre les mémoires et les unités de calcul sont très énergivores. Cependant, les classiques mémoires Flash souffrent de problèmes de miniaturisation et ne semblent pas facilement adaptées à l'I/NMC. Ceci n'est pas le cas de nouvelles technologies mémoires émergentes comme les ReRAM. Ces dernières souffrent cependant d'une variabilité importante, et nécessitent l'utilisation d'un transistor d'accès par bit (1T1R) pour limiter les courants de fuite, dégradant ainsi leur densité. Dans cette thèse, nous nous proposons de résoudre ces deux défis. Tout d'abord, l'impact de la variabilité des ReRAM sur les opérations de lecture et de calcul en mémoire est étudié, et de nouvelles techniques de calculs booléens robustes et à faible impact surfacique sont développées. Dans le contexte des réseaux de neurones, de nouveaux accélérateurs neuromorphiques à base de ReRAM sont proposés et caractérisés, visant une bonne robustesse face à la variabilité, un bon parallélisme et une efficacité énergétique élevée. Dans un deuxième temps, pour résoudre les problèmes de densité d'intégration, une nouvelle technologie de cube mémoire 3D à base de ReRAM 1T1R est proposée, pouvant à la fois être utilisée en tant que mémoire de type NOR 3D dense qu'en tant qu'accélérateur pour l'I/NMC
With the advent of edge devices and artificial intelligence, the data deluge is a reality, making energy-efficient computing systems a must-have. Unfortunately, classical von Neumann architectures suffer from the high cost of data transfers between memories and processing units. At the same time, CMOS scaling seems more and more challenging and costly to afford, limiting the chips' performance due to power consumption issues.In this context, bringing the computation directly inside or near memories (I/NMC) seems an appealing solution. However, data-centric applications require an important amount of non-volatile storage, and modern Flash memories suffer from scaling issues and are not very suited for I/NMC. On the other hand, emerging memory technologies such as ReRAM present very appealing memory performances, good scalability, and interesting I/NMC features. However, they suffer from variability issues and from a degraded density integration if an access transistor per bitcell (1T1R) is used to limit the sneak-path currents. This thesis work aims to overcome these two challenges. First, the variability impact on read and I/NMC operations is assessed and new robust and low-overhead ReRAM-based boolean operations are proposed. In the context of neural networks, new ReRAM-based neuromorphic accelerators are developed and characterized, with an emphasis on good robustness against variability, good parallelism, and high energy efficiency. Second, to resolve the density integration issues, an ultra-dense 3D 1T1R ReRAM-based Cube and its architecture are proposed, which can be used as a 3D NOR memory as well as a low overhead and energy-efficient I/NMC accelerator
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Conference papers on the topic "3D ReRAM"

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Fukuda, Natsuki, Yutaka Nishioka, and Koukou Suu. "TaOx-based ReRAM stack with NbOx-based selector for 3D cross-point ReRAM application." In 2014 Silicon Nanoelectronics Workshop (SNW). IEEE, 2014. http://dx.doi.org/10.1109/snw.2014.7348604.

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Lee, Edward, Daehyun Kim, Venkata Chaitanya Krishna Chekuri, Yun Long, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler with Layout-Precise Performance Evaluation." In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2019. http://dx.doi.org/10.1109/s3s46989.2019.9320750.

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Yi-Chung Chen, Hai Li, Yiran Chen, and R. E. Pino. "3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763289.

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Huangfu, Wenqin, Shuangchen Li, Xing Hu, and Yuan Xie. "RADAR: A 3D-ReRAM based DNA Alignment Accelerator Architecture." In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). IEEE, 2018. http://dx.doi.org/10.1109/dac.2018.8465882.

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Adam, Gina C., Bhaswar Chrakrabarti, Hussein Nili, Brian Hoskins, Miguel A. Lastras-Montano, Advait Madhavan, Melika Payvand, et al. "3D ReRAM arrays and crossbars: Fabrication, characterization and applications." In 2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2017. http://dx.doi.org/10.1109/nano.2017.8117387.

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Velasquez, Alvaro, and Sumit Kumar Jha. "Computation of Boolean matrix chain products in 3D ReRAM." In 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2017. http://dx.doi.org/10.1109/iscas.2017.8050962.

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Chien, W. C., F. M. Lee, Y. Y. Lin, M. H. Lee, S. H. Chen, C. C. Hsieh, E. K. Lai, et al. "Multi-layer sidewall WOX resistive memory suitable for 3D ReRAM." In 2012 IEEE Symposium on VLSI Technology. IEEE, 2012. http://dx.doi.org/10.1109/vlsit.2012.6242507.

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Huang, Yu, Long Zheng, Xiaofei Liao, Hai Jin, Pengcheng Yao, and Chuangyi Gui. "RAGra: Leveraging Monolithic 3D ReRAM for Massively-Parallel Graph Processing." In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019. http://dx.doi.org/10.23919/date.2019.8715192.

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Liu, Bosheng, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, and Peng Liu. "F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM." In 2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE, 2021. http://dx.doi.org/10.1109/dac18074.2021.9586135.

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Amir, Mohammad Faisal, and Saibal Mukhopadhyay. "3D Stacked High Throughput Pixel Parallel Image Sensor with Integrated ReRAM Based Neural Accelerator." In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2018. http://dx.doi.org/10.1109/s3s.2018.8640151.

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