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Journal articles on the topic '32 NM TECHNOLOGY NODE'

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Published: 11 September 2023

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1

Allgair, John, Benjamin Bunday, Aaron Cordes, Pete Lipscomb, Milt Godwin, Victor Vartanian, Michael Bishop, Doron Arazi, and Kye-Weon Kim. "Metrology Requirements for the 32 nm Technology Node and Beyond." ECS Transactions 18, no. 1 (December 18, 2019): 151–60. http://dx.doi.org/10.1149/1.3096443.

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Huang, Zhengfeng, Di Cao, Jianguo Cui, Yingchun Lu, Yiming Ouyang, Haochen Qi, Qi Xu, Huaguo Liang, and Tianming Ni. "Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology." Journal of Computer-Aided Design & Computer Graphics 33, no. 3 (March 1, 2021): 346–55. http://dx.doi.org/10.3724/sp.j.1089.2021.18385.

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Huang, Zhengfeng, Yang Guo, Shangjie Pan, Yingchun Lu, Huaguo Liang, Haochen Qi, Yiming Ouyang, Tianming Ni, and Qi Xu. "Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology." Journal of Computer-Aided Design & Computer Graphics 32, no. 12 (December 1, 2020): 2013–20. http://dx.doi.org/10.3724/sp.j.1089.2020.18160.

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Ono, Kazuo, Kenzo Kurotsuchi, Yoshihisa Fujisaki, Riichiro Takemura, Motoyasu Terao, and Norikatsu Takaura. "Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond." Japanese Journal of Applied Physics 48, no. 4 (April 20, 2009): 04C160. http://dx.doi.org/10.1143/jjap.48.04c160.

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5

Orlowski, Marius, and Andreas Wild. "Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?" ECS Transactions 3, no. 6 (December 21, 2019): 3–17. http://dx.doi.org/10.1149/1.2357050.

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6

Park, Dae-Gyu, Mike Chudzik, and Haizhou Yin. "Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond." ECS Transactions 11, no. 6 (December 19, 2019): 371–77. http://dx.doi.org/10.1149/1.2778394.

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7

Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (June 17, 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.
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Kumar, Amresh, and Aminul Islam. "Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node." Microsystem Technologies 23, no. 9 (July 6, 2016): 4099–109. http://dx.doi.org/10.1007/s00542-016-3055-4.

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9

Andrieu, F., O. Weber, T. Ernst, O. Faynot, and S. Deleonibus. "Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node." Microelectronic Engineering 84, no. 9-10 (September 2007): 2047–53. http://dx.doi.org/10.1016/j.mee.2007.04.132.

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10

Collaert, N., R. Rooyackers, A. Hikavyy, A. Dixit, F. Leys, P. Verheyen, R. Loo, M. Jurczak, and S. Biesemans. "Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth." Thin Solid Films 517, no. 1 (November 2008): 101–4. http://dx.doi.org/10.1016/j.tsf.2008.08.031.

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11

Sankar, P. A. Gowri, and K. Udhayakumar. "Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes." Journal of Low Power Electronics 10, no. 4 (December 1, 2014): 602–16. http://dx.doi.org/10.1166/jolpe.2014.1355.

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12

Morgenfeld, Bradley. "Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes." Journal of Micro/Nanolithography, MEMS, and MOEMS 11, no. 1 (March 19, 2012): 013010. http://dx.doi.org/10.1117/1.jmm.11.1.013010.

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13

Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.
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14

Sharma, Vijay Kumar, and Manisha Pattanaik. "Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library." Journal of Circuits, Systems and Computers 25, no. 11 (August 14, 2016): 1650134. http://dx.doi.org/10.1142/s0218126616501346.

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In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8[Formula: see text]V by using Silvaco’s EDA tools. All generated cells have same cell height of 1.58 [Formula: see text]m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS’85 benchmark circuits 74181 and c17 are designed and verified with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications.
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15

Trojman, Lionel, Eduardo Holguin, Marco Villegas, Luis-Miguel Procel, and Ramiro Taco. "From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits." Electronics 11, no. 4 (February 10, 2022): 525. http://dx.doi.org/10.3390/electronics11040525.

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In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.
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16

Bourgeat, Johan, and Philippe Galy. "Single and compact ESD device Beta-Matrix solution based on bidirectional SCR Network in advanced 28/32 nm technology node." Solid-State Electronics 87 (September 2013): 34–42. http://dx.doi.org/10.1016/j.sse.2013.04.033.

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17

Mannaert, G., L. Witters, Denis Shamiryan, Werner Boullart, K. Han, S. Luo, A. Falepin, R. Sonnemans, Ivan L. Berry, and Carlo Waldfried. "Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond." Solid State Phenomena 145-146 (January 2009): 253–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.253.

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The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.
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18

Hussin, H., N. Soin, M. F. Bukhori, S. Wan Muhamad Hatta, and Y. Abdul Wahab. "Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs." Scientific World Journal 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/490829.

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We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping inE′center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-kPMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2are increased but is reduced by 11% when the SiO2interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.
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19

Wada, Masayuki, H. Takahashi, J. Snow, Rita Vos, P. W. Mertens, and H. Shirakawa. "Applicable Solvent Photoresist Strip Process for High-K/Metal Gate." Solid State Phenomena 187 (April 2012): 105–8. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.105.

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In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.
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20

Pham, Huyen Thi, Hung Tuan Dao, and Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder." Journal of Science and Technology on Information security 9, no. 01 (April 9, 2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.

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Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.Tóm tắt— Các mã LDPC phi nhị phân (NB-LDPC) vượt trội so với các mã LDPC nhị phân về chất lượng sửa lỗi và thuộc tính lỗi san bằng khi chiều dài là trung bình. Tuy nhiên, nhược điểm của các bộ giải mã NB-LDPC là tính phức tạp cao và độ phức tạp tăng đáng kể khi bậc của trường Galois cao. Trong bài báo này, thuật toán Trellis Min-Max dựa trên tập cơ sở được đơn giản hóa được đề xuất cho xử lý nốt biến mà hiệu quả cho các trường Galois bậc cao để giảm độ phức tạp của khối nốt biến (VNU) cũng như cả bộ giải mã. Kiến trúc bộ giải mã tương ứng với thuật toán đề xuất được thiết kế cho mã NB-LDPC (837, 726) thông qua trường GF(32). Các kết quả thực hiện sử dụng công nghệ CMOS 90-nm chỉ ra rằng kiến trúc bộ giải mã được đề xuất giảm số lượng cổng logic 21,35% và 9,4% với chất lượng sửa lỗi gần như không thay đổi so với các nghiên cứu gần đây.
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21

Feruglio, S., F. Andrieu, O. Faynot, and G. Ghibaudo. "Low-temperature electrical characterization of fully depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 gate stack for the 32-nm technology node." Cryogenics 49, no. 11 (November 2009): 605–10. http://dx.doi.org/10.1016/j.cryogenics.2008.12.004.

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22

Jin, Yurin, Yeonho Seo, Sungmi Kim, and Seongik Cho. "Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero." Electronics 12, no. 11 (May 23, 2023): 2361. http://dx.doi.org/10.3390/electronics12112361.

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Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V.
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23

Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.
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24

Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (May 31, 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.
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25

Cho, Sangki, Sueyeon Kim, Insoo Choi, Myounggon Kang, Seungjae Baik, and Jongwook Jeon. "Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor." AIP Advances 13, no. 4 (April 1, 2023): 045211. http://dx.doi.org/10.1063/5.0141131.

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Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.
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26

Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (February 5, 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.

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Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.
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27

Ahmed Khan, Imran. "Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications." Journal of Physics: Conference Series 2161, no. 1 (January 1, 2022): 012050. http://dx.doi.org/10.1088/1742-6596/2161/1/012050.

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Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.
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28

Sharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (March 9, 2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.

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With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.
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29

Amin, Abu Bony, Syed Muhammad Shakil, and Muhammad Sana Ullah. "A Theoretical Modeling of Adaptive Mixed CNT Bundles for High-Speed VLSI Interconnect Design." Crystals 12, no. 2 (January 27, 2022): 186. http://dx.doi.org/10.3390/cryst12020186.

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The aroused quest to reduce the delay at the interconnect level is the main urge of this paper, so as to come across a configuration of carbon nanotube (CNT) bundles, namely, squarely packed bundles of mixed CNTs. The demonstrated approach in this paper makes the mixed CNT bundle adaptable to adopt for high-speed very-large-scale integration (VLSI) interconnects with technology shrinkage. To reduce the delay of the proposed configuration of the mixed CNT bundle, the behavioral change of resistance (R), inductance (L), and capacitance (C) has been observed with respect to both the width of the bundle and the diameter of the CNTs in the bundle. Consequently, the performance of the modified bundle configuration is compared with a previously developed configuration, namely, squarely packed bundles of dimorphic MWCNTs in terms of propagation delay and crosstalk delay at local-, semiglobal-, and global-level interconnects. The proposed bundle configuration is, ultimately, enacted as the better one for 32-nm and 16-nm technology nodes, and is suitable for 7-nm nodes as well.
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30

Garg, Sandeep, and Tarun K. Gupta. "A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology." Journal of Circuits, Systems and Computers 28, no. 10 (September 2019): 1950165. http://dx.doi.org/10.1142/s0218126619501652.

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In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.
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31

Zhu, Yihan, and Takashi Ohsawa. "A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters." Japanese Journal of Applied Physics 61, SC (February 21, 2022): SC1053. http://dx.doi.org/10.35848/1347-4065/ac44ce.

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Abstract A novel loadless four-transistor static random access memory (4T SRAM) cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32 nm technology node that the read static noise margin (SNM) of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold SNM can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.
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32

Ghasemian, Arsalan, Ebrahim Abiri, Kourosh Hassanli, and Abdolreza Darabi. "HF-QSRAM: Half-Select Free Quaternary SRAM Design with Required Peripheral Circuits for IoT/IoVT Applications." ECS Journal of Solid State Science and Technology 11, no. 1 (January 1, 2022): 011002. http://dx.doi.org/10.1149/2162-8777/ac4798.

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By using CNFET technology in 32 nm node by the proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered. Various simulations on temperature, supply voltage, and access frequency have been done to evaluate and ensure the performance of the proposed SQI gate, suggested cells, and quaternary to binary decoder. Moreover, 1000 Monte-Carlo analyses on the fabrication parameters have been done to classify read and write delay and standby power of proposed cells along with PDP of the proposed quaternary to binary decoder. It is worth mentioning that the PDP of the proposed SQI gate, decoder, and average power consumption of suggested HF-QSRAM cell reached 0.92 aJ, 4.13 aJ, and 0.15 μW, respectively, which are approximately 80%, 91%, and 33% improvements in comparison with the best existing designs in the literature.
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33

Bendre, Varsha S., A. K. Kureshi, and Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier." Journal of Nanotechnology 2018 (December 4, 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.
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34

Lai, Fu-Der, and Jian Long Huang. "Proposed single layer composite film used as high transmission phase shifting masks for the 32, 45, and 65 nm technology nodes." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, no. 6 (2007): 1799. http://dx.doi.org/10.1116/1.2790920.

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35

Bhuvana, B. P., and V. S. Kanchana Bhaaskaran. "Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures." Journal of Circuits, Systems and Computers 29, no. 01 (April 23, 2019): 2050016. http://dx.doi.org/10.1142/s0218126620500164.

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This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.
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36

Dadoria, Ajay Kumar, Kavita Khare, Tarun Kumar Gupta, and R. P. Singh. "New Leakage Reduction Techniques for FinFET Technology with Its Application." Journal of Circuits, Systems and Computers 27, no. 07 (March 26, 2018): 1850112. http://dx.doi.org/10.1142/s0218126618501128.

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This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32[Formula: see text]nm technology node at 25[Formula: see text]C and 110[Formula: see text]C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10[Formula: see text]MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25[Formula: see text]C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% in SG mode and in LP mode a maximum saving of 95.10% at 25[Formula: see text]C is achieved. Similarly, DGNPT saves 99.34% in SG mode and in LP mode it saves 99.90% leakage power at 25[Formula: see text]C with respect to conventional gates. The proposed techniques are also applied on different benchmark circuits and the results are validated. As an application of the proposed techniques, NAND gate is modified accordingly and it is used in 1-bit and 2-bit full-adder circuits.
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37

Bhattacharya, Sandip, Debaprasad Das, and Hafizur Rahaman. "Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850001. http://dx.doi.org/10.1142/s0218126618500019.

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The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16[Formula: see text]nm ITRS technology node. A [Formula: see text] standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10[Formula: see text][Formula: see text]m interconnect length at temperatures (233[Formula: see text]K, 300[Formula: see text]K and 378[Formula: see text]K). Our analysis shows that MLGNR exhibits ([Formula: see text]–[Formula: see text]) less SSN and ([Formula: see text]–[Formula: see text]) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52–32% (at 233[Formula: see text]K), 53–32% (at 300[Formula: see text]K) and 52–30% (at 378[Formula: see text]K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54–31% (at 233[Formula: see text]K), 57–29% (at 300[Formula: see text]K) and 57–26% (at 378[Formula: see text]K) less than that of Cu-based power interconnects.
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38

Park, Jun-Young, Minhyun Jin, Soo-Youn Kim, and Minkyu Song. "Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips." Electronics 11, no. 6 (March 10, 2022): 877. http://dx.doi.org/10.3390/electronics11060877.

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In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.
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39

Decoster, Stefan, Elisabeth Camerotto, Gayle Murdoch, Souvik Kundu, Quoc Toan Le, Zsolt Tőkei, Gosia Jurczak, and Frédéric Lazzarino. "Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below." Journal of Vacuum Science & Technology B 40, no. 3 (May 2022): 032802. http://dx.doi.org/10.1116/6.0001791.

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Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of <10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implemented without barrier. An integration scheme with direct metal etch instead of damascene patterning could simplify the overall patterning flow and eventually opens the possibility for exploring new integration concepts and patterning approaches. However, the learning on direct metal etch of Ru and Mo in the literature is scarce, especially at the relevant dimensions of today's interconnects. In this work, we will focus on the major patterning challenges we have encountered during the development of direct metal etch processes for Ru at 18 nm pitch and Mo gratings at 32 nm pitch. We have observed that the direct metal etch of Ru at these small dimensions is impacted by the growth of an oxidized layer on the sidewalls of the hard mask, which originates from the sputtering of the hard mask in combination with the O2-based Ru etch chemistry. This results in a narrowing of the trenches to be patterned and can easily lead to an etch stop in the smallest features. We will discuss several mitigation mechanisms to remove this oxidized layer, as well as to avoid the formation of such a layer. For patterning Mo with a Cl2/O2-based chemistry, the major patterning challenges we encountered are the insufficient sidewall passivation and the oxidation of the patterned Mo lines. The sidewall passivation issue has been overcome with an in situ thin SiO2-like deposition after partial Mo etch, while a possible mitigation mechanism for the Mo oxidation could be the in situ encapsulation immediately after Mo patterning.
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40

Decoster, Stefan, Elisabeth Camerotto, Gayle Murdoch, Souvik Kundu, Quoc Toan Le, Zsolt Tőkei, Gosia Jurczak, and Frédéric Lazzarino. "Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below." Journal of Vacuum Science & Technology B 40, no. 3 (May 2022): 032802. http://dx.doi.org/10.1116/6.0001791.

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Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of <10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implemented without barrier. An integration scheme with direct metal etch instead of damascene patterning could simplify the overall patterning flow and eventually opens the possibility for exploring new integration concepts and patterning approaches. However, the learning on direct metal etch of Ru and Mo in the literature is scarce, especially at the relevant dimensions of today's interconnects. In this work, we will focus on the major patterning challenges we have encountered during the development of direct metal etch processes for Ru at 18 nm pitch and Mo gratings at 32 nm pitch. We have observed that the direct metal etch of Ru at these small dimensions is impacted by the growth of an oxidized layer on the sidewalls of the hard mask, which originates from the sputtering of the hard mask in combination with the O2-based Ru etch chemistry. This results in a narrowing of the trenches to be patterned and can easily lead to an etch stop in the smallest features. We will discuss several mitigation mechanisms to remove this oxidized layer, as well as to avoid the formation of such a layer. For patterning Mo with a Cl2/O2-based chemistry, the major patterning challenges we encountered are the insufficient sidewall passivation and the oxidation of the patterned Mo lines. The sidewall passivation issue has been overcome with an in situ thin SiO2-like deposition after partial Mo etch, while a possible mitigation mechanism for the Mo oxidation could be the in situ encapsulation immediately after Mo patterning.
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41

Lai, Fu-Der, Jui-Ming Hua, C. Y. Huang, Fu-Hsiang Ko, L. A. Wang, C. H. Lin, C. M. Chang, S. Lee, and Gia-Wei Chern. "ArF-line high transmittance attenuated phase shift mask blanks using amorphous Al2O3–ZrO2–SiO2 composite thin films for the 65-, 45- and 32-nm technology nodes." Thin Solid Films 496, no. 2 (February 2006): 247–52. http://dx.doi.org/10.1016/j.tsf.2005.08.382.

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42

Kim, Youngbae, Shuai Li, Nandakishor Yadav, and Kyuwon Ken Choi. "A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks." Electronics 10, no. 17 (September 6, 2021): 2181. http://dx.doi.org/10.3390/electronics10172181.

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We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.
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43

Bilouk, Sabrina, Carole Pernel, Lucile Broussous, Valentina Ivanova, and Ricardo Nogueira. "Electrochemical Behavior of Cobalt in Post-Via Etch Cleaning Solutions." Solid State Phenomena 145-146 (January 2009): 343–46. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.343.

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The integration of CoWP and CoWB self-aligned barriers (SAB) for 32 nm technology nodes allows improving copper interconnections reliability [1, 3]. However the introduction of such materials in copper interconnection levels drives new challenges for plasma dry etch and wet clean processes. Indeed, during the post-via-etch cleaning step, cobalt and copper can be altered by corrosion. Moreover, a galvanic coupling between cobalt, the major component of SAB, and copper can thermodynamically occur. In this way, the cleaning solution acts as ionic medium providing a contact between the two metals. Thus, both metals polarize to a mixed potential comprised between the individual open circuit potentials (OCP) of cobalt and copper. As a result, the less noble metal can suffer from accelerated corrosion, and the more noble metal corrodes with slower rate. According to thermodynamic aspects, cobalt in contact with copper is the less noble metal. Consequently, Co is susceptible to undergo galvanic corrosion which may enhance the dissolution of the SAB.
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44

Kang, Bong Kyun, Ji Hyun Jeong, Min Su Kim, Hong Seong Sohn, Ahmed A. Busnaina, and Jin Goo Park. "Acoustic Cavitation Behavior in Isopropyl Alcohol Added Cleaning Solution." Solid State Phenomena 195 (December 2012): 169–72. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.169.

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As the semiconductor manufacturing technology for ultra-high integration devices continue to shrink beyond 32 nm, stringent measures have to be taken to get damage free patterns during the cleaning process. The patterns are no longer cleaned with the megasonic (MS) irradiation in the advanced device node because of severe pattern damages caused by cleaning. Recently, several investigations are carried out to control the cavitation effects of megasonic to reduce the pattern damages. The mechanism of damage caused by an unstable acoustic bubble motion was mainly attributed to the high sound pressure associated with violent bubble collapse [1]. In order to characterize the dominant factors affecting the cavitation, MS cleaning was conducted with various dissolved gas concentrations in water. It was reported that the cavitation phenomena relating to particle removal efficiency (PRE) and pattern damage were considerably changed with the addition of a specific gas [2]. This changing behavior may be due to the difference in the physical properties of dissolved gases associated with acoustic bubble growth rate as a function of their concentration. In particular, cavitation effects induced during MS cleaning was controlled by adjusting the acoustic bubble growth rate. Also the change of bubble growth rate is well explained by both rectified diffusion for single bubble and bubble coalescence for multi-bubble, respectively. Similarly, it is well-known that surface active solute (SAS) in the ultrasound field plays an important role in controlling the cavitation effects. A detailed explanation of the acoustic bubble growth rate, cavitation threshold and their relationship with various types of SAS and concentration of biomedical and chemical reactions perspective have been reported elsewhere [3,4]. Their studies demonstrated that the change of cavitation effects depends not only on the chain length of alcohol in the solution but also on the physical properties such as surface tension and viscosity of SAS solutions.
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45

Ganesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.

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This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.
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46

Itani, Toshiro. "157 nm Lithography for 70 nm Technology Node." Japanese Journal of Applied Physics 41, Part 1, No. 6B (June 30, 2002): 4033–36. http://dx.doi.org/10.1143/jjap.41.4033.

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47

Park, Joon-Min, Ilsin An, and Hye-Keun Oh. "Resist Reflow Process for 32 nm Node Arbitrary Pattern." Japanese Journal of Applied Physics 48, no. 4 (April 20, 2009): 046501. http://dx.doi.org/10.1143/jjap.48.046501.

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48

Elangovan, M., and K. Gunavathi. "High Stable and Low Power 8T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 05 (August 2, 2019): 2050080. http://dx.doi.org/10.1142/s0218126620500802.

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Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.
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49

Thornton, Trevor J., William Lepkowski, and Seth J. Wilk. "Impact Ionization in SOI MESFETs at the 32-nm Node." IEEE Transactions on Electron Devices 63, no. 10 (October 2016): 4143–46. http://dx.doi.org/10.1109/ted.2016.2601241.

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50

Petrillo, Karen, Yayi Wei, R. Brainard, G. Denbeaux, Dario Goldfarb, C. S. Koay, J. Mackey, et al. "Are extreme ultraviolet resists ready for the 32 nm node?" Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, no. 6 (2007): 2490. http://dx.doi.org/10.1116/1.2787815.

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