Academic literature on the topic '2T Memory Architecture'

Data transfer between a processor and memory frequently represents a bottleneck with respect to improving application-level performance. Computing-in-memory (CiM), where logic and arithmetic operations are performed in memory, could significantly reduce both energy consumption and computational overheads associated with data transfer. This work presents a revisited study of FeFET-CiM, a CiM architecture capable of performing Boolean ((N)AND, (N)OR, X(N)OR, INV) as well as arithmetic (ADD) operations between words in memory. In this study, we employ two types of FeFET-based memory cells in the CiM architecture. Namely, the 2T+1FeFET and the 1-FeFET memory cells. The use of these two types of memory cells in the FeFET-CiM architecture is enabled by two distinct models for FeFET devices. The FeFET-CiM architecture based on 2T+1FeFETs (1FeFETs) offers an average speedup of ∼2.5X (∼1.1X) and energy reduction of ∼1.7X (∼1.4X) when compared to a SRAM baseline across 12 benchmark programs. Despite smaller speedups and energy savings enabled by 1FeFET-CiM when compared to 2T+1FeFET-CiM, 1FeFET memory arrays may offer up to ∼5.3X density improvements when compared to conventional 6T-SRAM arrays. Furthermore, 1FeFET-CiM offers significant application-level improvements when compared to a counterpart STT-CiM architecture.

AbstractIn-memory computing may enable multiply-accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). Performing MAC operations with high capacity in a small area with high energy efficiency remains a challenge. In this work, we propose a circuit architecture that integrates monolayer MoS2 transistors in a two-transistor–one-capacitor (2T-1C) configuration. In this structure, the memory portion is similar to a 1T-1C Dynamic Random Access Memory (DRAM) so that theoretically the cycling endurance and erase/write speed inherit the merits of DRAM. Besides, the ultralow leakage current of the MoS2 transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The electrical characteristics of a single MoS2 transistor also allow analog computation by multiplying the drain voltage by the stored voltage on the capacitor. The sum-of-product is then obtained by converging the currents from multiple 2T-1C units. Based on our experiment results, a neural network is ex-situ trained for image recognition with 90.3% accuracy. In the future, such 2T-1C units can potentially be integrated into three-dimensional (3D) circuits with dense logic and memory layers for low power in-situ training of neural networks in hardware.

L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle architecture mémoire a été proposée : la cellule BitErasable. Elle a montré une excellente fiabilité et a permis d’apporter des éléments de compréhension sur les mécanismes de dégradation présents dans ces dispositifs mémoires à transistor de sélection enterré. Cette nouvelle architecture offre de plus la possibilité d’effacer les cellules d’un plan mémoire de façon individuelle : bit à bit. Conscient du grand intérêt que présente l’effacement bit à bit, un nouveau mécanisme d’effacement pour injection de trous chauds a été proposé pour la cellule eSTM. Il a montré des performances et un niveau de fiabilité parfaitement compatible avec les exigences industrielles des applications Flash-NOR
The objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications