Relevant bibliographies by topics / 2d-3d tcad

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  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic '2d-3d tcad'

Author: Grafiati
Published: 20 July 2023

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Journal articles on the topic "2d-3d tcad"

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IÑIGUEZ, BENJAMIN, ROMAIN RITZENTHALER, and FRANÇOIS LIME. "COMPACT MODELING OF DOUBLE AND TRI-GATE MOSFETs." International Journal of High Speed Electronics and Systems 22, no. 01 (November 2013): 1350004. http://dx.doi.org/10.1142/s0129156413500043.

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This chapter presents some insights into the modeling of different Multi-Gate SOI MOSFET structures, and in particular Double-Gate MOSFETs (DG MOSFETs) and Tri-Gate MOSFETs (TGFETs). For long-channel case an electrostatic model can be developed from the solution of the 1D Poisson's equation (in the case of DG MOSFETs) and the 2D Poisson's equation in the section perpendicular to the channel (in the case of TGFETs). Allowing it to be incorporated in quasi-2D compact models. For short-channel devices a model can be derived from a 2D (in the case of DG MOSFETs) or a 3D (in the case of TGFETs) electrostatic analysis. The models were successfully compared with 2D and 3D TCAD simulations and, in some cases, experimental measurements. Short-channel effects, such as subthrehold slope degradation, threshold voltage roll-off and DIBL were accurately reproduced.
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Rahimo, Munaf T., Iulian Nistor, and David Green. "Advanced 1200V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology." Materials Science Forum 1062 (May 31, 2022): 539–43. http://dx.doi.org/10.4028/p-u88313.

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This paper presents a Singular Point Source MOS (S-MOS) cell concept suitable for SiC MOSFETs targeting low conduction losses, low switching losses and high robustness. The S-MOS concept differs from standard Planar or Trench MOS cells in the manner by which the total channel width per device area is determined. For the proof of concept and device electrical performance evaluation, the paper will provide 2D and 3D TCAD simulations results for 1200V SiC MOSFETs including the S-MOS and reference planar and trench structures.
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Aguirre, P., M. Rau, and A. Schenk. "2D and 3D TCAD simulation of III-V channel FETs at the end of scaling." Solid-State Electronics 159 (September 2019): 123–28. http://dx.doi.org/10.1016/j.sse.2019.03.043.

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Dash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra, and C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.

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Background:: In nano and microelectronics, device performance enhancement is limited by downscaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. This paper explores the key design challenges of stress-engineered FinFETs based on the epitaxial SiGe S/D at 7 nm Technology node. Objective:: To study the mechanical stress evolution in a tri-gate FinFET at 7 nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the devices through device simulation. Methods: 3D sub-band Boltzmann transport analysis for tri-gate PMOS FinFETs was used, with 2D Schrödinger solution in the fin cross-section and 1D Boltzmann transport along the channel. Results:: Using stress maps, the mechanical stress impact on the transfer characteristics of the device through device simulation has been analyzed. Conclusion:: Suitability of predictive TCAD simulations to explore the potential of innovative strain-engineered FinFET structures for future generation CMOS technology is demonstrated.
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Mo, Fei, Xiaoran Mei, Takuya Saraya, Toshiro Hiramoto, and Masaharu Kobayashi. "A simulation study on memory characteristics of InGaZnO-channel ferroelectric FETs with 2D planar and 3D structures." Japanese Journal of Applied Physics 61, SC (February 9, 2022): SC1013. http://dx.doi.org/10.35848/1347-4065/ac3d0e.

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Abstract We have investigated the memory characteristics of InGaZnO (IGZO)-channel ferroelectric FETs (FeFETs) with 2D planar and 3D structures by TCAD simulation to improve the memory window (MW) with a floating-body channel for high-density memory applications. From the study on 2D planar FeFETs with a single gate and a double gate, the MW depends on channel length (L) and is enhanced with shorter L due to stronger electrostatic coupling from the source and drain to the center region of the IGZO layer. From the study on 3D structure FeFETs with macaroni (MAC) and nanowire (NW) structures, a large MW can be obtained especially in NW FeFETs due to the electric field concentration by Gauss’s law in the 3D electrostatics. Furthermore, we have systematically studied and discussed the device design of MAC and NW structure FeFETs in terms of the diameter and thickness for high-density memory applications. As the IGZO thickness and the outer diameter of the IGZO layer decrease, the MW increases due to the voltage divider and the electric field concentration. The device parameters that can maximize the MW can be determined under the constraints of the layout and material based on this study.
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Rahimo, Munaf, Iulian Nistor, and David Green. "Suppression of Short Channel Effects for a SiC MOSFET Based on the S-MOS Cell Concept." Key Engineering Materials 945 (May 19, 2023): 83–89. http://dx.doi.org/10.4028/p-g4w5h5.

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This paper investigates the short channel effects (SCE) of the recently proposed Singular Point Source MOS (S-MOS) SiC MOSFET. The study was carried out using 2D and 3D TCAD simulations for a planar, trench and S-MOS 1200V SiC MOSFETs for the IV output characteristics up to 1200V and under short circuit transient conditions. The S-MOS device shows no SCE up to the rated voltage when compared to reference planar and trench devices which exhibit strong SCE. This is due to the appropriate P++ protection of the N++ source and the electric field shielding due to the narrow mesa dimensions between orthogonal trenches where the channel is located.
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Italia, Markus, Ioannis Deretzis, Alfio Nastasi, Silvia Scalese, Antonino La Magna, Massimo Pirnaci, Daniele Pagano, Dario Tenaglia, and Patrizia Vasquez. "Multiscale Simulations of Plasma Etching in Silicon Carbide Structures." Materials Science Forum 1062 (May 31, 2022): 214–18. http://dx.doi.org/10.4028/p-n9v122.

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Manufacturing of Silicon Carbide (SiC) based devices will soon require the accuracy and control typical of the advanced Si based nanoelectronics. As a consequence, the processes development will surely benefit of technology computer aided design (TCAD) tools dedicated to the current and future SiC process technologies. Plasma etching is one of the most critical and difficult process for optimization procedures in the micro/nanofabrication area, since the resultant 2D (e.g. in trenches) or 3D (e.g in holes) profiling is the consequence of the complex interactions between plasma and materials in the device structures. In this contribution we present a simulation tool dedicated to the etching simulation of SiC structures based on the sequential combination of a plasma scale global model and feature scale Kinetic Monte Carlo simulations. As an example of the approach validation procedure the simulations are compared with the characterization analysis of particular real process results.
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Tripathi, Suman Lata. "Pocket Vertical Junction-Less U-Shape Tunnel FET and Its Challenges in Nano-Scale Regime." Advanced Science, Engineering and Medicine 11, no. 12 (December 1, 2019): 1225–30. http://dx.doi.org/10.1166/asem.2019.2466.

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Low voltage application of Tunnel FET with steep subthreshold slope, has potential to replace its MOSFET counterpart for future scaling due to thermal limits imposed on nano-level transistors. Longer channel region increases the tunneling area results in increasing tunneling current and decreasing miller capacitance to improve device switching performance for digital application. A new pocket tunnel junction-less UTFET (JLUTFET) exploits increased channel length with U shape and high ON current capability of junction-less transistor provide better device performance in subthreshold region showing improvement in ION/IOFF(∼109) as compared to other similar conventional TFET and vertical TFET structures. The proposed nJLUTFET also shows lower drain induced barrier lowering (<20 mV/V) and near to ideal subthreshold slope (∼66 mV/decade). The temperature analysis plays a vital role to decide a stable ON and OFF-state performance of transistors. So, the proposed pocket JLUTFET is investigated for temperature variations (ranging 250–400 K) to characterize the performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed n-channel JLUTFET has been designed on visual TCAD 2D/3D device simulator.
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Assiouras, P., P. Asenov, A. Kyriakis, and D. Loukas. "Fast calculation of capacitances in silicon sensors with 3D and 2D numerical solutions of the Laplace's equation and comparison with experimental data and TCAD simulations." Journal of Instrumentation 15, no. 11 (November 24, 2020): P11034. http://dx.doi.org/10.1088/1748-0221/15/11/p11034.

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Sulaiman, Raed, Pradip De, Jennifer C. Aske, Xiaoqian Lin, Adam Dale, Kris Gaster, Luis Rojas Espaillat, David Starks, and Nandini Dey. "A CAF-Based Two-Cell Hybrid Co-Culture Model to Test Drug Resistance in Endometrial Cancers." Biomedicines 11, no. 5 (April 29, 2023): 1326. http://dx.doi.org/10.3390/biomedicines11051326.

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The management of advanced or recurrent endometrial cancers presents a challenge due to the development of resistance to treatments. The knowledge regarding the role of the tumor microenvironment (TME) in determining the disease’s progression and treatment outcome has evolved in recent years. As a TME component, cancer-associated fibroblasts (CAFs) are essential in developing drug-induced resistance in various solid tumors, including endometrial cancers. Hence, an unmet need exists to test the role of endometrial CAF in overcoming the roadblock of resistance in endometrial cancers. We present a novel tumor–TME two-cell ex vivo model to test CAF’s role in resisting the anti-tumor drug, paclitaxel. Endometrial CAFs, both NCAFs (tumor-adjacent normal-tissue-derived CAFs) and TCAFs (tumor-tissue-derived CAFs) were validated by their expression markers. Both TCAFs and NCAFs expressed positive markers of CAF, including SMA, FAP, and S100A4, in varying degrees depending on the patients, while they consistently lacked the negative marker of CAF, EpCAM, as tested via flow cytometry and ICC. CAFs expressed TE-7 and immune marker, PD-L1, via ICC. CAFs better resisted the growth inhibitory effect of paclitaxel on endometrial tumor cells in 2D and 3D formats compared to the resistance of the tumoricidal effect of paclitaxel in the absence of CAFs. TCAF resisted the growth inhibitory effect of paclitaxel on endometrial AN3CA and RL-95-2 cells in an HyCC 3D format. Since NCAF similarly resisted the growth inhibitor action of paclitaxel, we tested NCAF and TCAF from the same patient to demonstrate the protective action of NCAF and TCAF in resisting the tumoricidal effect of paclitaxel in AN3CA in both 2D and 3D matrigel formats. Using this hybrid co-culture CAF and tumor cells, we established a patient-specific, laboratory-friendly, cost-effective, and time-sensitive model system to test drug resistance. The model will help test the role of CAFs in developing drug resistance and contribute to understanding tumor cell-CAF dialogue in gynecological cancers and beyond.
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Dissertations / Theses on the topic "2d-3d tcad"

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Bourgeat, Johan. "Etude du thyristor en technologies CMOS avancées pour implémentation dans des stratégies locale et globale de protection contre les décharges électrostatiques." Toulouse 3, 2011. http://thesesups.ups-tlse.fr/5671/.

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Les travaux présentés dans ce mémoire s'inscrivent dans le contexte de la protection des circuits intégrés contre les décharges électrostatiques (ESD) pour les nœuds technologiques très avancés tels que les nœuds CMOS45nm et CMOS32nm. La réduction des dimensions lithographiques ajoutée à l'introduction de nouveaux procédés technologiques ont contribué à accroître leur sensibilité aux ESD. Un parfait contrôle de l'environnement du circuit intégré et l'ajout d'éléments de protections dédiés permettent de réduire les dégradations induites par ce type d'évènement. Ce travail de thèse consiste ainsi à proposer de nouvelles protections basées sur l'utilisation du thyristor. Pour cela, une étude approfondie sur le fonctionnement du thyristor lors d'évènements ESD a été réalisée à l'aide de simulations TCAD en 3 dimensions. Cette étude permet d'investiguer différentes possibilités afin de moduler les paramètres principaux du thyristor. Pour permettre l'utilisation du thyristor en tant que protection locale située dans les plots d'alimentation, un circuit de déclenchement a été étudié et ajouté en CMOS45nm. Pour cela, l'optimisation du circuit a été réalisée au travers de simulations de type SPICE. Cette protection a été développée en CMOS32nm et améliorée en utilisant un thyristor bidirectionnel (triac). Enfin, une nouvelle stratégie de protection globale basée sur un réseau de trois thyristors bidirectionnels appelé "Beta Matrice" a été investiguée. Pour cela, une première étude s'est focalisée sur le développement de son circuit de déclenchement, une seconde sur l'optimisation topologique de la "Beta Matrice". Cette stratégie de protection a été validée sur du silicium CMOS32nm
The research work presented in this thesis addresses the issues related to the protection against electrostatic discharges (ESD) of integrated circuits in advanced technology nodes, CMOS45nm and CMOS32nm. The lithography dimension shrinking and the introduction of new technological process steps contribute to increase the ESD sensitivity. Excellent IC environment control together with the addition of dedicated protection circuits enable to decrease ESD failures. Thus, this research work consists to propose new protections based on the use of silicon controlled rectifier (SCR) devices. For that reason, a thorough study of the SCR behavior during ESD events has been carried out using three-dimensional TCAD simulations. This study enables the optimization of the main SCR parameters to improve its performance. To allow the SCR utilization as a local ESD protection with a power IO, a trigger circuit has been studied and firstly validated in CMOS45nm technology. Then, the trigger circuit optimization has been realized with SPICE simulations. The full protection has been developed in CMOS32nm and improved with bidirectional SCR (Triac). Finally, a new global protection strategy based on one network of three bidirectional SCRs, called "Beta-Matrix" has been investigated. A first study is focused on the development of its trigger circuit and a second one on the optimization of the "Beta-Matrix" topology. This protection strategy has been fully validated in CMOS32nm node
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Postel-Pellerin, Jérémy. "Fiabilité des Mémoires Non-Volatiles de type Flash en architectures NOR et NAND." Phd thesis, Université de Provence - Aix-Marseille I, 2008. http://tel.archives-ouvertes.fr/tel-00370377.

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Cette thèse étudie divers aspects de la fiabilité des mémoires, notamment les tests en endurance et les tenues en rétention sur des mémoires Flash, en architectures NOR et NAND. Nous abordons différentes méthodes de programmation existantes dans la littérature, à savoir l'utilisation de signaux très courts et un algorithme de programmation intelligent, que nous avons appliquées sur nos cellules mémoires afin de réduire la dégradation qu'elles subissent lors des phases successives de programmation /effacement. Les améliorations observées n'étant pas significatives, nous n'avons pas choisi d'utiliser de tels signaux dans la suite de notre étude. Nous présentons également une théorie des signaux optimisés qui n'a pas été approfondie ici mais que nous avons étudiée dans une étude préalable à cette thèse. Nous présentons ensuite une modélisation des pertes de charges en rétention à partir d'équations simples de types Fowler-Nordheim et Poole-Frenkel qui se superposent et respectivement prépondérantes à des temps de rétention élevés (t>200h) et courts (t<200h). Nous proposons enfin une étude des perturbations intervenant dans une matrice mémoire, à la fois du point de vue des tensions électriques appliquées sur les cellules mais aussi du point de vue des capacités de couplages parasites. Nous avons dans un premier temps évalué les valeurs de perturbation de grille sur des cellules mémoires Flash en architecture NOR puis NAND avant de traiter des capacités parasites entre cellules dans une matrice. Nous avons été amenés à étudier ces capacités dans la cadre de l'étude des dégradations excessives des cellules inhibées lors de tests en endurance pour certaines conditions process non-optimisées. Nous avons pour cela développé une simulation TCAD bidimensionnelle à partir des étapes process réelles que nous avons ensuite calibrée sur des mesures sur silicium. Enfin cette simulation a été complétée par une prise en compte des capacités parasites de couplage, extraites sur une simulation tridimensionnelle d'une matrice 3x3 de cellules mémoires. Les valeurs de ces capacités ont été validées par des mesures sur des structures de test spécifiques et par calcul géométrique. Notre simulation bidimensionnelle émule donc un comportement tridimensionnel tout en restant dans une rapidité de calcul liée à une simulation 2D. Nous avons ainsi pu développer des simulations électriques permettant de visualiser le phénomène d'inhibition des cellules, tout au long de l'application des diverses polarisations sur la structure.
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Book chapters on the topic "2d-3d tcad"

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Wu, Yung-Chun, and Yi-Ruei Jhan. "2D MOSFET Simulation." In 3D TCAD Simulation for CMOS Nanoeletronic Devices, 19–90. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3066-6_2.

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Conference papers on the topic "2d-3d tcad"

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Kaid, Achraf, Fabrice Roqueta, Jean-Baptiste Kammerer, and Luc Hebrard. "Electro-thermal Modeling Method of Protection Power Diodes Using TCAD 3D / 2D approach." In 2019 25th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC). IEEE, 2019. http://dx.doi.org/10.1109/therminic.2019.8923815.

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Postel-Pellerin, J., F. Lalande, P. Canet, R. Bouchakour, F. Jeuland, B. Bertello, and B. Villard. "A full 2D and 3D TCAD simulation of ultimate 22nm NAND Flash memories." In 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS 2009). IEEE, 2009. http://dx.doi.org/10.1109/nvmt.2009.5429787.

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Aguirre, P., M. Rau, and A. Schenk. "2D and 3D TCAD simulation of III-V channel FETs at the end of scaling." In 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 2018. http://dx.doi.org/10.1109/ulis.2018.8354744.

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Benistant, F., M. Bazizi, L. Jiang, J. H. M. Tng, and M. H. J. Goh. "Full 3D process/device simulations re-using 2D TCAD knowledge for optimizing N and P-type FinFET transistors." In 2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM). IEEE, 2014. http://dx.doi.org/10.1109/istdm.2014.6874650.

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Morabito, Caterina, Simone Guarnieri, Marika Berardini, Luisa Gesualdi, Francesca Ferranti, Anna Reale, Giulia Ricci, Angela Catizone, and Maria A. Mariggiò. "Microgravity-Induced Metabolic Response in 2D and 3D TCam-2 Cell Cultures." In Cells 2023. Basel Switzerland: MDPI, 2023. http://dx.doi.org/10.3390/blsf2023021007.

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