Relevant bibliographies by topics / 28nm

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  1. Journal articles
  2. Dissertations / Theses
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  4. Book chapters
  5. Conference papers
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Academic literature on the topic '28nm'

Author: Grafiati
Published: 9 March 2023
Last updated: 22 June 2025

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Journal articles on the topic "28nm"

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Kalia, Kartik, Khyati Nanda, Arushi Aggarwal, Akshita Goel, and Shivani Malhotra. "Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA." Advanced Materials Research 1098 (April 2015): 37–43. http://dx.doi.org/10.4028/www.scientific.net/amr.1098.37.

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In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.
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Chen, Fu Ping, Hai Bo Lei, Xiao Yan Zhang, et al. "High Performance, Eco-Friendly SPM Cleaning Technology Using Integrated Bench-Single Wafer Cleaning System." Solid State Phenomena 314 (February 2021): 133–39. http://dx.doi.org/10.4028/www.scientific.net/ssp.314.133.

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Batch SPM systems do not meet the current clean specification/requirements below 28nm. Single wafer SPM systems use a high volume of chemistry which runs to drain, while meeting the cleaning specifications below 28nm. The work in this paper describe the use of a batch SPM system and a single wafer clean in an integrated system, Ultra-C Tahoe which results in meeting the technical specification and using less that 80% of the SPM chemistry used in single wafer systems. The data collected shows this new system meet the specifications, whilst saving more than 80%of SPM chemistry.
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Zhang, Beichao, Bin Zhang, Haibo Xiao, et al. "Thin Film Challenges in 28nm Technology Node." ECS Transactions 44, no. 1 (2019): 391–94. http://dx.doi.org/10.1149/1.3694344.

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Aguiar, V. A. P., N. H. Medina, N. Added, et al. "Thermal neutron induced upsets in 28nm SRAM." Journal of Physics: Conference Series 1291 (July 2019): 012025. http://dx.doi.org/10.1088/1742-6596/1291/1/012025.

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Rochefeuille, E., F. Alicalapa, A. Douyère, and T. P. Vuong. "FDSOI 28nm performances study for RF energy scavenging." IOP Conference Series: Materials Science and Engineering 321 (March 2018): 012009. http://dx.doi.org/10.1088/1757-899x/321/1/012009.

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., Anshu Gaur. "HDL IMPLEMENTATION OF AMBA AHB ON 28NM FPGA." International Journal of Research in Engineering and Technology 06, no. 06 (2017): 148–53. http://dx.doi.org/10.15623/ijret.2017.0606024.

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Gupta, Arpit, Aarushi Sapra, Alisha Nagpal, and Sanchit Sharma. "Energy Efficient Traffic Light Controller Design on 28nm FGPA." International Journal of Smart Home 9, no. 10 (2015): 133–44. http://dx.doi.org/10.14257/ijsh.2015.9.10.15.

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Chandra Verma, Puneet, Pragya Agarwal, Apurva Omer, Bhaskar Gururani, and Sanchit Verma. "Designing Green ECG Machine Based on Artix7 28nm FPGA." Gyancity Journal of Engineering and Technology 3, no. 1 (2017): 38–44. http://dx.doi.org/10.21058/gjet.2017.31006.

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Phu Phu, Tran Nguyen, Dang Phuong Gia Han, Nguyen Cong Luong, and Nguyen Van Cuong. "Design A Synchronous Single-Port Sram 1024x32xMUX4 Using 28NM Technology." International Journal of Computing and Digital Systems 10, no. 1 (2021): 103–9. http://dx.doi.org/10.12785/ijcds/100110.

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Shi, I., E. Tian, and C. Ren. "Defect Investigation of the Develop Process on 28nm Contact Mask." ECS Transactions 60, no. 1 (2014): 199–204. http://dx.doi.org/10.1149/06001.0199ecst.

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Dissertations / Theses on the topic "28nm"

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Biswas, Avishek Ph D. Massachusetts Institute of Technology. "Energy-efficient SRAM design in 28nm FDSOI Technology." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91095.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>48<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 75-81).<br>As CMOS scaling continues to sub-32nm regime, the effects of device variations become more prominent. This is very critical in SRAMs, which use very small transistor dimensions to achieve high memory density. The conventional 6T SRAM bit-cell, which provides the smallest cell-area, fails to operate at lower supply voltages (Vdd). This is due to the significant degradation of functional margins as the supply voltage is scaled down. However, Vdd scaling is crucial in reducing the energy consumption of SRAMs, which is a significant portion of the overall energy consumption in modern micro-processors. Energy savings in SRAM is particularly important for batteryoperated applications, which run from a very constrained power-budget. This thesis focuses on energy-efficient 6T SRAM design in a 28nm FDSOI technology. Significant savings in energy/access of the SRAM is achieved using two techniques: Vdd scaling and data prediction. A 200mV improvement in the minimum SRAM operating voltage (Vdd,min) is achieved by using dynamic forward body-biasing (FBB) on the NMOS devices of the bit-cell. The overhead of dynamic FBB is reduced by implementing it row-wise. Layout modifications are proposed to share the body terminals (n-wells) horizontally, along a row. Further savings in energy/access is achieved by incoporating data-prediction in the 6T read path, which reduces bitline switching. The proposed techniques are implemented for a 128Kb 6T SRAM, designed in a 28nm FDSOI technology. This thesis also presents a reconfigurable fully-integrated switched-capacitor based step-up DC-DC converter, which can be used to generate the body-bias voltage for a SRAM. 3 reconfigurable conversion ratios of 5/2, 2/1 and 3/2 are implemented in the converter. It provides a wide range of output voltage, 1.2V-2.4V, from a fixed input of 1V. The converter achieves a peak efficiency of 88%, using only on-chip MOS and MOM capacitors, for a high density implementation.<br>by Avishek Biswas.<br>S.M.
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PIPINO, ALESSANDRA. "Design of Analog Circuits in 28nm CMOS Technology for Physics Applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/158126.

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Il trend esponenziale delle tecnologie CMOS previsto dalla legge di Moore è stato ampiamento dimostrato nel corso degli ultimi tre decenni. Si è osservato uno scaling costante, caratterizzato da dispositivi sempre più piccoli, per soddisfare le esigenze delle applicazioni digitali in termini di velocità, complessità, densità circuitale e basso consumo di potenza. Ogni nodo tecnologico è rappresentato dalla minima lunghezza ottenibile, che corrisponde alla lunghezza del canale del più piccolo transistor che si può integrare. Con l'arrivo delle tecnologie al di sotto dei 100nm, le performance dei circuiti digitali sono ulteriormente aumentate, a scapito dei progettisti analogici che si ritrovano ad affrontare nuove problematiche. Infatti, da una parte lo scaling tecnologico comporta dei vantaggi per i circuiti digitali: aumento della velocità, basso consumo di potenza, alto livello di integrazione. I circuiti analogici invece risentono negativamente dello scaling, a causa di un peggioramento del comportamento del transistor, soprattutto per le tecnologie ultra-scalate. In queste ultime infatti, effetti del secondo ordine, fino a prima del tutto trascurabili, diventano importanti e iniziano ad essere dominanti, influenzando il funzionamento e le performance dei dispositivi. Per esempio, basso guadagno intrinseco del MOS, swing ridotto, problemi di punto operativo e elevata variabilità dei parametri, sono solo alcune delle difficoltà derivanti dallo scaling. I progettisti analogici devono far fronte a questi problemi in diverse fasi della progettazione, sia circuitale che di layout. Nonostante ciò, la progettazione di circuiti analogici in tecnologie così scalate in molti casi è determinante. Per esempio, in molti sistemi mixed-signal, dove coesistono circuiti analogici e digitali e sono necessarie alte performance ad alta frequenza, l’uso di queste tecnologie anche per la parte analgica diventa una scelta obbligata. Oppure ci sono gli esperimenti di fisica ad alta energia, dove la scelta di tecnologie scalate è strategica. Infatti in queste applicazioni, i circuiti elettronici sono esposti ad alti livelli di radiazione con conseguente peggioramento delle performance e fenomeni di malfunzionamento. Dato che il danno da radiazione è proporzionale allo spessore dell'ossido, è evidente che per i dispositivi più piccoli, il danneggiamento è inferiore. In questa tesi, i trend e le principali problematiche derivanti dall'uso di tecnologie molto scalate sono analizzati nel primo capitolo, seguiti poi dalla presentazione di circuiti integrati in tecnologia CMOS 28nm. Il primo circuito presentato nel secondo capitolo è un Fast-Tracker front-end (FTfe) per la rilevazione di cariche. In particolare il sistema di read-out è stato implementato a partire dalle principali specifiche e soluzioni circuitali già usate per la rilevazione di muoni nell'esperimento ATLAS. Il front-end proposto è in grado di rilevare un evento e subito dopo resettare il sistema in maniera tale da rendere il FTfe già pronto per il prossimo evento, evitando lunghi tempi morti. Il secondo circuito, presentato nel terzo capitolo ed anch'esso integrato in tecnologia CMOS 28nm, è un amplificatore per strumentazione di tipo Chopper. Gli amplificatori per strumentazione sono elementi chiave nelle applicazioni per sensori, dove vengono usati per amplificare segnali tipicamente piccoli (dell'ordine dei mV) e a bassa frequenza. Per questo motivo risulta importante ridurre o addirittura eliminare l'offset e il rumore flicker in ingresso, segnali che si sovrappongono al segnale utile da rilevare ed introdotto dallo stesso circuito elettronico. L'amplificatore per strumentazione proposto usa una tecnica di modulazione, chiamata chopper, per ridurre i contributi di rumore flicker ed offset. Inoltre l'intero amplificatore è stato progettato per lavorare in regione di sottosoglia, dati i problemi dovuti alla tecnologia fortemente scalata.<br>The exponential trend of the complementary metal-oxide-semiconductor (CMOS) technologies predicted by Moores law has been successfully demonstrated over the last three decades. A constant downscaling of CMOS technologies with smaller and smaller device size has been developed, in order to comply with requirements on speed, complexity, circuit density and power consumption of advanced high performance digital applications. The minimum reachable length, which corresponds to the half the length of the channel of the smallest transistor that can be manufactured, represents every following technological node. With the arrival of nanoscale (sub-100nm) CMOS technologies, digital performance improve further, but many new challenges have been introduced for analog designers. In fact, for the digital circuits CMOS scaling-down leads to several benefits: speed improvement, reduced power consumption, high integration and complexity level. The analog circuits, instead, strongly suffers from the ScalTech trend, because the MOS behavior dramatically changes through the different technological nodes and especially for the ultra-scaled ones, where second order effects, previously negligible, become very important and start to be dominant, affecting its performance. For instance, lower intrinsic DC-gain, reduced dynamic range, operating point issues and larger parameter variability are some of the problems due to scaling-down. Analog designers must face this problems at different phases of the design, circuital and layout. Despite that, the design of analog circuit in sub-nm technologies is mandatory in some cases or can be even helpful in others. For example, in mainly mixed-signal systems, the read-out electronic requires high frequency performance, so the choice of deep submicron technology is mandatory, also for the analog part. Other types of applications where using scaled technology is even strategical are the high-energy physics experiments, where read-out circuits are exposed to very high radiation levels with consequent performance degradation and breakdown events. Since radiation damage is proportional to gate oxide volume, smaller devices exhibit lower radiation detriment. It has been demonstrated in fact, that 28nm CMOS technology devices are capable to sustain 1Grad-TID exposure, not possible with previous technologies. In this thesis, the main key challenges in ultra-scaled technologies are analyzed in the first chapter, and then integrated circuits designed in 28nm CMOS technology are presented. The first circuit design, presented in the second chapter and integrated in 28nm CMOS technology, is a Fast-Tracker front-end (FTfe) for charge detection. The read-out system has been developed starting from the main specifications and circuital solutions already adopted for muon detection in ATLAS experiment. The proposed front-end is able to detect an event and soon after to reset the system in order to make the FTfe already available for the following event, avoiding long dead times. The architecture is analyzed in detail, followed by the layout choices and the performance results. The second circuit design presented in the third chapter and always integrated in 28nm CMOS technology, is a Chopper instrumentation amplifier. Instrumentation amplifiers are the key building blocks in sensor and monitoring applications, where they are used to sense and amplify usually very small (sub-mV) and low frequency signals. For this reason it is important to reduce or eliminate the input offset and flicker noise, which cover and disturb the main signal to be detected. The proposed amplifier use a modulation technique, called chopper, in order to meet the low offset and low flicker noise requirements. Moreover it has been modeled to operate in sub-threshold region, in order to address the scaling problems. After the architecture description, layout and results of the integrated prototype are shown.
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Lorrain, Vincent. "Etude et conception de circuits innovants exploitant les caractéristiques des nouvelles technologies mémoires résistives." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLS182/document.

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Dans cette thèse, nous étudions les approches calculatoires dédiées des réseaux de neurones profonds et plus particulièrement des réseaux de neurones convolutionnels (CNN). En effet, l'efficacité des réseaux de neurones convolutionnels en font des structures calculatoires intéressantes dans de nombreuses applications. Nous étudions les différentes possibilités d'implémentation de ce type de réseaux pour en déduire leur complexité calculatoire. Nous montrons que la complexité calculatoire de ce type de structure peut rapidement devenir incompatible avec les ressources de l'embarqué. Pour résoudre cette problématique, nous avons fait une exploration des différents modèles de neurones et architectures susceptibles de minimiser les ressources nécessaires à l'application. Dans un premier temps, notre approche a consisté à explorer les possibles gains par changement de modèle de neurones. Nous montrons que les modèles dits impulsionnels permettent en théorie de réduire la complexité calculatoire tout en offrant des propriétés dynamiques intéressantes, mais nécessitent de repenser entièrement l'architecture matériel de calcul. Nous avons alors proposé notre approche impulsionnelle du calcul des réseaux de neurones convolutionnels avec une architecture associée. Nous avons mis en place une chaîne logicielle et de simulation matérielle dans le but d'explorer les différents paradigmes de calcul et implémentation matérielle et évaluer leur adéquation avec les environnements embarqués. Cette chaîne nous permet de valider les aspects calculatoires mais aussi d'évaluer la pertinence de nos choix architecturaux. Notre approche théorique a été validée par notre chaîne et notre architecture a fait l'objet d'une simulation en FDSOI 28 nm. Ainsi nous avons montré que cette approche est relativement efficace avec des propriétés intéressantes un terme de passage à l'échelle, de précision dynamique et de performance calculatoire. Au final, l'implémentation des réseaux de neurones convolutionnels en utilisant des modèles impulsionnels semble être prometteuse pour améliorer l'efficacité des réseaux. De plus, cela permet d'envisager des améliorations par l'ajout d'un apprentissage non supervisé type STDP, l'amélioration du codage impulsionnel ou encore l'intégration efficace de mémoire de type RRAM<br>In this thesis, we study the dedicated computational approaches of deep neural networks and more particularly the convolutional neural networks (CNN).We highlight the convolutional neural networks efficiency make them interesting choice for many applications. We study the different implementation possibilities of this type of networks in order to deduce their computational complexity. We show that the computational complexity of this type of structure can quickly become incompatible with embedded resources. To address this issue, we explored differents models of neurons and architectures that could minimize the resources required for the application. In a first step, our approach consisted in exploring the possible gains by changing the model of neurons. We show that the so-called spiking models theoretically reduce the computational complexity while offering interesting dynamic properties but require a complete rethinking of the hardware architecture. We then proposed our spiking approach to the computation of convolutional neural networks with an associated architecture. We have set up a software and hardware simulation chain in order to explore the different paradigms of computation and hardware implementation and evaluate their suitability with embedded environments. This chain allows us to validate the computational aspects but also to evaluate the relevance of our architectural choices. Our theoretical approach has been validated by our chain and our architecture has been simulated in 28 nm FDSOI. Thus we have shown that this approach is relatively efficient with interesting properties of scaling, dynamic precision and computational performance. In the end, the implementation of convolutional neural networks using spiking models seems to be promising for improving the networks efficiency. Moreover, it allows improvements by the addition of a non-supervised learning type STDP, the improvement of the spike coding or the efficient integration of RRAM memory
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Torres, Florent. "Power amplifier design for 5G applications in 28nm FD-SOI technology." Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0064/document.

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Le futur réseau mobile 5G est prévu pour être déployé à partir de 2020, dans un contexte d’évolution exponentielle du marché de la téléphonie mobile et du volume de données échangées. La 5G servira de levier à des applications révolutionnaires qui permettront l’émergence du monde connecté. Dans ce but, plusieurs spécifications pour le réseau sont attendues même si aucun standard n’est encore défini et notamment une faible latence, une consommation d’énergie réduite et un haut débit de données. Les bandes de fréquences traditionnellement utilisées dans les réseaux mobiles ne permettront pas d’atteindre les performances visées et plusieurs bandes de fréquences millimétriques sont à l’étude pour créer un spectre complémentaire. Cependant, ces bandes de fréquence millimétriques souffrent d’une forte atténuation dans l’air et dans les matériaux de construction. Plusieurs techniques vont être implémentées pour outrepasser ces limitations dans les zones urbaines denses comme le backhauling, FD-MIMO et beamforming phased array. Ces techniques entraînent l’utilisation d’un grand nombre de transmetteurs dans les stations de bases et dans les dispositifs de l’utilisateur final. La technologie CMOS offre d’indéniables avantages pour ce marché de masse tandis que la technologie FD-SOI offre des performances et fonctionnalités additionnelles. L’amplificateur de puissance est le bloc le plus critique à concevoir dans un transmetteur et consomme le plus d’énergie. Afin d’adresser les challenges de la 5G, plusieurs spécifications concernant la puissance consommée, la linéarité et le rendement sont attendues. Les variations de l’environnement dans les beamforming phased array et le contexte industriel nécessitent des topologies robustes alors qu’une reconfigurabilité au niveau de l’amplificateur de puissance est bénéfique dans le cas de circuits adaptatifs. Cette thèse adresse ces challenges en explorant la conception d’un amplificateur de puissance reconfigurable et robuste pour des applications 5G en intégrant des techniques de design spécifiques et en mettant en avant les avantages de la technologie 28nm FD-SOI pour la reconfigurabilité<br>The 5G future mobile network is planned to be deployed from 2020, in a context of exponential mobile market and exchanged data volume evolution. The 5G will leverage revolutionary applications for the advent of the connected world. For this purpose, several network specifications are expected notably low latency, reduced power consumption and high data-rates even if no standard is yet defined. The frequency bands traditionally used for mobile networks will not permit the needed performances and several mmW frequency bands are under study to create a complementary frequency spectrum. However, these mmW frequency bands suffer from large attenuation inbuilding material and in free-space. Therefore, several techniques will be implemented to tackle these limitations indense urban areas like backhauling, FD-MIMO and beamforming phased array. This is leading to a large number of transceivers for base stations and end-user devices. CMOS technology offers undeniable advantages for this mass market while FD-SOI technology offers additional features and performances. The power amplifier is the most critical block to design in a transceiver and is also the most power consuming. To address the 5G challenges, several specifications concerning power consumption, linearity and efficiency are expected. The environment variations inbeamforming phased array and the industrial context drive the need for robust topologies while power amplifier reconfigurability is benefic in a context of adaptive circuits. This thesis addresses these challenges by exploring the conception of a robust and reconfigurable power amplifier targeting 5G applications while integrating specific design techniques and taking advantage of 28nm FD-SOI CMOS technology features for reconfigurability purposes
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Arfaoui, Wafa. "Fiabilité Porteurs Chauds (HCI) des transistors FDSOI 28nm High-K grille métal." Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4335.

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Au sein de la course industrielle à la miniaturisation et avec l’augmentation des exigences technologiques visant à obtenir plus de performances sur moins de surface, la fiabilité des transistors MOSFET est devenue un sujet d’étude de plus en plus complexe. Afin de maintenir un rythme de miniaturisation continu, des nouvelles architectures de transistors MOS en été introduite, les technologies conventionnelles sont remplacées par des technologies innovantes qui permettent d'améliorer l'intégrité électrostatique telle que la technologie FDSOI avec des diélectriques à haute constante et grille métal. Malgré toutes les innovations apportées sur l’architecture du MOS, les mécanismes de dégradations demeurent de plus en plus prononcés. L’un des mécanismes le plus critique des technologies avancées est le mécanisme de dégradation par porteurs chauds (HCI). Pour garantir les performances requises tout en préservant la fiabilité des dispositifs, il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du transistor élémentaire. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradations HCI des transistors 28nm FDSOI. Basé sur l’énergie des porteurs, le modèle en tension proposé dans ce manuscrit permet de prédire la dégradation HC en tenant compte de la dépendance en polarisation de substrat incluant les effets de longueur, d’épaisseur de l’oxyde de grille ainsi que l’épaisseur du BOX et du film de silicium. Ce travail ouvre le champ à des perspectives d’implémentation du model HCI pour les simulateurs de circuits, ce qui représente une étape importante pour anticiper la fiabilité des futurs nœuds technologiques<br>As the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps
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Bayat, Shahin. "Experiments and simulations on negative/positive bias temperature instability in 28nm CMOS devices." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/55104.

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CMOS transistors come with a scaling potential, which brings along challenges such as process variation and NBTI/PBTI (Negative/Positive Bias Temperature Instability). My objectives during this project are to investigate effects of aging on CMOS devices as well as to show experimental results in order to model the effect of N/PBTI specifically targeting the 28nm technology node. The direct effect of transistor aging is a degradation of device threshold voltage, which can lead to performance degradation or malfunctions. Places such as server farms, data centers, and outer space-crafts, where device reliability for a long period is significant and accessibility is an issue, can benefit from an aging reversal process. In addition, as transistor channel lengths become smaller, they are more prone to a reduced lifetime. The exact causes of aging are not entirely known until this day and as a result, no real mechanism to reverse the process has been fully implemented on FPGAs or ASICs. I believe the true solution to these scalability challenges lay within the device structure and materials used in CMOS transistors, however, accelerated recovery at high temperatures can also help in reversing the effect of aging by a noticeable amount. I have been able to use this technique to reverse the effect of threshold voltage degradation in FPGAs. In this thesis, I present experimental results on the effect of degradation and recovery on a commercial FPGA. I then use the experimental results to calculate degradation parameters of transistor aging in this technology node and propose experimental setups for a 28nm ASIC.<br>Applied Science, Faculty of<br>Electrical and Computer Engineering, Department of<br>Graduate
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Fonseca, Alexandre. "Conception et réalisation de circuits de génération de fréquence en technologie FDSOI 28nm." Thesis, Nice, 2015. http://www.theses.fr/2015NICE4100/document.

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Le déploiement à grande échelle de l’internet des objets nécessite le développement de systèmes de radiocommunication plus économes en énergie, dont le circuit de génération de fréquences est connu pour être particulièrement énergivore. L’objectif de ce travail de thèse est donc d’une part de développer une synthèse de fréquences très faible consommation et d’autre part de démontrer les performances de la technologie FDSOI pour des applications analogiques et radiofréquences. Dans le premier chapitre sont présentées les spécifications du standard choisi -le BLE-, les spécificités de la technologie FDSOI et l'état de l’art des architectures de transmetteurs radiofréquences à faible consommation. Nous avons retenue de cette comparaison l'architecture à division par phases. Le deuxième chapitre présente les résultats de trois types de modélisation système de l’architecture ; 1 - le fonctionnement de ses composants et les points clés à respecter pour son implémentation, 2 - le comportement en bruit de phase pour la définition des spécifications, et 3 - l’impact de l’architecture sur la génération de raies spectrales parasites. Cette étude nous a permis de fixer le cahier des charges du VCRO développé au chapitre suivant. Le troisième chapitre est consacré à la conception, la réalisation et le test de 4 topologies de VCROs en technologie FDSOI 28nm et d'un circuit de test. Les premiers résultats de mesure sont encourageants mais nécessitent d’être complétés par des mesures avec PLL fractionnaire intégrée. En effet, la sensibilité des circuits à la tension d’alimentation (pushing de l’ordre de 5 GHz/V) a rendu les mesures du bruit de phase très délicates<br>The large-scale deployment of IoT requires the development of more efficient energy radio systems, within which the frequency generation circuit is known to be particularly energy-consuming. The objective of this thesis is firstly to develop a very low consumption frequency synthesis and secondly to demonstrate the performance of the FDSOI technology for analog and RF applications.In the first chapter are the specifications of the chosen standard -the BLE-, the specifications of the FDSOI technology and state of the art of low power radio frequency synthesizers architecture. We have chosen from this comparison the Fractional Phase Divider architecture. The second chapter presents the results of three types of system simulations of the PLL; 1 - the operation of its components and the key points to be respected for its implementation, 2 - the phase noise behavior for the definition of specifications, and 3 - the impact of architecture on the generation of spurious. This study allowed us to set the specifications of VCROs developed in the next chapter. The third chapter is dedicated to the design, implementation and testing of four topologies of VCROs and a test circuit in FDSOI 28nm technology. The first measurement results are encouraging but they need to be complemented by an integrated fractional PLL measurement. Indeed, the sensitivity of the circuits to the supply voltage (pushing of about 5 GHz/V) made measurements of phase noise very delicate. The measured consumption is less than 0.8 mA and the surface of the circuits is of the order of 600 µm².In the fourth and final chapter we present the implementation at circuit-level of a phase synchronization PLL
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Souvignet, Thomas. "Contribution to the design of switched-capacitor voltage regulators in 28nm FDSOI CMOS." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0043/document.

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Les appareils multimédias portables nécessitent toujours plus d'innovation pour satisfaire les besoins des utilisateurs. Les fabricants de système-sur-puces font donc face à une forte demande en capacité de calcul jusqu'à lors réservée aux ordinateurs de bureau. Ce transfert de performance se répercute inévitablement sur la consommation de ces appareils alors que dans le même temps la capacité des batteries n'est pas en mesure de répondre à cet accroissement. De nombreux compléments matériels et logiciels sont mis en places afin d'économiser l'énergie au maximum sans toutefois dégrader les performances. La modulation de la fréquence de fonctionnement et de la tension d'alimentation est certainement la plus efficace mais reste néanmoins limitée par les coûts et les contraintes d'encombrement exigées par la taille des appareils. La réponse à un tel problème passe nécessairement par l'intégration d'une partie de l'alimentation dans la puce. La conversion DC-DC basée sur des convertisseurs à capacités commutées est prometteuse car elle permet de garder un maximum de compatibilité avec les process CMOS actuels. Cette thèse explore donc la conception d'une architecture d'alimentation utilisant des convertisseurs à capacités commutées. Un étage de puissance avec une tension d'entrée est de 1.8 V et des ratios programmables permet d'obtenir le rendement maximum pour une plage de tension de sortie allant de 0.3 à 1.2 V. La tension de sortie peut varier en fonction du point de fonctionnement requit par le système. Afin d'assurer le maximum de compatibilité avec la conception du circuit numérique à alimenter, une architecture modulaire basée sur les capacités MIM est privilégiée. Les capacités sont placées au dessus de la fonction numériques et les interrupteurs de puissance sont insérés à sa périphérie. Cette architecture permet également d'entrelacer les cellules de conversion afin de réduire l'ondulation de la tension de sortie. La fréquence de commutation du convertisseurs est communément utilisée pour réguler la tension de sortie et des stratégies de contrôles linéaires et non linéaires sont donc explorées. Un prototype de convertisseur présentant une densité de puissance de 310mW/mm2 pour un rendement de 72.5% a été fabriqué dans la technologie 28nm FDSOI de STMicroelectronics. La surface requise pour le convertisseur nécessite que 11.5% de la surface du circuit à alimenter. La méthodologie de conception du convertisseur a finalement été appliquée à un régulateur de tension dans le domaine négatif pour des applications de polarisation de caisson à basse consommation<br>Mobile and multimedia devices offer more innovations and enhancements to satisfy user requirements. Chip manufacturers thus propose high performances SoC to address these needs. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise as fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switched-capacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the manufacturing process of digital SoCs. This thesis focuses on the design of an embedded power supply architecture using switched-capacitor DC-DC converters.Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3-1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply and the power switches are located as an external ring. Such an architecture offers high flexibility. Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable and linear regulation and hysteretic control are analyzed. A prototype has been fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW/mm2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to the design of a negative SC converter for body-biasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application
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Sivadasan, Ajith. "Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT118.

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La mise à l'échelle de la technologie CMOS classique augmente les performances des circuits numériques grâce à la possibilité d'incorporation de composants de circuit supplémentaires dans la même zone de silicium. La technologie FDSOI 28nm de ST Microélectroniques est une stratégie d'échelle innovante qui maintient une structure de transistor planaire et donc une meilleure performance sans augmentation des coûts de fabrication de puces pour les applications basse tension. Il est important de s'assurer que l'augmentation des fonctionnalités et des performances ne se fasse pas au détriment de la fiabilité réduite, ce qui est assuré en répondant aux exigences des normes internationales ISO26262 pour les applications critiques dans les environnements automobile et industriel. Les entreprises de semi-conducteurs, pour se conformer à ces normes, doivent donc présenter des capacités d'estimation de la fiabilité au stade de la conception du circuit, qui est pour l'instant évaluer qu'après la fabrication d'un circuit numérique. Ce travail se concentre sur le vieillissement des standard cell et des circuits numériques avec le temps sous l'influence du mécanisme de dégradation du NBTI pour une large gamme de variations de processus, de tension et de température (PVT) et la compensation de vieillissement avec l'application de la tension à la face arrière (Body-Bias). L'un des principaux objectifs de cette thèse est la mise en place d'une infrastructure d'analyse de fiabilité composée d'outils logiciels et d'un modèle de vieillissement dans un cadre industriel d'estimation du taux de défaillance des circuits numériques au stade de la conception des circuits développés en technologie ST 28nm FDSOI<br>Scaling of classical CMOS technology provides an increase in performance of digital circuits owing to the possibility of incorporation of additional circuit components within the same silicon area. 28nm FDSOI technology from ST Microelectronics is an innovative scaling strategy maintaining a planar transistor structure and thus provide better performance with no increase in silicon chip fabrication costs for low power applications. It is important to ensure that the increased functionality and performance is not at the expense of decreased reliability, which can be ensured by meeting the requirements of international standards like ISO26262 for critical applications in the automotive and industrial settings. Semiconductor companies, to conform to these standards, are thus required to exhibit the capabilities for reliability estimation at the design conception stage most of which, currently, is done only after a digital circuit has been taped out. This work concentrates on Aging of standard cells and digital circuits with time under the influence of NBTI degradation mechanism for a wide range of Process, Voltage and Temperature (PVT) variations and aging compensation using backbiasing. One of the principal aims of this thesis is the establishment of a reliability analysis infrastructure consisting of software tools and gate level aging model in an industrial framework for failure rate estimation of digital circuits at the design conception stage for circuits developed using ST 28nm FDSOI technology
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Rahhal, Lama. "Analyse et modélisation des phénomènes de mismatch des transistors MOSFET avancées." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT061/document.

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Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés<br>For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed
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Books on the topic "28nm"

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Batalov, Vyacheslav. Loyal Alliance. Musketeers & Reiters: 28mm Paper Soldiers. Independently Published, 2019.

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Alexandrovich, Batalov, and Batalov Nicolaevich. Rebels. Highlanders 1680-1730: 28mm Paper Soldiers. Independently Published, 2019.

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Alexandrovich, Batalov, and Batalov Nicolaevich. Rebels. Pirates 1680-1730: 28mm Paper Soldiers. Independently Published, 2019.

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Alexandrovich, Batalov, and Batalov Nicolaevich. Golden Roses. Cavalry 1680-1730: 28mm Paper Soldiers. Independently Published, 2019.

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Batalov, Vyacheslav. Loyal Alliance. Cavalry 1600-1650: 28mm Paper Soldiers. Independently Published, 2019.

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Batalov, Vyacheslav. Loyal Alliance. Royalists 1640-1660: 28mm Paper Soldiers. Independently Published, 2019.

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Batalov, Vyacheslav. Protest League. Cavalry 1600-1650: 28mm Paper Soldiers. Independently Published, 2019.

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Alexandrovich, Batalov, and Batalov Nicolaevich. Flaming Spear. Seratkulu 1680-1730: 28mm Paper Soldiers. Independently Published, 2019.

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Batalov, Vyacheslav. Protest League. Ironsides 1640-1660: 28mm Paper Soldiers. Independently Published, 2019.

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Alexandrovich, Batalov, and Batalov Nicolaevich. Flaming Spear. Kapykulu 1680-1730: 28mm Paper Soldiers. Independently Published, 2019.

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Book chapters on the topic "28nm"

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Nemoianu, Virgil. "2. Romantic Irony and Biedermeier Tragicomedy." In Comparative History of Literatures in European Languages. John Benjamins Publishing Company, 1993. http://dx.doi.org/10.1075/chlel.ix.28nem.

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Metcalfe, N., T. Shanks, N. Roche, and R. Fong. "Galaxy Number-Counts to B = 28m." In Astronomy from Wide-Field Imaging. Springer Netherlands, 1994. http://dx.doi.org/10.1007/978-94-011-1146-1_137.

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Yoshikawa, Takamasa, Tadashi Inaba, Kenta Ida, and Shinya Mizutani. "Experimental Study of Critical Stresses of Fe-28Mn-6Si-5Cr SMA Under Various Temperature Conditions." In Advances in Shape Memory Materials. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53306-3_17.

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Meloni, Chantal. "Modes of Responsibility (Article 28N), Individual Criminal Responsibility (Article 46B) and Corporate Criminal Liability (Article 46C)." In International Criminal Justice Series. T.M.C. Asser Press, 2016. http://dx.doi.org/10.1007/978-94-6265-150-0_9.

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Ambos, Kai. "Genocide (Article 28B), Crimes Against Humanity (Article 28C), War Crimes (Article 28D) and the Crime of Aggression (Article 28M)." In International Criminal Justice Series. T.M.C. Asser Press, 2016. http://dx.doi.org/10.1007/978-94-6265-150-0_3.

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Morgenstern, Frank, and Stephan Huck. "Der Passionspunkt »Erinnern und Mahnen über die Grenzen hinweg« gefeiert auf dem Vorplatz des Marinemuseums in Wilhelmshaven in der Karwoche 2016 zum Thema: 28cm." In Ausgezeichnete Gottesdienste. Vandenhoeck & Ruprecht, 2017. http://dx.doi.org/10.13109/9783788732110.143.

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Smirnov, O. M., M. M. Voron, A. Tymoshenko, A. Semenko, Yu Skorobagatko, and S. L. Schwab. "Effect of heat treatment on the structure of the Fe-28Mn-12Al-0.9Si-1.35C alloy, additionally doped by Ni 3.3, Cr 1, V 0.15 (wt. %)." In Welding and Related Technologies. CRC Press, 2025. https://doi.org/10.1201/9781003518518-35.

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Fatima, Afroz, and Abhijit Pethe. "An RRAM-Based Neuromorphic Accelerator for Speech-Based Emotion Recognition." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-6596-7.ch003.

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A neuromorphic accelerator for a deep net having RRAM based processing elements has been implemented for emotion detection based on dialect. The proposed accelerator has been trained on the RAVDESS dataset in order to classify different emotion types. The RRAM based swish activation function has been employed to build the neuromorphic accelerator as it consumes less power (476μW), has lower operating voltage (1.23V), and has better performance and output characteristics. The proposed neuromorphic accelerator has been implemented using 1T-1RRAM Processing Elements on ST Microelectronics 28nm FD-SOI, also on Intel i3-8130U CPU and compared with NVIDIA GeForce GPU to highlight the advantages. The proposed accelerator achieves high-performance and consumes less power (1780μW) with on/off rate (13.81) and lower operating voltage (2V). The training accuracy for the FD-SOI implementation is 79.13% and has a learning rate of 0.01 and weight update interval of 1 epoch. This chapter also highlights the importance of the proposed neuromorphic accelerator from Industry 4.0 perspective.
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XU, PANPAN, LAN PENG, JIAN LIU, WENWEN YIN, and SHUAI ZHOU. "Nickel (28Ni)." In Handbook of Synthetic Methodologies and Protocols of Nanomaterials. World Scientific, 2019. http://dx.doi.org/10.1142/9789813277809_0019.

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Venkatachalam, Gnanalakshmi, M. Heman, and S. Sumesh. "Circular Fractal Array Antenna for C and S-Band Applications." In Advances in Wireless Technologies and Telecommunication. IGI Global, 2025. https://doi.org/10.4018/979-8-3693-8799-3.ch010.

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In this article, a circular fractal array antenna is proposed for C-band and S-band applications. The antenna uses circular fractal geometry to achieve high gain across the S and C bands frequency spectrum. The antenna is fabricated using an FR-4 substrate and tested in anechoic chamber. The antenna design holds potential for multi-functional wireless systems and S and C band applications. The measurement results reveal that the designed antenna has two resonant frequencies at 3.5 GHz and 5.8 GHz and gain of around 3.1dB is noted. The size of proposed antenna is 28mm×28mm×1.6mm.
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Conference papers on the topic "28nm"

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Gupta, Mihir, Lander Verstraete, Joern-Holger Franke, et al. "EUV dose reduction for pitch 28nm line-space." In International Conference on Extreme Ultraviolet Lithography 2024, edited by Joern-Holger Franke, Kurt G. Ronse, Paolo A. Gargini, Patrick P. Naulleau, and Toshiro Itani. SPIE, 2024. http://dx.doi.org/10.1117/12.3034646.

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Crafton, Brian, Samuel D. Spetalnick, Muya Chang, and Arijit Raychowdhury. "A 28nm Approximate / Binary 6T CAM for Sequence Alignment." In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631341.

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Liu, Mingjie, Zhujuan Wan, Biao Deng, Changwei Wang, Fan Yu, and Liguo Sun. "A 2.4GHz Integer-N Frequency Synthesizer in 28nm CMOS." In 2024 International Conference on Microwave and Millimeter Wave Technology (ICMMT). IEEE, 2024. http://dx.doi.org/10.1109/icmmt61774.2024.10672154.

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Taylor, Brad, and Ralph Wittig. "28nm generation programmable families." In 2010 IEEE Hot Chips 22 Symposium (HCS). IEEE, 2010. http://dx.doi.org/10.1109/hotchips.2010.7480077.

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Parpillon, Benjamin, Anthony Badea, Chinar Syal, et al. "Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm." In Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm. US DOE, 2024. http://dx.doi.org/10.2172/2477314.

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Parrassin, Thierry, Guillaume Celi, Sylvain Dudit, et al. "Laser Voltage Imaging and Its Derivatives—Efficient Techniques to Address Defect on 28 nm Technology." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0306.

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Abstract The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.
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Ning, Liew Chiun, Lau Kok Heng, Ng Yi Jie, Goh Lay Lay, Lee Chong Haw, and Loo Huey Wen. "FBGA 28nm Scan Chain Failure Analysis." In 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2018. http://dx.doi.org/10.1109/ipfa.2018.8452562.

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Kheirallah, Rida, Nadine Azemard, and Gilles Ducharme. "Energy study for 28nm FDSOI technology." In 2015 International Workshop on CMOS Variability (VARI). IEEE, 2015. http://dx.doi.org/10.1109/vari.2015.7456558.

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Sahashchik, Ulyana, and Evgeniya Sokolova. "DEVELOPMENT OF A TOOL FOR GENERATING A SET OF CLIPS FOR CONDUCTING SMO." In International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1656.silicon-2020/380-382.

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Celi, Guillaume, Sylvain Dudit, Thierry Parrassin, et al. "Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology." In ISTFA 2012. ASM International, 2012. http://dx.doi.org/10.31399/asm.cp.istfa2012p0176.

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Abstract The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.
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Reports on the topic "28nm"

1

Sologub, Dmitry, Emil Babaev, and Batdal Batdalov. MI-28N OPTICAL DETECTION AND GUIDANCE SYSTEMS. Science and Innovation Center Publishing House, 2020. http://dx.doi.org/10.12731/detection_and_guidance_systems.

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Книга предназначена для студентов (курсантов), а также технического персонала обслуживающего данное оборудование для ознакомления и подготовки к эксплуатации оптических систем вертолета МИ-28Н, а также его анализа с подобными ему иностранными техниками.
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