Journal articles on the topic '22~nm'
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Bloomstein, T. M., Michael F. Marchant, Sandra Deneault, Dennis E. Hardy, and Mordechai Rothschild. "22-nm immersion interference lithography." Optics Express 14, no. 14 (2006): 6434. http://dx.doi.org/10.1364/oe.14.006434.
Full textSadana, Devendra, Stephen W. Bedell, J. P. De Souza, Y. Sun, E. Kiewra, A. Reznicek, T. Adams, et al. "CMOS Scaling Beyond 22 nm Node." ECS Transactions 19, no. 5 (December 18, 2019): 267–74. http://dx.doi.org/10.1149/1.3119551.
Full textBuengener, Ralf, Carol Boye, Bryan N. Rhoads, Sang Y. Chong, Charu Tejwani, Sean D. Burns, Andrew D. Stamper, et al. "Process Window Centering for 22 nm Lithography." IEEE Transactions on Semiconductor Manufacturing 24, no. 2 (May 2011): 165–72. http://dx.doi.org/10.1109/tsm.2011.2106807.
Full textParker, Matthew. "A sub-terahertz transceiver in 22 nm FinFET." Nature Electronics 5, no. 3 (March 2022): 126. http://dx.doi.org/10.1038/s41928-022-00741-x.
Full textKurd, Nasser, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, et al. "Haswell: A Family of IA 22 nm Processors." IEEE Journal of Solid-State Circuits 50, no. 1 (January 2015): 49–58. http://dx.doi.org/10.1109/jssc.2014.2368126.
Full textHuang, Ru, HanMing Wu, JinFeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, et al. "Challenges of 22 nm and beyond CMOS technology." Science in China Series F: Information Sciences 52, no. 9 (September 2009): 1491–533. http://dx.doi.org/10.1007/s11432-009-0167-9.
Full textShiotani, Hideaki, Shota Suzuki, Dong Gun Lee, Patrick Naulleau, Yasuyuki Fukushima, Ryuji Ohnishi, Takeo Watanabe, and Hiroo Kinoshita. "Dual Grating Interferometric Lithography for 22-nm Node." Japanese Journal of Applied Physics 47, no. 6 (June 20, 2008): 4881–85. http://dx.doi.org/10.1143/jjap.47.4881.
Full textSeifert, N., B. Gill, S. Jahinuzzaman, J. Basile, V. Ambrose, Quan Shi, R. Allmon, and A. Bramnik. "Soft Error Susceptibilities of 22 nm Tri-Gate Devices." IEEE Transactions on Nuclear Science 59, no. 6 (December 2012): 2666–73. http://dx.doi.org/10.1109/tns.2012.2218128.
Full textZhang, Bo, Min Zhang, and Tianhong Cui. "Low-cost shrink lithography with sub-22 nm resolution." Applied Physics Letters 100, no. 13 (March 26, 2012): 133113. http://dx.doi.org/10.1063/1.3697836.
Full textLi, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.
Full textSeaberg, Matthew D., Daniel E. Adams, Ethan L. Townsend, Daisy A. Raymondson, William F. Schlotter, Yanwei Liu, Carmen S. Menoni, et al. "Ultrahigh 22 nm resolution coherent diffractive imaging using a desktop 13 nm high harmonic source." Optics Express 19, no. 23 (October 25, 2011): 22470. http://dx.doi.org/10.1364/oe.19.022470.
Full textJeong-Dong Choe, Chang-Sub Lee, Sung-Ho Kim, Sung-Min Kim, Shin-Ae Lee, Ju-Won Lee, Y. G. Shin, Donggun Park, and Kinam Kim. "A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation." IEEE Electron Device Letters 24, no. 3 (March 2003): 195–97. http://dx.doi.org/10.1109/led.2003.811401.
Full textBrewer, Rachel M., En Xia Zhang, Mariia Gorchichko, Peng Fei Wang, Jonathan Cox, Steven L. Moran, Dennis R. Ball, et al. "Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors." IEEE Transactions on Nuclear Science 68, no. 5 (May 2021): 677–86. http://dx.doi.org/10.1109/tns.2021.3059594.
Full textGao, Ping, Na Yao, Changtao Wang, Zeyu Zhao, Yunfei Luo, Yanqin Wang, Guohan Gao, Kaipeng Liu, Chengwei Zhao, and Xiangang Luo. "Enhancing aspect profile of half-pitch 32 nm and 22 nm lithography with plasmonic cavity lens." Applied Physics Letters 106, no. 9 (March 2, 2015): 093110. http://dx.doi.org/10.1063/1.4914000.
Full textCao Zhen, 曹振, 李艳秋 Li Yanqiu, and 刘菲 Liu Fei. "Manufacturable Design of 16~22 nm Extreme Ultraviolet Lithographic Objective." Acta Optica Sinica 33, no. 9 (2013): 0922005. http://dx.doi.org/10.3788/aos201333.0922005.
Full textChakraborty, Wriddhi, Khandker Akif Aabrar, Jorge Gomez, Rakshith Saligram, Arijit Raychowdhury, Patrick Fay, and Suman Datta. "Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS." IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7, no. 2 (December 2021): 184–92. http://dx.doi.org/10.1109/jxcdc.2021.3131144.
Full textChung, Shine C., Wen-Kuang Fang, and Fang-Hua Chen. "A 4Kx8 Innovative Fuse OTP on 22-nm FD-SOI." IEEE Journal of the Electron Devices Society 7 (2019): 837–45. http://dx.doi.org/10.1109/jeds.2019.2922711.
Full textXiaobin Wang, Yiran Chen, Hai Li, D. Dimitrov, and H. Liu. "Spin Torque Random Access Memory Down to 22 nm Technology." IEEE Transactions on Magnetics 44, no. 11 (November 2008): 2479–82. http://dx.doi.org/10.1109/tmag.2008.2002386.
Full textRusu, Stefan, Harry Muljono, David Ayers, Simon Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, and Eddie Wang. "A 22 nm 15-Core Enterprise Xeon® Processor Family." IEEE Journal of Solid-State Circuits 50, no. 1 (January 2015): 35–48. http://dx.doi.org/10.1109/jssc.2014.2368933.
Full textFukushima, Yasuyuki, Yuya Yamaguchi, Takafumi Iguchi, Takuro Urayama, Tetsuo Harada, Takeo Watanabe, and Hiroo Kinoshita. "Development of interference lithography for 22 nm node and below." Microelectronic Engineering 88, no. 8 (August 2011): 1944–47. http://dx.doi.org/10.1016/j.mee.2011.02.076.
Full textXie, Peng, and Bruce W. Smith. "Scanning interference evanescent wave lithography for sub-22-nm generations." Journal of Micro/Nanolithography, MEMS, and MOEMS 12, no. 1 (February 11, 2013): 013011. http://dx.doi.org/10.1117/1.jmm.12.1.013011.
Full textNaulleau, Patrick P., Christopher N. Anderson, Lorie-Mae Baclea-an, Paul Denham, Simi George, Kenneth A. Goldberg, Michael Goldstein, et al. "Pushing extreme ultraviolet lithography development beyond 22 nm half pitch." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 27, no. 6 (2009): 2911. http://dx.doi.org/10.1116/1.3237092.
Full textMohsen, Ali, Adnan Harb, Nathalie Deltimple, and Abraham Serhane. "28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I." Circuits and Systems 08, no. 04 (2017): 93–110. http://dx.doi.org/10.4236/cs.2017.84006.
Full textMohsen, Ali, Adnan Harb, Nathalie Deltimple, and Abraham Serhane. "28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II." Circuits and Systems 08, no. 05 (2017): 111–21. http://dx.doi.org/10.4236/cs.2017.85007.
Full textJeevan, B., and K. Sivani. "Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers." Microelectronics Journal 113 (July 2021): 105059. http://dx.doi.org/10.1016/j.mejo.2021.105059.
Full textFreeman, G., P. Chang, E. R. Engbrecht, K. J. Giewont, D. F. Hilscher, M. Lagus, T. J. McArdle, et al. "Performance-optimized gate-first 22-nm SOI technology with embedded DRAM." IBM Journal of Research and Development 59, no. 1 (January 2015): 5:1–5:14. http://dx.doi.org/10.1147/jrd.2014.2380252.
Full textXu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang, and Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (December 15, 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.
Full textSchmidt, Matthias, Martin J. Suess, Angelica D. Barros, Richard Geiger, Hans Sigg, Ralph Spolenak, and Renato A. Minamisawa. "A Patterning-Based Strain Engineering for Sub-22 nm Node FinFETs." IEEE Electron Device Letters 35, no. 3 (March 2014): 300–302. http://dx.doi.org/10.1109/led.2014.2300865.
Full textSze-Ann Wu, Yi-Lung Cheng, Chia-Yang Wu, and Wen-Hsi Lee. "A Study of Cu/CuMn Barrier for 22-nm Semiconductor Manufacturing." IEEE Transactions on Device and Materials Reliability 14, no. 1 (March 2014): 286–90. http://dx.doi.org/10.1109/tdmr.2013.2262525.
Full textHolmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (January 1, 2010): 013001. http://dx.doi.org/10.1117/1.3302125.
Full textPark, Joon-Min, Dai-Gyoung Kim, Joo-Yoo Hong, Ilsin An, and Hye-Keun Oh. "Anisotropic Resist Reflow Process Simulation for 22 nm Elongated Contact Holes." Japanese Journal of Applied Physics 47, no. 6 (June 20, 2008): 4940–43. http://dx.doi.org/10.1143/jjap.47.4940.
Full textKozawa, Takahiro, Seiichi Tagawa, Julius Joseph Santillan, and Toshiro Itani. "Quencher Effects at 22 nm Pattern Formation in Chemically Amplified Resists." Japanese Journal of Applied Physics 47, no. 7 (July 11, 2008): 5404–8. http://dx.doi.org/10.1143/jjap.47.5404.
Full textBrown, J., and Z. Zuo. "Renal receptors for atrial and C-type natriuretic peptides in the rat." American Journal of Physiology-Renal Physiology 263, no. 1 (July 1, 1992): F89—F96. http://dx.doi.org/10.1152/ajprenal.1992.263.1.f89.
Full textMayeda, Jill, Donald Y. C. Lie, and Jerry Lopez. "Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT." Electronics 11, no. 5 (February 23, 2022): 683. http://dx.doi.org/10.3390/electronics11050683.
Full textWurm, Stefan. "EUV Lithography Development and Research Challenges for the 22 nm Half-pitch." Journal of Photopolymer Science and Technology 22, no. 1 (2009): 31–42. http://dx.doi.org/10.2494/photopolymer.22.31.
Full textDas, S., R. Yu, K. Cherkaoui, P. Razavi, and S. Barraud. "Performance of 22 nm Tri-Gate Junctionless Nanowire Transistors at Elevated Temperatures." ECS Solid State Letters 2, no. 8 (May 23, 2013): Q62—Q65. http://dx.doi.org/10.1149/2.004308ssl.
Full textBenk, Markus P., Kenneth A. Goldberg, Antoine Wojdyla, Christopher N. Anderson, Farhad Salmassi, Patrick P. Naulleau, and Michael Kocsis. "Demonstration of 22-nm half pitch resolution on the SHARP EUV microscope." Journal of Vacuum Science & Technology B 33, no. 6 (November 2015): 06FE01. http://dx.doi.org/10.1116/1.4929509.
Full textBaklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (December 16, 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.
Full textSeo, Soon-Cheon, Chih-Chao Yang, Miaomiao Wang, Frederic Monsieur, Lahir Adam, Jeffrey B. Johnson, Dave Horak, et al. "Copper Contact for 22 nm and Beyond: Device Performance and Reliability Evaluation." IEEE Electron Device Letters 31, no. 12 (December 2010): 1452–54. http://dx.doi.org/10.1109/led.2010.2078483.
Full textYan, H., A. J. Bergren, R. McCreery, M. L. Della Rocca, P. Martin, P. Lafarge, and J. C. Lacroix. "Activationless charge transport across 4.5 to 22 nm in molecular electronic junctions." Proceedings of the National Academy of Sciences 110, no. 14 (March 18, 2013): 5326–30. http://dx.doi.org/10.1073/pnas.1221643110.
Full textYounkin, Todd R. "Extreme-ultraviolet secondary electron blur at the 22-nm half pitch node." Journal of Micro/Nanolithography, MEMS, and MOEMS 10, no. 3 (July 1, 2011): 033004. http://dx.doi.org/10.1117/1.3607429.
Full textWu, Banqiu. "Next-generation lithography for 22 and 16 nm technology nodes and beyond." Science China Information Sciences 54, no. 5 (May 2011): 959–79. http://dx.doi.org/10.1007/s11432-011-4227-6.
Full textKozawa, Takahiro, Seiichi Tagawa, Julius Joseph Santillan, Minoru Toriumi, and Toshiro Itani. "Feasibility Study of Chemically Amplified Extreme Ultraviolet Resists for 22 nm Fabrication." Japanese Journal of Applied Physics 47, no. 6 (June 13, 2008): 4465–68. http://dx.doi.org/10.1143/jjap.47.4465.
Full textKim, Eugene, Andrea Steinbrück, Maria Teresa Buscaglia, Vincenzo Buscaglia, Thomas Pertsch, and Rachel Grange. "Second-Harmonic Generation of Single BaTiO3 Nanoparticles down to 22 nm Diameter." ACS Nano 7, no. 6 (May 24, 2013): 5343–49. http://dx.doi.org/10.1021/nn401198g.
Full textTawarayama, Kazuo, Hajime Aoyama, Kentaro Matsunaga, Shunko Magoshi, Yukiyasu Arisawa, and Taiga Uno. "Resolution Enhancement for Beyond-22-nm Node Using Extreme Ultraviolet Exposure Tool." Japanese Journal of Applied Physics 49, no. 6 (June 21, 2010): 06GD01. http://dx.doi.org/10.1143/jjap.49.06gd01.
Full textAcri, G., F. Podevin, E. Pistono, L. Boccia, N. Corrao, T. Lim, E. N. Isa, and P. Ferrari. "A Millimeter-Wave Miniature Branch-Line Coupler in 22-nm CMOS Technology." IEEE Solid-State Circuits Letters 2, no. 6 (June 2019): 45–48. http://dx.doi.org/10.1109/lssc.2019.2930197.
Full textHuang, Mingjing, and Xiaoyong He. "A Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 22-nm CMOS." Journal of Physics: Conference Series 2613, no. 1 (October 1, 2023): 012024. http://dx.doi.org/10.1088/1742-6596/2613/1/012024.
Full textHaarig, Moritz, Albert Ansmann, Holger Baars, Cristofer Jimenez, Igor Veselovskii, Ronny Engelmann, and Dietrich Althausen. "Depolarization and lidar ratios at 355, 532, and 1064 nm and microphysical properties of aged tropospheric and stratospheric Canadian wildfire smoke." Atmospheric Chemistry and Physics 18, no. 16 (August 20, 2018): 11847–61. http://dx.doi.org/10.5194/acp-18-11847-2018.
Full textIbe, Eishi, Hitoshi Taniguchi, Yasuo Yahagi, Ken-ichi Shimbo, and Tadanobu Toba. "Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule." IEEE Transactions on Electron Devices 57, no. 7 (July 2010): 1527–38. http://dx.doi.org/10.1109/ted.2010.2047907.
Full textEitan, Ro'ee, and Ariel Cohen. "Untrimmed Low-Power Thermal Sensor for SoC in 22 nm Digital Fabrication Technology." Journal of Low Power Electronics and Applications 4, no. 4 (December 9, 2014): 304–16. http://dx.doi.org/10.3390/jlpea4040304.
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