Journal articles: '22-nm technology node'

1

Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.

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Xu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang, and Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (December 15, 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.

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Holmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (January 1, 2010): 013001. http://dx.doi.org/10.1117/1.3302125.

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Baklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (December 16, 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.

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Saxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (April 24, 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new materials and devices hold promise as potential device candidates to be integrated onto the silicon platform to enhance semiconductor industry growth and extend Moore's Law. Here we address state–of–the–art research trends in nanomaterials and nanodevices for future technology node and discuss associated challenges.

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Huang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan, and Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology." Microelectronics Reliability 147 (August 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.

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Li, Zongru, Christopher Elash, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Jiesi Xing, Shuting Shi, Zhi Wu Yang, and Bharat L. Bhuva. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node." Microelectronics Reliability 146 (July 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.

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Lu, Peng, Can Yang, Yifei Li, Bo Li, and Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs." Eng 2, no. 4 (December 3, 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.

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The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

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Changhwan Shin, Min Hee Cho, Yasumasa Tsukamoto, Bich-Yen Nguyen, Carlos Mazuré, Borivoje Nikolić, and Tsu-Jae King Liu. "Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node." IEEE Transactions on Electron Devices 57, no. 6 (June 2010): 1301–9. http://dx.doi.org/10.1109/ted.2010.2046070.

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Shin, Changhwan, Nattapol Damrongplasit, Xin Sun, Yasumasa Tsukamoto, Borivoje Nikolic, and Tsu-Jae King Liu. "Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node." IEEE Transactions on Electron Devices 58, no. 7 (July 2011): 1846–54. http://dx.doi.org/10.1109/ted.2011.2139213.

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Mah, Siew Kien, Pin Jern Ker, Ibrahim Ahmad, Noor Faizah Zainul Abidin, and Mansur Mohammed Ali Gamel. "A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length." Materials 14, no. 19 (September 30, 2021): 5721. http://dx.doi.org/10.3390/ma14195721.

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

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Duari, Chusen, Shilpi Birla, and Amit Kumar Singh. "A Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability." Journal of Integrated Circuits and Systems 15, no. 2 (July 31, 2020): 1–7. http://dx.doi.org/10.29292/jics.v15i2.140.

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Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.

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Mazurier, J., O. Weber, F. Andrieu, A. Toffoli, O. Thomas, F. Allain, J. P. Noel, M. Belleville, O. Faynot, and T. Poiroux. "Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below." Journal of Low Power Electronics 8, no. 1 (February 1, 2012): 125–32. http://dx.doi.org/10.1166/jolpe.2012.1173.

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Karthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.

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Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

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Valasa, Sresta, Shubham Tayal, and Laxman Raju Thoutam. "Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node." ECS Journal of Solid State Science and Technology 11, no. 4 (April 1, 2022): 041008. http://dx.doi.org/10.1149/2162-8777/ac6627.

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This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (Lg) along with high-k gate dielectrics. A comprehensive analysis of analog/RF performances like Transconductance (gm), Gate capacitance (Cgg), Gate to drain capacitance (Cgd), Output conductance (gds), Intrinsic gain (Av), Maximum oscillation frequency (fMAX), Gain Frequency Product (GFP), Cutoff frequency (fT) is carried out for the temperature range 77 K to 400 K. It is noticed that with the decrease in temperature from 400 K to 77 K, there is an improvement in AV, GFP, fT, and fMAX by an amount of ∼7.43%, ∼78.4%, ∼78.38%, ∼50.9% respectively. It is also found AV gets degraded with the downscaling of Lg from 16 nm to 8 nm. However, the same resulted in the improvement of RF performance. From detailed analysis, it is further observed that the usage of high-k gate dielectrics (k = 22) in JL-NSFET devices is not suitable due to the depreciation of analog/RF FOMs. Moreover interestingly, it is also noticed that the improvement in analog/RF performance (ΔFoM=FoM(T=400) − FoM(T=100)) resulted from lowering the temperature can further be improved by downscaling of Lg and by using low-k gate dielectric.

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Verbitskiy, V. G., S. V. Voevodin, V. V. Fedulov, G. V. Kalistyi, and D. O. Verbitskiy. "Manifestation of the channeling effect when manufacturing JFET transistors." Semiconductor Physics, Quantum Electronics and Optoelectronics 23, no. 04 (November 19, 2020): 379–84. http://dx.doi.org/10.15407/spqeo23.04.379.

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TThe proposed work covers the tasks of such areas as reducing input currents and bias voltage of integrated operational amplifiers (ICs OA) manufactured according to BiFET technology, the prospect of using JFET transistors in digital circuit technology, Si CMOS technology at 22 nm node and beyond, manufacturing bipolar transistors on ultra-thin layers of the active base and emitter, increasing resistance of ICs to external influences. The main method of experimental investigation of channeling is the construction of impurity distribution profiles using SIMS. In this work to study the channeling effect of boron and phosphorus in silicon was chosen the method for constructing the response surface of the saturation current of JFET for a silicon wafer. The choice of method was based on the high sensitivity of the cut-off voltage and saturation current of the JFET transistor to the channel thickness and impurity concentration in it, the relative simplicity of performance and practical benefits in improving BiFET technology.

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Kwon, Ah-Young, Ju-Yeon Jeong, Hyun Park, Sohyun Hwang, Gwangil Kim, Haeyoun Kang, Jin-Hyung Heo, Hye Jin Lee, Tae-Heon Kim, and Hee Jung An. "miR-22-3p and miR-30e-5p Are Associated with Prognosis in Cervical Squamous Cell Carcinoma." International Journal of Molecular Sciences 23, no. 10 (May 17, 2022): 5623. http://dx.doi.org/10.3390/ijms23105623.

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Alteration in expression of miRNAs can cause various malignant changes and the metastatic process. Our aim was to identify the miRNAs involved in cervical squamous cell carcinoma (SqCC) and metastasis, and to test their utility as indicators of metastasis and survival. Using microarray technology, we performed miRNA expression profiling on primary cervical SqCC tissue (n = 6) compared with normal control (NC) tissue and compared SqCC that had (SqC-M; n = 3) and had not (SqC-NM; n = 3) metastasized. Four miRNAs were selected for validation by qRT-PCR on 29 SqC-NM and 27 SqC-M samples, and nine metastatic lesions (ML-SqC), from a total of 56 patients. Correlation of miRNA expression and clinicopathological parameters was analyzed to evaluate the clinical impact of candidate miRNAs. We found 40 miRNAs differentially altered in cervical SqCC tissue: 21 miRNAs were upregulated and 19 were downregulated (≥2-fold, p < 0.05). Eight were differentially altered in SqC-M compared with SqC-NM samples: four were upregulated (miR-494, miR-92a-3p, miR-205-5p, and miR-221-3p), and four were downregulated (miR-574-3p, miR-4769-3p, miR-1281, and miR-1825) (≥1.5-fold, p < 0.05). MiR-22-3p might be a metastamiR, which was gradually further downregulated in SqC-NM > SqC-M > ML-SqC. Downregulation of miR-30e-5p significantly correlated with high stage, lymph node metastasis, and low survival rate, suggesting an independent poor prognostic factor.

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Kumar Rai, Mayank, Rajesh Khanna, and Sankar Sarkar. "Control of tube parameters on SWCNT bundle interconnect delay and power dissipation." Microelectronics International 31, no. 1 (December 20, 2013): 24–31. http://dx.doi.org/10.1108/mi-03-2013-0016.

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Purpose – This paper aims to propose to study the control of tube parameters in terms of diameter, separation between adjacent tubes and length, on delay and power dissipation in single-walled carbon nanotube (SWCNT) bundle interconnect for VLSI circuits. Design/methodology/approach – The paper considers a distributed-RLC model of interconnect. A CMOS-inverter driving a distributed-RLC model of interconnect with load of 1 pF. A 0.1 GHz pulse of 2 ns rise time provides input to the CMOS-inverter. For SPICE simulation, predictive technology model (PTM) is used for the CMOS-driver. The performance of this setup is studied by SPICE simulation in 22 nm technology node. The results are compared with those of currently used copper interconnect. Findings – SPICE simulation results reveal that delay increases with increase in separation between tubes and diameter whereas the reverse is true for power dissipation. The authors also find that SWCNT bundle interconnects are of lower delay than copper interconnect at various lengths and higher power dissipation due to dominance of larger capacitance of tube bundle. Originality/value – The investigations show that tube parameters can control delay and this can also be utilized to decrease power dissipation in SWCNT bundle interconnects for VLSI applications.

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Boureau, Victor, Aurèle Durand, Patrice Gergaud, Delphine Le Cunff, Matthew Wormington, Denis Rouchon, Alain Claverie, Daniel Benoit, and Martin Hÿtch. "Dark-field electron holography as a recording of crystal diffraction in real space: a comparative study with high-resolution X-ray diffraction for strain analysis of MOSFETs." Journal of Applied Crystallography 53, no. 4 (June 18, 2020): 885–95. http://dx.doi.org/10.1107/s1600576720006020.

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Diffraction-based techniques, with either electrons or photons, are commonly used in materials science to measure elastic strain in crystalline specimens. In this paper, the focus is on two advanced techniques capable of accessing strain information at the nanoscale: high-resolution X-ray diffraction (HRXRD) and the transmission electron microscopy technique of dark-field electron holography (DFEH). Both experimentally record an image formed by a diffracted beam: a map of the intensity in the vicinity of a Bragg reflection spot in the former, and an interference pattern in the latter. The theory that governs these experiments will be described in a unified framework. The role of the geometric phase, which encodes the displacement field of a set of atomic planes in the resulting diffracted beam, is emphasized. A detailed comparison of experimental results acquired at a synchrotron and with a state-of-the-art transmission electron microscope is presented for the same test structure: an array of dummy metal–oxide–semiconductor field-effect transistors (MOSFETs) from the 22 nm technology node. Both techniques give access to accurate strain information. Experiment, theory and modelling allow the illustration of the similarities and inherent differences between the HRXRD and DFEH techniques.

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Merad, Faiza, and Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

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Wu, Banqiu. "Next-generation lithography for 22 and 16 nm technology nodes and beyond." Science China Information Sciences 54, no. 5 (May 2011): 959–79. http://dx.doi.org/10.1007/s11432-011-4227-6.

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Ganesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.

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This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.

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McCants, Carl E. "The IARPA Circuit Analysis Tools Program." EDFA Technical Articles 15, no. 4 (November 1, 2013): 52–54. http://dx.doi.org/10.31399/asm.edfa.2013-4.p052.

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Abstract The semiconductor industry continues to scale microelectronics in accordance with Moore’s Law, as the minimum feature size on integrated circuits has decreased from 800 nm in 1993 to 90 nm in 2003 to 22 nm today. In addition, manufacturing advances include 3-D packaging, with multiple dice stacked in various configurations, and 3-D integrated circuits that use through-silicon vias or through-oxide vias to connect the various dice layers. The Intelligence Advanced Research Projects Activity (IARPA) Circuit Analysis Tools (CAT) program is developing tools and techniques to ensure that the U.S. government has capabilities for circuit analysis at future technology nodes, specifically at 22 nm and beyond, and for chips assembled using advanced packaging techniques. This column describes the CAT program activities and goals.

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Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (February 5, 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.

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Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.

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Wang, Guilei, Qiang Xu, Tao Yang, Jinjuan Xiang, Jing Xu, Jianfeng Gao, Chunlong Li, et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology." ECS Journal of Solid State Science and Technology 3, no. 4 (2014): P82—P85. http://dx.doi.org/10.1149/2.015404jss.

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Veloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil, and Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications." Japanese Journal of Applied Physics 50, no. 4S (April 1, 2011): 04DC16. http://dx.doi.org/10.7567/jjap.50.04dc16.

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Wang, G., Q. Xu, T. Yang, J. Luo, J. Xiang, J. Xu, G. Xu, et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology." ECS Transactions 58, no. 10 (August 31, 2013): 317–24. http://dx.doi.org/10.1149/05810.0317ecst.

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Veloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil, and Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications." Japanese Journal of Applied Physics 50, no. 4 (April 20, 2011): 04DC16. http://dx.doi.org/10.1143/jjap.50.04dc16.

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Zhao, Chun, C. Z. Zhao, M. Werner, S. Taylor, and P. R. Chalker. "Advanced CMOS Gate Stack: Present Research Progress." ISRN Nanotechnology 2012 (February 9, 2012): 1–35. http://dx.doi.org/10.5402/2012/689023.

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The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k). When the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology have been a very active research area. This paper reviews the progress and efforts made in the recent years for high-k dielectrics, which can be potentially integrated into 22 nm (and beyond) technology nodes. Our work includes deposition techniques, physical characterization methods at the atomic scale, and device reliability as the focus. For most of the materials discussed here, structural and physical properties, dielectric relaxation issues, and projections towards future applications are also discussed.

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Cui, Hushan, Jun Luo, Jing Xu, Jianfeng Gao, Jinjuan Xiang, Zhaoyun Tang, Xiaolei Wang, et al. "Investigation of TaN as the wet etch stop layer for HKMG-last integration in the 22 nm and beyond nodes CMOS technology." Vacuum 119 (September 2015): 185–88. http://dx.doi.org/10.1016/j.vacuum.2015.05.021.

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Veloso, Anabela, Soon Aik Chew, Tom Schram, Harold Dekkers, Annemie Van Ammel, Thomas Witters, Hilde Tielens, et al. "W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes." Japanese Journal of Applied Physics 52, no. 4S (April 1, 2013): 04CA03. http://dx.doi.org/10.7567/jjap.52.04ca03.

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32

DAOUD, HOUDA, SAMIR BENSELEM, SONIA ZOUARI, and MOURAD LOULOU. "USE OF ROBUST PREDICTIVE METHOD FOR NANO-CMOS PROCESS: APPLICATION TO BASIC BLOCK ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 21, no. 07 (November 2012): 1250061. http://dx.doi.org/10.1142/s0218126612500612.

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This paper deals with the prediction of primary parameters of CMOS transistor for upcoming process using the robust Bisquare Weights method which is able to provide solutions to the challenges of some parameters of Nanoscale CMOS. Predicted parameters for 45 nm to 22 nm process nodes are obtained in order to solve design challenges generated by Nanoscale process. These predicted primary parameters are helpful to estimate the performance of a basic element circuit having a key role in the design of upcoming analog systems. Comparisons between predictive technology model data and predicted parameters are used to check the validity of the used method. As a study case, we will detail the behavior of optimized telescopic operational transconductance amplifier performance with process scaling.

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Chiu, H. Y., Y. K. Fang, T. H. Chou, Y. T. Chiang, and C. I. Lin. "A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology." Semiconductor Science and Technology 22, no. 10 (September 7, 2007): 1157–60. http://dx.doi.org/10.1088/0268-1242/22/10/013.

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"Ultra Low Dielectric Constant Materials for 22 nm Technology Node and beyond." ECS Meeting Abstracts, 2011. http://dx.doi.org/10.1149/ma2011-01/22/1407.

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35

Li, Zongru, Christopher Elash, Jiesi Xing, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Shuting Shi, Zhi Wu Yang, and Bharat L. Bhuva. "SEU Performance of RHBD Flip-Flops Using Guard-Gates at 22-nm FDSOI Technology Node." IEEE Transactions on Nuclear Science, 2023, 1. http://dx.doi.org/10.1109/tns.2023.3284758.

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Wang, Hanbin, Jinshun Bi, Jianhui Bu, Hainan Liu, Fazhan Zhao, Huajun Cao, and Chao Ai. "Characteristics of 22 nm UTBB-FDSOI technology with an ultra-wide temperature range." Semiconductor Science and Technology, August 4, 2022. http://dx.doi.org/10.1088/1361-6641/ac86ec.

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Abstract The performance of the ultra-thin body and buried oxide (BOX) fully-depleted silicon-on-insulator (UTBB-FDSOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on a 22 nm technology node is investigated in this paper over an ultra-wide temperature range from 6 K to 550 K. The current-voltage (I-V) characteristics under wide temperature range conditions are shown, including the influence of the back-gate bias (Vbg). The important electrical parameters, such as threshold voltage (Vt), subthreshold swing (SS), ON-state current (Ion), and OFF-state current (Ioff), are extracted with temperature changes. From 550 K to 6 K, Vtincreased by 0.21 V, Ioff decreased nearly 6 orders of magnitude, and the gate-induced drain leakage (GIDL) current decreased by nearly 8 orders of magnitude. The main physical mechanisms for the changing electrical performance with temperature are the variation of carrier concentration, mobility, and energy band. By utilizing a technology computer-aided design (TCAD) simulation, the temperature dependence of the device performance is discussed and analyzed.

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Wang, Guilei, Jun Luo, Jinbiao Liu, Tao Yang, Yefeng Xu, Junfeng Li, Huaxiang Yin, et al. "pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology." Nanoscale Research Letters 12, no. 1 (April 26, 2017). http://dx.doi.org/10.1186/s11671-017-2080-2.

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Sharma, Vijay Kumar. "A Survey on Low Power Design Approaches in nanoscale regime." Micro and Nanosystems 12 (June 23, 2020). http://dx.doi.org/10.2174/1876402912999200623120558.

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Background: The increased demand of battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality and faster response at lower technology nodes. The applied power supply and threshold voltage of the individual device is scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3-input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and improving the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

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Barik, Rasmita, Rudra Sankar Dhar, Falah Awwad, and Mousa I. Hussein. "Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances." Scientific Reports 13, no. 1 (July 14, 2023). http://dx.doi.org/10.1038/s41598-023-38239-x.

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AbstractThe incubation of strained nano-system in the form of tri-layered structure as nanowire channel in the cylindrical-gate-all-around (CGAA) FET at 10 nm gate length is developed for the first time to keep abreast with the proposed 3 nm technology node of IRDS 2022. The system installs Type-II hetero-strain alignment in the channel attesting itself as the fastest operating device debasing the SCEs at nano regime. The ultra-thin strained-channel comprises of two cylindrical s-Si wells encompassing s-SiGe barrier in between, which enables improvement of carrier mobility by succumbing of quantum charge carriers in the region. This results in 2D charge centroid creation with cylindrical based circular Nano-system contemplating electrostatic potential difference leading to enriched electric field, current density and transconductance, while the gate-all-around architecture with increased gate controllability lowers leakage current, in the device. The 10 nm strained-channel CGAA astounded havoc ON current enhancements of ~ 20% over 22 nm strained CGAA, 57% over Si CGAA FET and 75% over proposed 3 nm technology node IRDS 2022 are accomplished. Hence, carrier mobility and velocity enriches instituting quasi-ballistic transport through the Nanowire channel, thereby augments in ~ 28% drain current so the 10 nm channel CGAA FET stands as the most suitable and improved device in nano regime.

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Yin, Zihan, Md Abdullah-Al Kaiser, Lamine Ousmane Camara, Mark Camarena, Maryam Parsa, Ajey Jacob, Gregory Schwartz, and Akhilesh Jaiswal. "IRIS: Integrated Retinal Functionality in Image Sensors." Frontiers in Neuroscience 17 (September 1, 2023). http://dx.doi.org/10.3389/fnins.2023.1241691.

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Neuromorphic image sensors draw inspiration from the biological retina to implement visual computations in electronic hardware. Gain control in phototransduction and temporal differentiation at the first retinal synapse inspired the first generation of neuromorphic sensors, but processing in downstream retinal circuits, much of which has been discovered in the past decade, has not been implemented in image sensor technology. We present a technology-circuit co-design solution that implements two motion computations—object motion sensitivity and looming detection—at the retina's output that could have wide applications for vision-based decision-making in dynamic environments. Our simulations on Globalfoundries 22 nm technology node show that the proposed retina-inspired circuits can be fabricated on image sensing platforms in existing semiconductor foundries by taking advantage of the recent advances in semiconductor chip stacking technology. Integrated Retinal Functionality in Image Sensors (IRIS) technology could drive advances in machine vision applications that demand energy-efficient and low-bandwidth real-time decision-making.

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Dobbie, Andy, Maksym Myronov, Xue-Chao Liu, Van Huy Nguyen, Evan Parker, and David Leadley. "Investigation of the Thermal Stability of Strained Ge Layers Grown at Low Temperature by Reduced-pressure Chemical Vapour Deposition on Si0.2Ge0.8 Relaxed Buffers." MRS Proceedings 1252 (2010). http://dx.doi.org/10.1557/proc-1252-i04-06.

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AbstractHigh quality strained Ge (s-Ge) epitaxial layers are a promising candidate to achieve high mobility channel MOSFETs suitable for the 22 nm technology node and beyond, due to the intrinsically higher mobility of Ge compared to Si, and the additional performance enhancements from strain [1]. In order to achieve an s-Ge channel more than a few monolayers thick it is necessary to engineer a relaxed Si1-xGex buffer with a high Ge content (x > 0.5). We have recently reported high quality s-Ge layers grown by RP-CVD at low temperature (T ≤ 450 °C), on a fully relaxed Si0.2Ge0.8 buffer [2]. By using a reverse-grading approach, we achieved a high Ge composition in the buffer, with a smooth surface (rms surface roughness of ~2 nm), low threading dislocations density (~ 4 x 106 cm-2) and much thinner (~ 2.1 μm) than can be achieved with conventional linear grading [3].In this work, the thermal stability of s-Ge epilayers (up to 80 nm thick) grown on relaxed Si0.2Ge0.8 buffers has been investigated by in-situ annealing in H2 ambient at temperatures up to 650 °C. These temperatures are similar to those currently used during fabrication of advanced CMOS devices. All s-Ge layers were grown at 400 °C using GeH4 gaseous precursor. The relaxation of the annealed layers has been studied using high-resolution XRD reciprocal space maps (RSMs), and was found to depend strongly on both annealing temperature and thickness of the Ge epilayer. Strained Ge layers up to 50 nm thick remained fully strained after annealing at 450 °C, whereas after annealing at 550 °C s-Ge layers thicker than 20 nm were on the onset of relaxation; after annealing at 650 °C all s-Ge layers showed significant relaxation with defects clearly visible at the Si0.2Ge0.8/Ge interface. All annealed s-Ge layers exhibited higher surface roughness than s-Ge control samples without annealing (rms ~ 2 nm). Annealing at 450 °C resulted in only a slight increase in surface roughness (rms ~ 3 nm), almost independent of s-Ge thickness. However, annealing at 550 °C and 650 °C resulted in significant surface roughening (with maximum rms values of 5 nm and 35 nm, respectively) due to the formation of Ge islands, which were observed by AFM. At these higher temperatures, the surface roughness of the s-Ge layers was found to be thickness dependent, with a Ge smoothing effect observed for layers greater than 50 nm.These results are particularly important for the fabrication of s-Ge MOSFETs, for which the surface passivation prior to gate stack formation is critical to the performance of the device. Based on the results presented here, the thermal budget should be kept below 550 °C to avoid relaxation and roughening of the s-Ge epilayer, which could degrade the device performance.

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Tang, Guangzhi, Kanishkan Vadivel, Yingfu Xu, Refik Bilgic, Kevin Shidqi, Paul Detterer, Stefano Traferro, et al. "SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges." Frontiers in Neuroscience 17 (June 23, 2023). http://dx.doi.org/10.3389/fnins.2023.1187252.

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Neuromorphic processors aim to emulate the biological principles of the brain to achieve high efficiency with low power consumption. However, the lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. This paper proposes SENECA, a digital neuromorphic architecture that balances the trade-offs between flexibility and efficiency using a hierarchical-controlling system. A SENECA core contains two controllers, a flexible controller (RISC-V) and an optimized controller (Loop Buffer). This flexible computational pipeline allows for deploying efficient mapping for various neural networks, on-device learning, and pre-post processing algorithms. The hierarchical-controlling system introduced in SENECA makes it one of the most efficient neuromorphic processors, along with a higher level of programmability. This paper discusses the trade-offs in digital neuromorphic processor design, explains the SENECA architecture, and provides detailed experimental results when deploying various algorithms on the SENECA platform. The experimental results show that the proposed architecture improves energy and area efficiency and illustrates the effect of various trade-offs in algorithm design. A SENECA core consumes 0.47 mm2 when synthesized in the GF-22 nm technology node and consumes around 2.8 pJ per synaptic operation. SENECA architecture scales up by connecting many cores with a network-on-chip. The SENECA platform and the tools used in this project are freely available for academic research upon request.

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43

Ayush, Poornima Mittal, and Rajesh Rohilla. "Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM." ACM Transactions on Design Automation of Electronic Systems, August 2, 2023. http://dx.doi.org/10.1145/3611672.

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A modified decoupled sense amplifier (MDSA) and modified decoupled sense amplifier with NMOS foot-switch is proposed for improved sensing in differential SRAM for low voltage operation at 22 nm technology node. The MDSA and MDSANF both offer notable improvements to read delay over conventional voltage and current sense amplifiers. At an operating voltage of 0.8 V, the MDSA exhibited a reduced delay of 28.6%, 41.79%, 37.74%, 30.94% compared to modified clamped sense amplifier (MCSA), double tail sense amplifier(DTSA), modified hybrid sense amplifier (MHSA) and conventional latch-type sense amplifier (LSA) respectively. Similarly, the MDSANF demonstrated a delay reduction of 26.13%, 39.78%, 35.58%, 28.55% over MCSA, DTSA, MHSA and LSA respectively. To validate the performance, the MDSA and MDSANF are evaluated using the variation in delay and power consumption across various supply voltages, process corners, input differential bit line voltage ( Δ V BL ), bit line capacitance C BL ) and the sizing of decoupling transistors. Monte Carlo simulations were conducted to analyse the impact of voltage threshold variations on transistor mismatch which leads to an increased occurrence of read failures and a decline in SRAM yield. The performance analysis of various voltage and current sense amplifiers is presented along with MDSA and MDSANF. Area consideration for selection of sensing scheme is important and as such layout of MDSA and MDSANF was performed conforming to the design rules and estimated area for MDSA is 0.297 μ m 2 whereas MDSANF occupies 0.5192 μ m 2 .

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Letertre, Fabrice Jerome. "Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology." MRS Proceedings 1068 (2008). http://dx.doi.org/10.1557/proc-1068-c01-01.

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ABSTRACTEngineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies.The Smart Cutä technology, introduced in the mid 1990's by M. Bruel [2] is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs [3], InP [4], SiC [5], GaN [6], Germanium [7] ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates?In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates.[1] B. Ghyselen et al., ICSI3 proc., 173 5 (2003)[2] M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995)[3] E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998)[4] E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999)[5] L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)[6] A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127[7] F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004).[8] B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118[9] H. Larèche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004)[10] G. Meneghesso et al , IEDM 2007, to be published[11] Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004)[12] J. Dorsaz and al., Proceedings, ICNS6 (2005)[13] S.G. Thomas et al., IEEE EDL Vol. 26, July 2005.[14] K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34

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45

Moreau, Stephane, Fré;déric Gaillard, Jean-Charles Barbé, Raphaël Gras, Gérard Passemard, and Joaquin Torres. "Mechanical Integrity Study of Air Gap Structures Assisted by FE Simulations." MRS Proceedings 1079 (2008). http://dx.doi.org/10.1557/proc-1079-n02-02.

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ABSTRACTIn this paper, mechanical reliability of “air gap” structures has been evaluated when a copper line is completely surrounded with air. Different Finite Element (FE) simulation models have been used on a 2-metal level structure to study the M2 copper line bow evolution as a function of its dimensions if complete air cavities are generated underneath (i.e. at via level). Design rules information may therefore be obtained to optimize “air gap” integration considering the 65 nm and 22 nm technology nodes. Thus, we not only highlight that M2 copper line can not collapse considering our failure criterion but that M2 bow variation may also be improved when a tensile SiCN capping layer is deposited on top of the structure. The influence of the interline spacing vs. M2 bow has also been studied and we show that its increase is a beneficial parameter for the air gap structure. In opposite, we demonstrate that buckling can occur when a compressive SiCN layer is used. Finally, we accurately predict the M2 bow variation for air gap structures of the 65 nm and 22 nm technology nodes, but stress and strain distribution can complementary be provided. Those results highlight interesting criteria for designers to build reliable air gap structures.

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46

"Application of Atomic Layer Deposition Tungsten (ALD W) as gate filling metal for 22 nm and beyond nodes CMOS technology." ECS Meeting Abstracts, 2013. http://dx.doi.org/10.1149/ma2013-02/24/1890.

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47

Dhillon, Gurleen, and Karmjit Singh Sandha. "Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes." Journal of Circuits, Systems and Computers 31, no. 05 (November 10, 2021). http://dx.doi.org/10.1142/s0218126622500980.

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The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

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"Two-Dimensional Chemical Delineation of Junction Profile with High Spatial Resolution and Application in Failure Analysis in 65 nm Technology Node." ECS Meeting Abstracts, 2009. http://dx.doi.org/10.1149/ma2009-02/22/1988.

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Smaani, Billel, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav, and Shubham Tayal. "Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance." ECS Journal of Solid State Science and Technology, February 6, 2023. http://dx.doi.org/10.1149/2162-8777/acb96b.

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Abstract Nanosheet field effect transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7 nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including the impact of self-heating effect (SHE) and also the influence of geometry scaling. The thermal resistance and the maximum lattice temperature have been analyzed according to the device’s channel number. Also, the distribution of lattice temperature has been exposed. During the 3D investigation, it has been observed that SHE degrades the switching performance and subthreshold swing SS≈22%. Furthermore, it is found that the proposed device is showing improved figure of merits as ION (~2.77×10-5A), IOFF (~10-20A), SS (>60mV/decade) and ION/IOFF (~1015). The DIBL has been reduced by -52% when the NS’s width ranges from 10 to 5 nm, and increased from 32 to 92 mV/V when the gate-length decreases from 14 to 8 nm.

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Journal articles on the topic '22-nm technology node'

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