Relevant bibliographies by topics / 22~nm

Academic literature on the topic '22~nm'

Author: Grafiati
Published: 25 May 2024

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Contents

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic '22~nm.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "22~nm"

1

Bloomstein, T. M., Michael F. Marchant, Sandra Deneault, Dennis E. Hardy, and Mordechai Rothschild. "22-nm immersion interference lithography." Optics Express 14, no. 14 (2006): 6434. http://dx.doi.org/10.1364/oe.14.006434.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Sadana, Devendra, Stephen W. Bedell, J. P. De Souza, Y. Sun, E. Kiewra, A. Reznicek, T. Adams, et al. "CMOS Scaling Beyond 22 nm Node." ECS Transactions 19, no. 5 (December 18, 2019): 267–74. http://dx.doi.org/10.1149/1.3119551.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Buengener, Ralf, Carol Boye, Bryan N. Rhoads, Sang Y. Chong, Charu Tejwani, Sean D. Burns, Andrew D. Stamper, et al. "Process Window Centering for 22 nm Lithography." IEEE Transactions on Semiconductor Manufacturing 24, no. 2 (May 2011): 165–72. http://dx.doi.org/10.1109/tsm.2011.2106807.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Parker, Matthew. "A sub-terahertz transceiver in 22 nm FinFET." Nature Electronics 5, no. 3 (March 2022): 126. http://dx.doi.org/10.1038/s41928-022-00741-x.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kurd, Nasser, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, et al. "Haswell: A Family of IA 22 nm Processors." IEEE Journal of Solid-State Circuits 50, no. 1 (January 2015): 49–58. http://dx.doi.org/10.1109/jssc.2014.2368126.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Huang, Ru, HanMing Wu, JinFeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, et al. "Challenges of 22 nm and beyond CMOS technology." Science in China Series F: Information Sciences 52, no. 9 (September 2009): 1491–533. http://dx.doi.org/10.1007/s11432-009-0167-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Shiotani, Hideaki, Shota Suzuki, Dong Gun Lee, Patrick Naulleau, Yasuyuki Fukushima, Ryuji Ohnishi, Takeo Watanabe, and Hiroo Kinoshita. "Dual Grating Interferometric Lithography for 22-nm Node." Japanese Journal of Applied Physics 47, no. 6 (June 20, 2008): 4881–85. http://dx.doi.org/10.1143/jjap.47.4881.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Seifert, N., B. Gill, S. Jahinuzzaman, J. Basile, V. Ambrose, Quan Shi, R. Allmon, and A. Bramnik. "Soft Error Susceptibilities of 22 nm Tri-Gate Devices." IEEE Transactions on Nuclear Science 59, no. 6 (December 2012): 2666–73. http://dx.doi.org/10.1109/tns.2012.2218128.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Zhang, Bo, Min Zhang, and Tianhong Cui. "Low-cost shrink lithography with sub-22 nm resolution." Applied Physics Letters 100, no. 13 (March 26, 2012): 133113. http://dx.doi.org/10.1063/1.3697836.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

Full text
Abstract:
Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "22~nm"

1

Bansal, Anil Kumar. "CMOS scaling considerations in sub 10-nm node multiple-gate FETS." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8046.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Baldauf, Tim. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-132044.

Full text
Abstract:
Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab
Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work
APA, Harvard, Vancouver, ISO, and other styles
3

Hamioud, Karim. "Élaboration et caractérisation des interconnexions pour les nœuds technologiques CMOS 32 et 22 nm." Lyon, INSA, 2010. http://www.theses.fr/2010ISAL0011.

Full text
Abstract:
Les performances globales des circuits intégrés doivent augmenter d’environ 20 % à chaque nouvelle génération technologique. Les interconnexions constituant ces circuits ces circuits doivent participer à l’augmentation de ces performances et plus particulièrement à la réduction du temps de propagation des signaux. L’utilisation de diélectrique poreux à très faible permittivité est nécessaire pour les générations sub-45 nm. Dans un premier temps, une feuille de route pour une filière BEOL 32 nm performante est proposée. Les développements de procédés élémentaires ont permis de démontrer la fonctionnalité d’un démonstrateur multi niveaux au minimum des règles de dessin de la technologie 32 nm. Dans un deuxième temps, l’utilisation d’une technologie mature 45 nm a permis l’étude de l’intégration des diélectriques poreux k = 2. 3 et k = 2. 2 qui sont respectivement les candidats potentiels pour les générations 32 et 22 nm. L’introduction de ces matériaux dans l’architecture d’intégration permet d’améliorer les performances des circuits mais la fiabilité diélectrique de ces matériaux se retrouve dégradée par rapport au matériau k = 2. 5 de référence. Ainsi, après avoir mis en évidence les différentes sources de dégradation de la fiabilité diélectrique, une réponse au critère de fiabilité a permis la définition d’un schéma d’architecture fiable. Ce schéma d’intégration fiabilisée et performante utilise une barrière métallique TaN/Ta robuste et l’ajout d’une couche diélectrique supplémentaire dans l’empilement technologique. Ce schéma d’architecture fiable et performant constitue une bonne base de départ pour les futures filières BEOL 32 et 22 nm
[The overall performance of integrated circuits should grow by about 20% at each new technology node. The interconnects have to be involved in increasing the performance and specially the reduction of signal propagation. The use of porous ultra low-k dielectric is necessary for the Sub-45 nm generation. In a first step, a roadmap for the 32 nm BEOL is proposed. The elementary processes developments have demonstrated the functionality of a multi-level demonstrator at minimum design rules of 32 nm technology node. In second step, a mature 45 nm technology has enabled the integration study of porous dielectric k = 2. 3 and k = 2. 2 which are potential candidates, respectively, for the 32 and 22 nm technology nodes. The introduction of these materials in the BEOL architecture scheme improves circuit performance but the dielectric reliability is found damaged from the reference k = 2. 5 material. Consequently, after to have identified the different sources of the dielectric reliability degradation, a response to the reliability standard has allowed the definition of reliable architecture. This reliable architecture used a robust metal barrier TaN/Ta robust and an additional layer in the dielectric stack technology. This reliable and efficient architecture represents a good beginning for the future 32 and 22 nm BEOL technology nodes. ]
APA, Harvard, Vancouver, ISO, and other styles
4

Öberg, Eric, and Gustav Kindeskog. "16 GS/s Continuous-Time ΣΔ Modulator in a 22 nm SOI Process : a Simulation and Feasibility Study." Thesis, Linköpings universitet, Tekniska fakulteten, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-155781.

Full text
Abstract:
With a reference specification model in terms of 8 GS/s Sigma Delta Modulator in a 28 nm CMOS process consuming 890 mW, the purpose with this thesis is to construct a similar and simpler model but with higher specification demands. In a 22 nm SOI process with an input signal bandwidth of 500 MHz sampled at 16 GS/s with a power consumption below 2 W, the objective is to design a Continuous-Time Sigma Delta Modulator with verified simulated functionality on a transistor level basis. This specification is accomplished - with a power consumption in total of 75 mW. The design methodology is divided into an integrator part along with a quantizer and feedback DAC part. A top-down strategy is carried out starting with an ideal high level Verilog-A model for the complete system, followed by a hardware implementation on transistor level.
APA, Harvard, Vancouver, ISO, and other styles
5

Bauer, Heiner. "Dynamic instruction set extension of microprocessors with embedded FPGAs." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-222858.

Full text
Abstract:
Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, however, with the significant advantage of post-fabrication flexibility. Not only does this offer similar gains in performance but also the flexibility to configure each device individually. This thesis explored the benefit of a tight coupled and fine-grained reconfigurable microprocessor. In contrast to previous research, a detailed design space exploration of logical architectures for island-style field programmable gate arrays (FPGAs) has been performed in the context of a commercial 22nm process technology. Other research projects either reused general purpose architectures or spent little effort to design and characterize custom fabrics, which are critical to system performance and the practicality of frequently proposed high-level software techniques. Here, detailed circuit implementations and a custom area model were used to estimate the performance of over 200 different logical FPGA architectures with single-driver routing. Results of this exploration revealed similar tradeoffs and trends described by previous studies. The number of lookup table (LUT) inputs and the structure of the global routing network were shown to have a major impact on the area delay product. However, results suggested a much larger region of efficient architectures than before. Finally, an architecture with 5-LUTs and 8 logic elements per cluster was selected. Modifications to the microprocessor, whichwas based on an industry proven instruction set architecture, and its software toolchain provided access to this embedded reconfigurable fabric via custom instructions. The baseline microprocessor was characterized with estimates from signoff data for a 28nm hardware implementation. A modified academic FPGA tool flow was used to transform Verilog implementations of custom instructions into a post-routing netlist with timing annotations. Simulation-based verification of the system was performed with a cycle-accurate processor model and diverse application benchmarks, ranging from signal processing, over encryption to computation of elementary functions. For these benchmarks, a significant increase in performance with speedups from 3 to 15 relative to the baseline microprocessor was achieved with the extended instruction set. Except for one case, application speedup clearly outweighed the area overhead for the extended system, even though the modeled fabric architecturewas primitive and contained no explicit arithmetic enhancements. Insights into fundamental tradeoffs of island-style FPGA architectures, the developed exploration flow, and a concrete cost model are relevant for the development of more advanced architectures. Hence, this work is a successful proof of concept and has laid the basis for further investigations into architectural extensions and physical implementations. Potential for further optimizationwas identified on multiple levels and numerous directions for future research were described
Zunehmend komplexere Anwendungen und Besonderheiten moderner Halbleitertechnologien haben zu einer großen Nachfrage an leistungsfähigen und gleichzeitig sehr energieeffizienten Mikroprozessoren geführt. Konventionelle Architekturen versuchen den Befehlsdurchsatz durch Parallelisierung zu steigern und stellen anwendungsspezifische Befehlssätze oder Hardwarebeschleuniger zur Steigerung der Energieeffizienz bereit. Rekonfigurierbare Prozessoren ermöglichen ähnliche Performancesteigerungen und besitzen gleichzeitig den enormen Vorteil, dass die Spezialisierung auf eine bestimmte Anwendung nach der Herstellung erfolgen kann. In dieser Diplomarbeit wurde ein rekonfigurierbarer Mikroprozessor mit einem eng gekoppelten FPGA untersucht. Im Gegensatz zu früheren Forschungsansätzen wurde eine umfangreiche Entwurfsraumexploration der FPGA-Architektur im Zusammenhang mit einem kommerziellen 22nm Herstellungsprozess durchgeführt. Bisher verwendeten die meisten Forschungsprojekte entweder kommerzielle Architekturen, die nicht unbedingt auf diesen Anwendungsfall zugeschnitten sind, oder die vorgeschlagenen FGPA-Komponenten wurden nur unzureichend untersucht und charakterisiert. Jedoch ist gerade dieser Baustein ausschlaggebend für die Leistungsfähigkeit des gesamten Systems. Deshalb wurden im Rahmen dieser Arbeit über 200 verschiedene logische FPGA-Architekturen untersucht. Zur Modellierung wurden konkrete Schaltungstopologien und ein auf den Herstellungsprozess zugeschnittenes Modell zur Abschätzung der Layoutfläche verwendet. Generell wurden die gleichen Trends wie bei vorhergehenden und ähnlich umfangreichen Untersuchungen beobachtet. Auch hier wurden die Ergebnisse maßgeblich von der Größe der LUTs (engl. "Lookup Tables") und der Struktur des Routingnetzwerks bestimmt. Gleichzeitig wurde ein viel breiterer Bereich von Architekturen mit nahezu gleicher Effizienz identifiziert. Zur weiteren Evaluation wurde eine FPGA-Architektur mit 5-LUTs und 8 Logikelementen ausgewählt. Die Performance des ausgewählten Mikroprozessors, der auf einer erprobten Befehlssatzarchitektur aufbaut, wurde mit Ergebnissen eines 28nm Testchips abgeschätzt. Eine modifizierte Sammlung von akademischen Softwarewerkzeugen wurde verwendet, um Spezialbefehle auf die modellierte FPGA-Architektur abzubilden und eine Netzliste für die anschließende Simulation und Verifikation zu erzeugen. Für eine Reihe unterschiedlicher Anwendungs-Benchmarks wurde eine relative Leistungssteigerung zwischen 3 und 15 gegenüber dem ursprünglichen Prozessor ermittelt. Obwohl die vorgeschlagene FPGA-Architektur vergleichsweise primitiv ist und keinerlei arithmetische Erweiterungen besitzt, musste dabei, bis auf eine Ausnahme, kein überproportionaler Anstieg der Chipfläche in Kauf genommen werden. Die gewonnen Erkenntnisse zu den Abhängigkeiten zwischen den Architekturparametern, der entwickelte Ablauf für die Exploration und das konkrete Kostenmodell sind essenziell für weitere Verbesserungen der FPGA-Architektur. Die vorliegende Arbeit hat somit erfolgreich den Vorteil der untersuchten Systemarchitektur gezeigt und den Weg für mögliche Erweiterungen und Hardwareimplementierungen geebnet. Zusätzlich wurden eine Reihe von Optimierungen der Architektur und weitere potenziellen Forschungsansätzen aufgezeigt
APA, Harvard, Vancouver, ISO, and other styles
6

Baldauf, Tim [Verfasser], Gerald [Akademischer Betreuer] Gerlach, and Roland [Akademischer Betreuer] Stenzel. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie / Tim Baldauf. Gutachter: Gerald Gerlach ; Roland Stenzel. Betreuer: Gerald Gerlach ; Roland Stenzel." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://d-nb.info/1068444916/34.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Delpeyroux, Francis. "Insertions dans l'antigène de surface du virus de l'hépatite B expression d'un épitote de neutralisation du poliovirus à la surface departicules de 22 nm." Grenoble : ANRT, 1987. http://catalogue.bnf.fr/ark:/12148/cb37593763m.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Delpeyroux, Francis. "Insertions dans l'antigene de surface du virus de l'hepatite b : expression d'un epitope de neutralisation du poliovirus a la surface de particules de 22 nm." Paris 7, 1987. http://www.theses.fr/1987PA077198.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Lecat-Mathieu, de Boissac Capucine. "Developing radiation-hardening solutions for high-performance and low-power systems." Electronic Thesis or Diss., Aix-Marseille, 2021. http://www.theses.fr/2021AIXM0413.

Full text
Abstract:
De nouveaux acteurs industriels déploient de larges constellations de satellites, tandis que d'autres domaines comme l'industrie automobile développent des systèmes robustes. Ces systèmes s'appuient sur des technologies avancées, telles que le UTBB FD-SOI, afin d'atteindre les performances nécessaires. La complexité et la vitesse croissantes des systèmes nécessitent une caractérisation précise de ces technologies, ainsi qu'une adaptation des techniques traditionnelles de durcissement. L'objectif est l'étude des effets des radiations dans les technologies FD-SOI et bulk, ainsi que la recherche de mécanismes innovants de durcissement. Une structure intégrée de mesures des SETs, auto-calibrée et conçue grâce à un flot de conception automatisé est d'abord présentée. Elle permet la caractérisation de 4 technologies. La réponse aux radiations des cellules numériques est ensuite évaluée par des tests sous faisceau et par le biais de simulations TCAD, permettant d'étudier l'influence de la tension, de la fréquence de fonctionnement ainsi que l'application d'une tension en face arrière sur la sensibilité. Le TID est également étudié à l'aide d'un bloc de mesure intégré. Les différents résultats sont ensuite utilisés afin de proposer une nouvelle solution de durcissement pour les systèmes sur puce, qui rassemble les précédents blocs de mesure dans un module d'évaluation en temps réel du milieu radiatif. Une unité de gestion de l'énergie pour adapter les modes de fonctionnement au profil de mission. Enfin, une utilisation détournée du détecteur de SETs est proposée dans un contexte de sécurité des systèmes pour détecter et contrer les attaques laser
New actors have accelerated the pace of putting new satellites into orbit, and other domains like the automotive industry are at the origin of this development. These new actors rely on advanced technologies, such as UTBB FD-SOI in order to be able to achieve the necessary performance to accomplish the tasks. Albeit disruptive in terms of intrinsic soft-error resistance, the growing density and complexity of spaceborne and automotive systems require an accurate characterization of technologies, as well as an adaptation of traditional hardening techniques. This PhD focuses on the study of radiation effects in advanced FD-SOI and bulk silicon processes, and on the research of innovative protection mechanisms. A custom, self-calibrating transient measurements structure with automated design flow is first presented, allowing for the characterization of four different technologies during accelerated tests. The soft-error response of 28~nm FD-SOI and 40~nm bulk logic and storage cells is then assessed through beam testing and with the help of TCAD simulations, allowing to study the influence of voltage, frequency scaling and the application of forward body biasing on sensitivity. Total ionizing dose is also investigated through the use of an on-chip monitoring block. The test results are then utilized to propose a novel hardening solution for system on chip, which gathers the monitoring structures into a real-time radiation environment assessment and a power management unit for power mode adjustments. Finally, as an extension of the SET sensors capability, an implementation of radiation monitors in a context of secure systems is proposed to detect and counteract laser attacks
APA, Harvard, Vancouver, ISO, and other styles
10

Lallement, Guénolé. "Extension of socs mission capabilities by offering near-zero-power performances and enabling continuous functionality for Iot systems." Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0573.

Full text
Abstract:
Les développements récents dans le domaine des circuits intégrés (IC) à basse tension ont ouvert la voie à des dispositifs électroniques économes en énergie dans un réseau mondial en plein essor appelé l’internet des objets (IoT) ou l’internet des choses (IoE). Cependant, la durabilité de tous ces capteurs interconnectés est compromise par le besoin constant d’une batterie embarquée – qui doit être rechargée ou remplacée – ou d’un récupérateur d’énergie à rendement très limité. La consommation d’énergie des systèmes électroniques grand public actuels est en effet cinquante fois plus élevée que celle d’un collecteur d’une taille de l’ordre du cm 2 , ou limitée à quelques mois sur une petite batterie. Cela contraint la viabilité de solutions fonctionnant à l’échelle d’une vie humaine. Les systèmes sur puce (SoCs) à venir nécessitent donc de relever le défi de cette lacune énergétique en optimisant l’architecture, de la technologie au niveau du système. L’approche technique de ce travail vise à démontrer la faisabilité d’un SoC efficient, ultra-basse tension (ULV) et ultra-basse puissance (ULP) utilisant exclusivement les dernières directives industrielles en matière de technologies FD-SOI (Fully Depleted Silicon On Insulator) 28 nm et 22 nm. Plusieurs SoCs multi-domaines basés sur des cœurs ARM sont implémentés pour démontrer des stratégies de réveil basées sur les entrées des capteurs. Ainsi, en optimisant l’architecture du système, en sélectionnant et en concevant correctement les composants avec des caractéristiques technologiques choisies de manière adéquate, et en ajustant soigneusement l’implémentation physique, on obtient un SoC entièrement optimisé en énergie
Recent developments in the field of low voltage integrated circuits (IC) have paved the way towards energy efficient electronic devices in a booming global network called the internet-of-things (IoT) or the internet-of-everything (IoE). However, the sustainability of all these inter- connected sensors is still undermined by the constant need for either an on-board battery – that must be recharged or replaced – or an energy harvester with very limited power efficiency. The power consumption of present consumer electronic systems is fifty times higher than the energy available by cm 2-size harvester or limited to a few months on a small battery, thus hardly viable for lifetime solutions. Upcoming systems-on-chip (SoCs) must overcome the challenge of this energy gap by architecture optimizations from technology to system level. The technical approach of this work aims to demonstrate the feasibility of an efficient ultra-low-voltage (ULV) and ultra-low-power (ULP) SoC using exclusively latest industrial guidelines in 28 nm and 22 nm fully depleted silicon on insulator (FD-SOI) technologies. Several multi-power-domain SoCs based on ARM cores are implemented to demonstrate wake up strategies based on sensors inputs. By optimizing the system architecture, properly selecting and designing compo- nents with technology features chosen adequately, carefully tuning the implementation, a fully energy-optimized SoC is realized
APA, Harvard, Vancouver, ISO, and other styles

Books on the topic "22~nm"

1

IEEE, International Nonvolatile Memory Technology Conference (7th 1998 Albuquerque New Mexico). Seventh biennial IEEE Nonvolatile Memory Technology Conference: Proceedings : 1998 conference : June 22-24, 1998, Albuquerque, NM, USA. Piscataway, N.J: IEEE, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

IEEE Geoscience and Remote Sensing Society., Lasers and Electro-optics Society (Institute of Electrical and Electronics Engineers), and IEEE Microwave Theory and Techniques Society., eds. Topical Symposium on Combined Optical-microwave Earth and Atmosphere Sensing: Conference proceedings, March 22-25, 1993, Albuquerque, NM. Piscataway, NJ: Institute of Electrical and Electronics Engineers, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Symposium, on Time-of-Flight Diffraction at Pulsed Neutron Sources (1993 Albuquerque N. M. ). Proceedings of the Symposium on Time-of-Flight Diffraction at Pulsed Neutron Sources: At Albuquerque Convention Center, Albuquerque, NM, May 22-28, 1993. Buffalo, NY: American Crystallographic Association, 1994.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Center for Nonlinear Studies. International Conference. Nonlinearity in materials science: Proceedings of the twelfth annual International Conference of the Center for Nonlinear Studies, Los Alamos, NM 87545, USA, 18-22 May 1992. Edited by Bishop Alan, Ecke R, and Gubernatis James. Amsterdam: North-Holland, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Center of Nonlinear Studies. International Conference. Nonlinearity in biology and medicine: Proceedings of theseventh annual international conference of the Center for Nonlinear Studies, Los Alamos National Laboratory, Los Alamos, NM 87545, USA, May 18-22, 1987. Edited by Perelson Alan S. New York: Elsevier, 1988.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Labor, United States Congress House Committee on Education and. Civil Rights Restoration Act of 1985: Joint hearings before the Committee on Education and Labor, and the Subcommittee on Civil and Constitutional Rights of the Committee on the Judiciary, House of Representatives, Ninety-ninth Congress, first session on H.R. 700 ... hearings held in Philadelphia, PA, March 4; Washington, DC, March 7, 27, 28, and April 2; Atlanta, GA, March 11; Chicago, Il, March 15; Los Angeles, CA, March 22; and Santa Fe, NM, March 25, 1985. Washington: U.S. G.P.O., 1986.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Balasinski, Artur. Design for Manufacturability: From 1d to 4D for 90 22 NM Technology Nodes. Springer New York, 2016.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90–22 nm Technology Nodes. Springer, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90-22 Nm Technology Nodes. Springer London, Limited, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "22~nm"

1

Valasa, Sresta, and Shubham Tayal. "Modeling and Analysis of Low Power High-Speed Phase Detector and Phase Frequency Detector Using Nano Dimensional MOS Transistors at 16 nm, 22 nm, 32 nm." In Lecture Notes in Electrical Engineering, 1–11. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6780-1_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Poiroux, T., F. Andrieu, O. Weber, C. Fenouillet-Béranger, C. Buj-Dufournet, P. Perreau, L. Tosti, L. Brevard, and O. Faynot. "Ultrathin Body Silicon on Insulator Transistors for 22 nm Node and Beyond." In Semiconductor-On-Insulator Materials for Nanoelectronics Applications, 155–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-15868-1_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Delwar, Tahesin Samira, Sourav Biswas, and Anindya Jana. "Realization of hybrid single electron transistor based low power circuits in 22 nm technology." In Computational Science and Engineering, 27–32. CRC Press/Balkema, P.O. Box 11320, 2301 EH Leiden, The Netherlands, e-mail: Pub.NL@taylorandfrancis.com, www.crcpress.com – www.taylorandfrancis.com: CRC Press, 2016. http://dx.doi.org/10.1201/9781315375021-7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Cordova, David, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot, and Yohan Piccin. "Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI." In VLSI-SoC: Design Trends, 1–19. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81641-4_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Imtiaz, Shamim, and Ruqaiya Khanam. "Design and Analysis Delay of FinFET and CMOS 6T SRAM Using 22 nm Technology." In Studies in Autonomic, Data-driven and Industrial Computing, 449–60. Singapore: Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-5435-3_32.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Kannaujiya, Aryan, Narendra Yadava, Mangal Deep Gupta, and Rajeev Kumar Chauhan. "Improvement of Leakage Current in Double Pocket FDSOI 22 nm Transistor Using Gate Metal Arrangement." In Lecture Notes in Electrical Engineering, 227–35. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0312-0_23.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Vasudeva, G., and B. V. Uma. "Two-Stage Folded Resistive String 12-Bit Digital to Analog Converter Using 22-nm FINFET." In Sustainable Communication Networks and Application, 119–37. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6605-6_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Prouvée, J., G. Mangraviti, B. Debaillie, P. Wambacq, D. Borggreve, R. Ciocoveanu, H. Fredriksson, et al. "Digital Beamforming Transceiver Design in 22 nm FD-SOI Technology for 39 GHz 5G Access." In Technologies Enabling Future Mobile Connectivity & Sensing, 31–55. New York: River Publishers, 2023. http://dx.doi.org/10.1201/9781032633039-4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Wang, Guilei. "Introduction." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 1–7. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wang, Guilei. "Strained Silicon Technology." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 9–21. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "22~nm"

1

Bakker, Jelle H. T., Mark S. Oude Alink, Jurriaan Schmitz, and Bram Nauta. "Characterisation of Photodiodes in 22 nm FDSOI at 850 nm." In ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC). IEEE, 2023. http://dx.doi.org/10.1109/essderc59256.2023.10268483.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Buengener, Ralf, Carol Boye, Bryan N. Rhoads, Sang Y. Chong, Charu Tejwani, Sean D. Burns, Andrew D. Stamper, et al. "Process Window Centering for 22 nm lithography." In 2010 21st Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2010. http://dx.doi.org/10.1109/asmc.2010.5551447.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Seo, Soon-Cheon, Chih-Chao Yang, Chun-Chen Yeh, Bala Haran, Dave Horak, Susan Fan, Charles Koburger, et al. "Copper contact metallization for 22 nm and beyond." In 2009 IEEE International Interconnect Technology Conference - IITC. IEEE, 2009. http://dx.doi.org/10.1109/iitc.2009.5090326.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Auth, Chris. "22-nm fully-depleted tri-gate CMOS transistors." In 2012 IEEE Custom Integrated Circuits Conference - CICC 2012. IEEE, 2012. http://dx.doi.org/10.1109/cicc.2012.6330657.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Bourdillon, Antony J., Gwyn P. Williams, Yuli Vladimirsky, and Chris B. Boothroyd. "22-nm lithography using near-field x rays." In Microlithography 2003, edited by Roxann L. Engelstad. SPIE, 2003. http://dx.doi.org/10.1117/12.484989.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

TIAN, Ming, Cuiqin XU, and Haibo LEI. "Advanced 22 nm FD-SOI devices integration platform." In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2019. http://dx.doi.org/10.1109/s3s46989.2019.9320694.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Shiotani, Hideaki, Shota Suzuki, Dong Gun Lee, Patrick Naulleau, Takeo Watanabe, Yasuyuki Fukushima, Ryuji Ohnishi, and Hiroo Kinoshita. "Dual grating interferometric lithography for 22-nm node." In 2007 Digest of papers Microprocesses and Nanotechnology. IEEE, 2007. http://dx.doi.org/10.1109/imnc.2007.4456097.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Gambino, J. P. "Copper interconnect technology for the 22 nm node." In 2011 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2011. http://dx.doi.org/10.1109/vtsa.2011.5872228.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Yang, Edward, and Torsten Lehmann. "High Gain Operational Amplifiers in 22 nm CMOS." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702381.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Afifah Maheran, A. H., P. S. Menon, I. Ahmad, H. A. Elgomati, B. Y. Majlis, and F. Salehuddin. "Scaling down of the 32 nm to 22 nm gate length NMOS transistor." In 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2012. http://dx.doi.org/10.1109/smelec.2012.6417117.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "22~nm"

1

Becher, Julie, Samuel Beal, Susan Taylor, Katerina Dontsova, and Dean Wilcox. Photo-transformation of aqueous nitroguanidine and 3-nitro-1,2,4-triazol-5-one : emerging munitions compounds. Engineer Research and Development Center (U.S.), August 2021. http://dx.doi.org/10.21079/11681/41743.

Full text
Abstract:
Two major components of insensitive munition formulations, nitroguanidine (NQ) and 3-nitro-1,2,4-triazol-5-one (NTO), are highly water soluble and therefore likely to photo-transform while in solution in the environment. The ecotoxicities of NQ and NTO solutions are known to increase with UV exposure, but a detailed accounting of aqueous degradation rates, products, and pathways under different exposure wavelengths is currently lacking. We irradiated aqueous solutions of NQ and NTO over a 32-h period at three ultraviolet wavelengths and analyzed their degradation rates and transformation products. NQ was completely degraded by 30 min at 254 nm and by 4 h at 300 nm, but it was only 10% degraded after 32 h at 350 nm. Mass recoveries of NQ and its transformation products were >80% for all three wavelengths. NTO degradation was greatest at 300 nm with 3% remaining after 32 h, followed by 254 nm (7% remaining) and 350 nm (20% remaining). Mass recoveries of NTO and its transformation products were high for the first 8 h but decreased to 22–48% by 32 h. Environmental half-lives of NQ and NTO in pure water were estimated as 4 and 6 days, respectively. We propose photo-degradation pathways for NQ and NTO supported by observed and quantified degradation products and changes in solution pH.
APA, Harvard, Vancouver, ISO, and other styles
2

Perkins, Dustin. Invasive exotic plant monitoring at Fossil Butte National Monument: 2021 field season. Edited by Alice Wondrak Biel. National Park Service, September 2022. http://dx.doi.org/10.36967/2288496.

Full text
Abstract:
Invasive exotic plant (IEP) species are one of the biggest threats to natural ecosystem integrity and biodiversity, and controlling them is a high priority for the National Park Service. The Northern Colorado Plateau Network (NCPN) selected the early detection of IEPs as one of 11 monitoring protocols to be implemented as part of its long-term monitoring program. This report represents work completed during the 2021 field season at Fossil Butte National Monument (NM). From June 26 to 29, 2021, we recorded a total of 12 different priority IEP species during monitoring. A total of 763 priority IEP patches were recorded along 61.9 kilometers (38.5 mi) of 22 monitoring routes. Summer cypress (Bassia scoparia) was detected for the first time on monitoring routes along the Main Park Road. The highest densities of IEP patches were detected in several drainages and one trail: Sage Grouse Lek Drainage (32.7 patches/km), East Red Hill Drainage (19.4/km), Moose Bones Canyon (19.4/km), Main Park Road (19.0/km), West Fork Chicken Creek (17.6/km), Chicken Creek (15.0/km), Smallpox Creek (13.5/km) and the Historic Quarry Trail (11.1/km). The Fossil Butte Northwest, Wasatch Saddle, and North Dam Fork of Chicken Creek drainages were the only routes free of priority IEPs in 2021. Cheatgrass (Bromus tectorum), creeping foxtail (Alopecurus arundi-naceus), and Japanese brome (Bromus japonicus) were the most widespread species. Creeping foxtail continues to increase parkwide and along the Main Park Road and southern drainages. The two brome species have declined somewhat since 2018, but these species can fluctuate widely based on precipitation. Flixweed (Descurainia sophia), whitetop (Cardaria sp.), and quackgrass (Elymus repens) all appear to have declined since 2018 and their previous highs in earlier years. Control efforts by park staff are likely helping to prevent some IEP increases in the park. Network staff plan to return to Fossil Butte NM for an eighth round of monitoring in 2023.
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic '22~nm' for particular source types:
Journal articles Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography