Academic literature on the topic '16-Bit float'

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems.

This paper proposes a Polar-coded neural damapper based 5G multiple-input multiple-output (MIMO) system for M transmitting and N receiving antenna, operating in a flat fading environment. MIMO is a spatial diversity scheme to improve channel performance and mitigate troubling fading issues in urban environments. A neural network-based smart demapper is considered instead of traditional demapper to improve the system's performance. Researchers have recently focused on developing complex neural network (NN)-based demapper on generating soft information for each transmitted bit. Neural demapper also increases spectral efficiency, meaning a symbol-to-bit demapper with higher complexity. This work considers a Polar-coded MIMO 5G communication system with 2×3, 2×4, 4×6 and 4×16 transmitting and receiving antennas, respectively, to evaluate the system performance under QAM modulation (4-QAM, 16-QAM, 256-QAM) techniques. It is evident from the simulated result that our proposed system performs better for lower-order modulation techniques with an increase in the number of transmitting and receiving antenna.

Dark matter is one of the top unsolved mysteries in physics. Its existence is well-established although its nature remains unknown. Despite the progress made in the direct search effort, reflecting over 10 orders of magnitude in sensitivity since 1984, no true candidates to explain this phenomenon have appeared in searches covering a range from ~10 GeV to 1 TeV. This article reports on the development of a 1 kg freon bubble chamber prototype, including the chamber recompression system design and testing, initial acoustic detection of bubble formation, and initial neutron and alpha detector response studies. The prototype constructed was a transparent acrylic containment vessel, capable of withstanding recompression cycles to a pressure of 16 bar. The acoustic signal accompanying bubble formation was investigated using three different sensors: a low frequency microphone (Panasonic) with a flat response over 0.020-16 kHz, an ultrasound externallypolarized condenser microphone (AviSoft) with a flat response over 10-150 kHz, and an hydrophone (Reson) with a flat response over 5-170 kHz. Acoustic signatures of several induced events were successfully registered. The data acquisition digitizer used, to meet the range of the three microphones, was the NI PCI-6251 16-Bit, with at least 1.25 MSps for 1-Channel.

With increasing real-time constraints being put on the use of Deep Neural Networks (DNNs) by real-time scenarios, there is the need to review information representation. A very challenging path is to employ an encoding that allows a fast processing and hardware-friendly representation of information. Among the proposed alternatives to the IEEE 754 standard regarding floating point representation of real numbers, the recently introduced Posit format has been theoretically proven to be really promising in satisfying the mentioned requirements. However, with the absence of proper hardware support for this novel type, this evaluation can be conducted only through a software emulation. While waiting for the widespread availability of the Posit Processing Units (the equivalent of the Floating Point Unit (FPU)), we can already exploit the Posit representation and the currently available Arithmetic-Logic Unit (ALU) to speed up DNNs by manipulating the low-level bit string representations of Posits. As a first step, in this paper, we present new arithmetic properties of the Posit number system with a focus on the configuration with 0 exponent bits. In particular, we propose a new class of Posit operators called L1 operators, which consists of fast and approximated versions of existing arithmetic operations or functions (e.g., hyperbolic tangent (TANH) and extended linear unit (ELU)) only using integer arithmetic. These operators introduce very interesting properties and results: (i) faster evaluation than the exact counterpart with a negligible accuracy degradation; (ii) an efficient ALU emulation of a number of Posits operations; and (iii) the possibility to vectorize operations in Posits, using existing ALU vectorized operations (such as the scalable vector extension of ARM CPUs or advanced vector extensions on Intel CPUs). As a second step, we test the proposed activation function on Posit-based DNNs, showing how 16-bit down to 10-bit Posits represent an exact replacement for 32-bit floats while 8-bit Posits could be an interesting alternative to 32-bit floats since their performances are a bit lower but their high speed and low storage properties are very appealing (leading to a lower bandwidth demand and more cache-friendly code). Finally, we point out how small Posits (i.e., up to 14 bits long) are very interesting while PPUs become widespread, since Posit operations can be tabulated in a very efficient way (see details in the text).

We introduce an improved image transmission scheme over wireless channels with flat Rayleigh fading. The proposed scheme jointly optimizes bit power and modulation level to maximize the peak signal-to-noise ratio (PSNR) of the reconstructed image and hence improves the perceptual quality of the received image. In this optimization process, the significance of bits with regard to the overall quality of the image is exploited. The optimality of the proposed algorithm is demonstrated using the Lagrange method and verified through an iterative offline exhaustive search algorithm. For practical implementation, a look-up table is used at the transmitter for assigning the bit power and modulation level to each bit stream according to the received signal-to-noise ratio (SNR) observed at the receiver. The proposed scheme has low complexity since the look-up table is computed offline, only once, and used for any image which makes it suitable for devices with limited processing capability. Analytical and simulation results show that the proposed scheme with jointly optimized bit power and variable modulation level provides an improvement in PSNR of about 10 to 20 dB over fixed power fixed modulation (16-QAM). A further reduction in complexity is achieved by using the average signal-to-noise ratio rather than the instantaneous SNR in selecting the system parameters.

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. A key technique for producing statistically accurate fading variates is to shape the flat spectrum of Gaussian variates using digital filters. This paper addresses various challenges when designing real and complex spectrum shaping filters with quantized coefficients for efficient realization of both isotropic and nonisotropic fading channels. An iterative algorithm for designing stable complex infinite impulse response (IIR) filters with fixed-point coefficients is presented. The performance of the proposed filter design algorithm is verified with 16-bit fixed-point simulations of two example fading filters.

4501 Background: Periop. FLOT has become SOC for resectable, esophagogastric adenocarcinoma. However, patient’s outcome is still poor. This trial evaluates the addition of the VEGF-R2 inhibitor ramucirumab (RAM) to FLOT for resectable patients (pts). Methods: This is a prospective, international, randomized, investigator-initiated phase II/III trial. Pts with resectable, Her2-negative, adenocarcinoma of the stomach and GEJ (≥ cT2 or cN+) were enrolled. Pts were randomized to 4 pre-and post-operative cycles of FLOT (docetaxel 50 mg/m²; oxaliplatin 85 mg/m²; leucovorin 200 mg/m²; 5-FU 2600 mg/m², q2w) alone (Arm A) or the same regimen with RAM 8mg/kg q2w, followed by 16 cycles RAM (Arm B, FLOT-RAM). Important endpoints of phase II (exploratory) were major pathological (complete and nearly complete) response, centrally assessed acc. to Becker criteria, R0-resection rate, and safety. GEJ type I tumors and pts requiring trans-thoracic esophagectomy were excluded for safety reasons during the conduct of the study. Results: In total, 180 pts were randomized. Baseline characteristics were similar between arms (male, 73%; median age, 60y; cT3/T4, 83%; cN+, 78%; GEJ, 54%; signet-ring cells, 40%). However, the FLOT-RAM arm included more unfavorable pts with T4 (9% vs. 4%), Siewert type I tumors (18% vs. 13%), impaired ECOG PS of 1 (34% vs. 20%), and concomitant disease (87% vs. 79%). 91% of pts with FLOT and 92% with FLOT-RAM completed the 4 pre- cycles. R0-resection (in the full set) could be achieved in 83% of pts with FLOT and 97% of pts with FLOT-RAM (p = 0.0049). The rate of major path response was similar in both arms and was 30% for FLOT and 27% for FLOT-RAM. Surgical morbidity was observed in 37% of pts with FLOT and 44% of pts with FLOT-RAM. Mortality was 2.5% with FLOT and 5.9% with FLOT-RAM including GEJ type I tumors and dropped to 2.9% in both arms after excluding type I tumors per amendment. There was bit more G≥3 adverse events with FLOT-RAM (78% vs. 89%). Conclusions: In this phase II trial, the addition of ramucirumab to perioperative FLOT significantly improved R0-resection rates without an impact on path response, mainly because more patients could proceed to operation. The FLOT-RAM is safe, when type I tumors are excluded. Clinical trial information: NCT02661971 .

4042 Background: Periop. FLOT has become SOC for resectable, esophagogastric adenocarcinoma. However, patient’s outcome is still poor. This trial evaluates the addition of the VEGF-R2 inhibitor ramucirumab (RAM) to FLOT for resectable patients (pts). Methods: This is a prospective, international, randomized, investigator-initiated phase II/III trial. Pts with resectable, Her2-negative, adenocarcinoma of the stomach and GEJ type II and III (≥ cT2 or cN+) were enrolled. Pts were randomized to 4 pre-and post-operative cycles of FLOT (docetaxel 50 mg/m²; oxaliplatin 85 mg/m²; leucovorin 200 mg/m²; 5-FU 2600 mg/m², q2w) alone (Arm A) or the same regimen with RAM 8mg/kg q2w, followed by 16 cycles RAM (Arm B, FLOT-RAM). Important endpoints of phase II (exploratory) were major pathological (complete and nearly complete) response, centrally assessed acc. to Becker criteria, R0-resection rate, overall survival (OS), disease-free survival (DFS) and safety. GEJ type I tumors and pts requiring trans-thoracic esophagectomy were excluded for safety reasons during the conduct of the study. Results: In total, 152 pts were analyzed within the intention to treat population. Baseline characteristics were similar between arms (male, 70%; median age, 60y; cT3/T4, 82%; cN+, 77%; GEJ, 45%). The rate of cancers with signet-ring cell component was at 45%. The FLOT-RAM arm included more unfavorable pts with T4 (8% vs. 5%), impaired ECOG PS of 1 (32% vs. 20%), and concomitant disease (86% vs. 76%). 92% of pts with FLOT as well as with FLOT-RAM completed the 4 pre- cycles. R0-resection could be achieved in 82% of pts with FLOT and 96% of pts with FLOT-RAM (p = 0.0093). The rate of major path response was similar in both arms and was 29% for FLOT and 26% for FLOT-RAM. Median DFS was slightly improved in pts with FLOT-RAM (32 months vs. 21 months), while median OS was similar in both treatment arms (FLOT 45 months, FLOT-RAM 46 months). Surgical morbidity was observed in 32% of pts with FLOT and 41% of pts with FLOT-RAM. Mortality at 60 days after surgery was 4.1% with FLOT and 2.8% with FLOT-RAM. There were bit more G≥3 adverse events with FLOT-RAM (76% vs. 92%). Conclusions: In this phase II trial, the addition of ramucirumab to perioperative FLOT significantly improved R0-resection rates and slightly prolonged DFS without an impact on path response or overall survival. FLOT-RAM is feasible and safe, when type I tumors are excluded. Clinical trial information: NCT02661971.

Cette thèse porte sur l'optimisation et l'implémentation efficace d'algorithmes d'estimation du mouvement des pixels (flot optique) sur des processeurs graphiques (GPU) embarqués. Deux algorithmes itératifs ont été étudiés : la méthode de Variation Totale - L1 (TV-L1) et la méthode de Horn-Schunck. L’objectif est d’obtenir un traitement temps réel (moins de 40 ms par images) sur des plateformes embarquées à faible consommation énergétique, tout en gardant une résolution image et une qualité d’estimation du flot acceptable pour les applications visées. Différents niveaux de stratégies d'optimisation ont été explorés. Des transformations algorithmiques de haut niveau, telles que la fusion d'opérateurs et le pipeline d'opérateurs, ont été mises en œuvre pour maximiser la réutilisation des données et améliorer la localité spatiale/temporelle. De plus, des optimisations bas niveau spécifiques aux GPU, notamment l'utilisation d'instructions et de nombres vectoriels, ainsi qu'une gestion efficace de l'accès à la mémoire, ont été intégrées. L'impact de la représentation des nombres en virgule flottante (simple précision par rapport à demi-précision) a également été étudié. Les implémentations ont été évaluées sur les plateformes embarquées Nvidia Jetson Xavier, TX2 et Nano en termes de temps d'exécution, de consommation énergétique et de précision du flot optique. Notamment, la méthode TV-L1 présente une complexité et une intensité de calcul plus élevées par rapport à Horn-Schunck. Les versions les plus rapides de ces algorithmes atteignent ainsi un temps de traitement de 0,21 nanosecondes par pixel par itération en demi-précision sur la plate-forme Xavier. Cela représente une réduction du temps d'exécution de 22x par rapport aux versions CPU efficaces et parallèles. De plus, la consommation d'énergie est réduite d'un facteur x5,3. Parmi les cartes testées, la plate-forme embarquée Xavier, à la fois la plus puissante et la plus récente, offre systématiquement les meilleurs résultats en termes de vitesse et d'efficacité énergétique. La fusion d'opérateurs et le pipelining se sont avérés essentiels pour améliorer les performances sur GPU en favorisant la réutilisation des données. Cette réutilisation des données est rendue possible grâce à la mémoire Shared des GPU, une petite mémoire d'accès rapide permettant le partage de données entre les threads du même bloc de threads GPU. Bien que la fusion de plusieurs itérations apporte des gains de performance, elle est limitée par la taille de la mémoire Shared, nécessitant des compromis entre l'utilisation des ressources et la vitesse. L'utilisation de nombres en demi-précision accélère les algorithmes itératifs et permet d'obtenir une meilleure précision du flot optique dans le même laps de temps par rapport aux versions en simple-précision. Les implémentations en demi-précision convergent plus rapidement en raison de l'augmentation du nombre d'itérations réalisables dans un délai donné. Plus précisément, l'utilisation de nombres en demi-précision sur la meilleure architecture GPU accélère l'exécution jusqu'à 2,2x pour TV-L1 et 3,7x pour Horn-Schunck. Ces travaux soulignent l'importance des optimisations spécifiques aux GPU pour les algorithmes de vision par ordinateur, ainsi que l'utilisation et l'étude des nombres à virgule flottante de précision réduite. Ils ouvrent la voie à des améliorations futures grâce à des différentes transformations algorithmiques, à des formats numériques différents et à des architectures matérielles nouvelles. Cette approche peut également être étendue à d'autres familles d'algorithmes itératifs
This thesis focus on the optimization and efficient implementation of pixel motion (optical flow) estimation algorithms on embedded graphics processing units (GPUs). Two iterative algorithms have been studied: the Total Variation - L1 (TV-L1) method and the Horn-Schunck method. The primary objective of this work is to achieve real-time processing, with a target frame processing time of less than 40 milliseconds, on low-power platforms, while maintaining acceptable image resolution and flow estimation quality for the intended applications. Various levels of optimization strategies have been explored. High-level algorithmic transformations, such as operator fusion and operator pipelining, have been implemented to maximize data reuse and enhance spatial/temporal locality. Additionally, GPU-specific low-level optimizations, including the utilization of vector instructions and numbers, as well as efficient memory access management, have been incorporated. The impact of floating-point number representation (single-precision versus half-precision) has also been investigated. The implementations have been assessed on Nvidia's Jetson Xavier, TX2, and Nano embedded platforms in terms of execution time, power consumption, and optical flow accuracy. Notably, the TV-L1 method exhibits higher complexity and computational intensity compared to Horn-Schunck. The fastest versions of these algorithms achieve a processing rate of 0.21 nanoseconds per pixel per iteration in half-precision on the Xavier platform, representing a 22x time reduction over efficient and parallel CPU versions. Furthermore, energy consumption is reduced by a factor of x5.3. Among the tested boards, the Xavier embedded platform, being both the most powerful and the most recent, consistently delivers the best results in terms of speed and energy efficiency. Operator merging and pipelining have proven to be instrumental in improving GPU performance by enhancing data reuse. This data reuse is made possible through GPU Shared memory, which is a small, high-speed memory that enables data sharing among threads within the same GPU thread block. While merging multiple iterations yields performance gains, it is constrained by the size of the Shared memory, necessitating trade-offs between resource utilization and speed. The adoption of half-precision numbers accelerates iterative algorithms and achieves superior optical flow accuracy within the same time frame compared to single-precision counterparts. Half-precision implementations converge more rapidly due to the increased number of iterations possible within a given time window. Specifically, the use of half-precision numbers on the best GPU architecture accelerates execution by up to x2.2 for TV-L1 and x3.7 for Horn-Schunck. This work underscores the significance of both GPU-specific optimizations for computer vision algorithms, along with the use and study of reduced floating point numbers. They pave the way for future enhancements through new algorithmic transformations, alternative numerical formats, and hardware architectures. This approach can potentially be extended to other families of iterative algorithms

Aprevious essay (see “Which Operating System Is Right for You,” p. 16), pointed out that your choice of hardware depends largely on your choice of operating system. So let’s assume that you’ve made up your mind and decided whether you want a Mac or a PC. The next question is whether you want a desktop or a laptop. Ask yourself a couple of relevant questions. Do you work in one place or you are a “road warrier”? Is space a consideration? Will this be your only computer? And how much can you afford? Feature for feature, desktops are cheaper than laptops. Normally, they are also more expandable. You can add more RAM, a better video card, an additional hard drive, a DVD or CD burner, or any of a number of other devices—provided that there are empty slots on the motherboard for additional expansion boards and empty drive bays in the case. You might eventually be able to add a more powerful processor, thus prolonging the useful life of your computer. Desktop cases are relatively easy to open, making it possible for intrepid users to install these items themselves. So check for expandability before you buy. You’ll need a monitor, of course. You’ll pay a bit less for one that comes with your desktop computer, but the dread sign in computer ads saying, “Monitor sold separately,” may not be such a bad thing. You may want something better than your computer vendor is offering. Having a large, steady, clear monitor can make a real difference in the quality of your computing experience. Broadly, there are two kinds to choose from now, and both flat-panel monitors and CRTs have distinct advantages. Sales of flat-panel monitors are fast catching up with those of CRTs, but—as always—your choice will depend on how you plan to use your computer, how much space you have, and the extent to which you are seduced by beauty and coolness. Flat-panel monitors, with their clean, slender profiles, are indeed appealing. (To find out why, see “The Ten Best Tools and Peripherals You Didn’t Know About,” p. 196.) New flat panels (and, by the way, laptop screens) come with TFT displays (that is, active-matrix, not the older, fuzzier passive-matrix displays), and their glare-free screens are easy on the eyes.

In the final reaction of this part I am going to help you extend your ability to use our toolkit to build a network of carbon atoms. The reaction I talk about here is one of many that I could have chosen and will give you some insight into the way that organic chemists go about building their intricate constructions. It was devised in 1877 by the French chemist Charles Friedel (1832–1899) and the American chemist James Crafts (1839–1917). There are two kinds of Friedel–Crafts reaction: I shall call them Type 1 and Type 2. The latter is more important, but the former is a bit simpler and I shall deal with it first. In a Type 1 Friedel–Crafts reaction, the aim is to attach a group of C atoms, such as 1, to a benzene ring or a related molecule. The strategy is to generate a powerful electrophile (Reaction 16), one characteristic of the group of atoms you want to attach, which will seek out regions of dense electron cloud in the target benzene molecule. The tactics involve taking the group you want to attach in combination with a chlorine atom, Cl, as in 2, and then finding another dentist-like compound that will extract the Cl atom as a chloride ion, Cl–. That extraction will leave a positively charged hydrocarbon ion hungry for opposite charge and thus able to act as the electrophile. The Friedel–Crafts procedure uses aluminium chloride, 3, to act as this dentist compound. It gets regenerated in the reaction, so it is present as a catalyst (Reaction 11). When you examine this molecule you see that although its Cl atoms are rich in electrons, the aluminium atom, Al, has a very skimpy share in them and the positive charge of its nucleus shines through. Moreover, the molecule is flat, and there is plenty of room for the Cl atoms to bend away from any incoming intruder atom and so make room for its attachment to the Al atom.

Abstract Drilling the intermediate section of deep gas wells in a Middle East field is quite challenging due to geological and wellbore instability problems, and the associated risks such as total losses, twist-off, stuck pipe, and casing not reaching bottom. Casing-While-Drilling (CWD) combined with stage-cementing tool with inflatable external packer has been implemented in a 16″ intermediate section to prove the viability of the technology in such downhole conditions, and moreover, improve the operational economics of drilling this section with conventional drilling. Whereas CWD is a proven drilling technology worldwide and deployed across the field at shallower depths or smaller sizes, a proof-of-concept implementation would be needed in a deep gas well to establish the limits for the technology while drilling in a big hole size (16″) to a deep casing point (~5,000 ft). An extensive case study for the application of CWD was conducted, which covered the main technical concerns: torque while drilling, casing fatigue, drilling fluid strategy, float equipment and stage-cementing tool reliability, expected rate-of-penetration and bit design, drilling parameters road map, and contingencies. CWD level 2 technology was successfully implemented in the gas field for the first time. The technology had proven its viability in a deep big hole size by drilling approximately 500 ft in the above problematic section, and across the more challenging formations to a total depth of 6,501 ft. The section was drilled with 70 hours of on-bottom drilling and a total of 88.25 hours of tripping and circulation. A new benchmark was established for the reliability of float equipment and stage collar with constant rotation as reaching the total depth of a challenging drilling environment. Plastering effect also proved its liability as no losses was observed despite the high risk from offset wells. Additionally, no losses were induced in case of full circulation scenario, and cementing operations completed successfully with no losses. Low vibrations, and smooth torque observed while drilling. The main advantages of this implementation in gas wells are mitigating the potential risk of wellbore instability related to lost circulation, minimizing potential twist-off and stuck pipe events, and reducing the hole exposure time due to excessive reaming while tripping. Shale reaction and hole bridging in the formation can be avoided since no tripping is required. CWD has been proved as a feasible technology for challenging intermediate sections in gas wells. Further developing the technology in the field for risk mitigations and optimizing the operational economics are ongoing, such as introduction of new CWD PDC bit and performance improvement from identified lessons identified. This manuscript will share the developing strategy behind proof-of-concept and technology evolution and will serve as a reference for service companies and operators in the region in similar cases.

In this work, we compared the precision, speed, and power consumption of the reciprocal square root of a single-precision floating point number, using different approximation techniques. We also devised an equivalent approximation for half-precision floating point numbers, and evaluated its performance across the whole range of positive non-zero 16-bit floating point values.

Abstract Drilling horizontal wells with a high dogleg severity (DLS) of 10–16 deg/30 m is the approach that one operator in Oman adopted to drill the buildup section. The 8½-in section used to be drilled with a conventional motor BHA, which took around 4 days to complete. Due to the high DLS, it was required to slide at least 80% of the time. This led to a slow drilling rate, hole cleaning issues, and difficulties running the 7-in liner afterward. For a step change to happen, a full directional drilling system had to be reengineered with an extensive study of the BHA and well design. The objective was to reduce the total drilling time in the 8½-in BUS, improve the borehole quality, and reduce flat time. Traditional rotary steerable systems (RSS) are limited with their steering capabilities. A hybrid, high-build-rate RSS with push- and point-the-bit features offers the capabilities of achieving a DLS of up to 17 deg/30 m as it is independent of outside formation. Implementing the new approach eliminated the long sliding intervals and poor borehole cleaning caused by limited surface rotation with the motor BHA. The system was modeled using finite element drilling dynamics simulation software, with multiple bits and drillstring configurations to optimize the directional results. In addition, compressive study of the mud properties enabled drilling the section safely throughout Nahr Umar shale. Later, the same system was coupled with a high-torque motor, and the results showed an even better performance, which the operator plans to consider in the future to enhance the drilling rate. The use of a hybrid RSS system with a specific bit built for the application has proven its success as an integrated engineered drilling solution. It reduced the 8½-in section drilling time by 50% with improved borehole quality and delivered an overall ROP that is approximately three times what a motor BHA would have delivered. The improvement is a result of the use of PDC over TCI bits and the elimination of slide drilling. In addition, full rotation and elimination of micro-DLS resulted in smoother liner running operation. While drilling, the 100% rotational steering improved the overall hole cleaning, and the modified mud properties and additives helped eliminate the wiper trips performed previously prior to reaching the reservoir section. The success of this integrated system led the operator to replace all the motors in the entire field. This paper emphasizes the impact of new technology together with effective well engineering in drilling efficiency. With current industry focus on cost control, high-DLS RSS technology introduces new savings when used in the right application. This particular case is very common across the industry and proves the many advantages of integrated engineering projects.

Flexible electronics provide new design options not afforded by rigid electronics in a variety of applications including wearable electronics, robotics and automotive systems. However, the processes for the manufacturing of complex electronic assemblies using fine-pitch components are not as well developed as those for rigid electronics. The lack of structural rigidity of flexible printed circuit cards requires attention to assembly configuration for double-sided flexible assemblies. In addition, mechanisms are needed to compensate for the deformation and warpage of the flexible substrate and components during assembly. In this paper, the stresses in solder joints of double-sided flexible assemblies have been measured during thermal excursions using x-ray micro-computed tomography in conjunction with digital volume correlation. The method allows for non-invasive measurement and does not require cross-sectioning of the part for the purpose of deformation and strain measurement. In addition, the measurements are not limited to the joints in the line of sight. The three-dimensional measurements of deformation and strain have been visualized on the geometry of the solder joints in the package. Digital volume correlation (DVC) method has been used to find the displacements and strains in interconnects of operational electronics. The x-ray microscopic computed tomography (μCT) system has been used to generate the 16 bit digital volume data. The x-ray detector has ability to image the x-ray attenuation of x-rays through the object. Reliability testing of SAC 305 solder interconnects has been performed on double-sided flexible circuit board using x-ray μCT by heating the package to 100°C. The flexible circuit board used in this experiment is of BGA 256-144 combination, two packages, A-PBGA256-1.0mm-17mm and A-CABGA144-1.0mm-13mm. A 3D printed fixture has also been used to support the flexible board and keep it flat while in the CT scan machine. The reference and deformed scans are then re-constructed 3D using Volume Graphics, and Digital Volume Correlation performed using MATLAB modules. Reliability of double-sided flexible printed circuit boards will be discussed and any crack, defects, or deformation in the solder interconnectivity which might occur while heating the package on flexible board is presented. The solder joint strains during thermal excursions are also compared between the flexible and rigid printed circuit assemblies.