Journal articles on the topic '10T SRAM CELL'
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Elangovan, M., and K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 10 (December 19, 2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.
Full textReddy Gujjula, Nagarjuna, and Rameshbabu Kellampalli. "Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor." International Journal of Scientific Methods in Engineering and Management 01, no. 01 (2023): 47–57. http://dx.doi.org/10.58599/ijsmem.2023.1105.
Full textGanesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.
Full textRao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak, and Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications." Journal of Electrical and Computer Engineering 2023 (June 7, 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.
Full textIslam, A., and M. Hasan. "Leakage Characterization of 10T SRAM Cell." IEEE Transactions on Electron Devices 59, no. 3 (March 2012): 631–38. http://dx.doi.org/10.1109/ted.2011.2181387.
Full textChaurasia, Ranu, Brijesh Kumar, Sudhanshu Verma, and Akhilesh Kumar. "Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques." IOP Conference Series: Materials Science and Engineering 1272, no. 1 (December 1, 2022): 012007. http://dx.doi.org/10.1088/1757-899x/1272/1/012007.
Full textLiu, Changjun, Hongxia Liu, and Jianye Yang. "A Novel Low-Power and Soft Error Recovery 10T SRAM Cell." Micromachines 14, no. 4 (April 13, 2023): 845. http://dx.doi.org/10.3390/mi14040845.
Full textZhou, Hong Gang, Qiang Song, Chun Yu Peng, and Shou Biao Tan. "A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture." Applied Mechanics and Materials 263-266 (December 2012): 9–14. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.9.
Full textSingh, Arjun, and Sangeeta Nakhte. "Optimized High Performance 10T SRAM Cell Characterization." International Journal of Computer Applications 134, no. 5 (January 15, 2016): 29–33. http://dx.doi.org/10.5120/ijca2016907964.
Full textGupta, Neha, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl, and Patrick Girard. "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications." Electronics 10, no. 14 (July 17, 2021): 1718. http://dx.doi.org/10.3390/electronics10141718.
Full textShah, Ambika Prasad, and Michael Waltl. "Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell." Electronics 9, no. 2 (February 3, 2020): 256. http://dx.doi.org/10.3390/electronics9020256.
Full textAparna and Ram Chandra Singh Chauhan. "Low Power PPN inverter based 10T SRAM Cell." Indian Journal of Science and Technology 14, no. 20 (May 25, 2021): 1699–710. http://dx.doi.org/10.17485/ijst/v14i20.400.
Full textSharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (March 9, 2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.
Full textLakshmi, T. Venkata, T. Edukondalu, S. Rahul, R. S. P. L. Suvarna, and T. Rohit Chaitanya. "A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (April 30, 2023): 714–21. http://dx.doi.org/10.22214/ijraset.2023.50158.
Full textZhou, Hong Gang, Shou Biao Tan, Qiang Song, and Chun Yu Peng. "A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS." Applied Mechanics and Materials 373-375 (August 2013): 1607–11. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.1607.
Full textLeavline, Epiphany Jebamalar, and Arumugam Sugantha. "Reliability improved dual driven feedback 10T SRAM bit cell." Microelectronics Reliability 139 (December 2022): 114804. http://dx.doi.org/10.1016/j.microrel.2022.114804.
Full textAhmad, Sayeed, Naushad Alam, and Mohd Hasan. "A Robust 10T SRAM Cell with Enhanced Read Operation." International Journal of Computer Applications 129, no. 2 (November 17, 2015): 7–12. http://dx.doi.org/10.5120/ijca2015906751.
Full textLimachia, Mitesh Jethabhai, Rajesh A. Thakker, and Nikhil J. Kothari. "Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology." Circuit World 44, no. 4 (November 5, 2018): 187–94. http://dx.doi.org/10.1108/cw-01-2018-0002.
Full textJoshi, Shital, and Umar Alabawi. "Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM." Journal of Nanotechnology 2017 (2017): 1–9. http://dx.doi.org/10.1155/2017/4575013.
Full textMansore, S. R., and Amit Naik. "Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell." Journal of VLSI Design and Signal Processing 8, no. 3 (November 16, 2022): 18–22. http://dx.doi.org/10.46610/jovdsp.2022.v08i03.003.
Full textBhanuchandar, R., B. Harikrishna, and Suman Mishra. "10T Sram cell designusing single ended decoupled read bit line." Indian Journal of Public Health Research & Development 9, no. 11 (2018): 2081. http://dx.doi.org/10.5958/0976-5506.2018.01757.6.
Full textShah, Ambika Prasad, Santosh Kumar Vishvakarma, and Michael Hübner. "Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications." Journal of Electronic Testing 36, no. 2 (March 6, 2020): 255–69. http://dx.doi.org/10.1007/s10836-020-05864-7.
Full textManikandan, A. "Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures." Journal of Electronics,Computer Networking and Applied Mathematics, no. 22 (March 26, 2022): 29–39. http://dx.doi.org/10.55529/jecnam.22.29.39.
Full textYao, Ruxue, Hongliang Lv, Yuming Zhang, Xu Chen, Yutao Zhang, Xingming Liu, and Geng Bai. "A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications." Micromachines 14, no. 7 (June 25, 2023): 1305. http://dx.doi.org/10.3390/mi14071305.
Full textMuthusamy, Parimaladevi, and Sharmila Dhandapani. "Leakage Characterization of a Novel Transmission Gate based 10T SRAM Cell." Asian Journal of Research in Social Sciences and Humanities 6, no. 7 (2016): 844. http://dx.doi.org/10.5958/2249-7315.2016.00469.x.
Full textKumar, C. I., and B. Anand. "Design of highly reliable energy‐efficient SEU tolerant 10T SRAM cell." Electronics Letters 54, no. 25 (December 2018): 1423–24. http://dx.doi.org/10.1049/el.2018.7267.
Full textFeki, Anis, Bruno Allard, David Turgis, Jean-Christophe Lafont, Faress Tissafi Drissi, Fady Abouzeid, and Sebastien Haendler. "Sub-threshold 10T SRAM bit cell with read/write XY selection." Solid-State Electronics 106 (April 2015): 1–11. http://dx.doi.org/10.1016/j.sse.2014.11.018.
Full textSudha, D., Ch Santhi Rani, and Sreenivasa Rao Ijjada. "SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects." Acta Physica Polonica A 135, no. 4 (April 2019): 702–4. http://dx.doi.org/10.12693/aphyspola.135.702.
Full textMansore, S. R., R. S. Gamad, and D. K. Mishra. "A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability." Journal of Circuits, Systems and Computers 29, no. 05 (July 1, 2019): 2050067. http://dx.doi.org/10.1142/s021812662050067x.
Full textKiran, PN Vamsi, and Nikhil Saxena. "Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed." International Journal of Hybrid Information Technology 9, no. 2 (February 28, 2016): 111–22. http://dx.doi.org/10.14257/ijhit.2016.9.2.10.
Full textRahman Aura, Shourin, S. M. Ishraqul Huq, and Satyendra N. Biswas. "Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature." International journal of electrical and computer engineering systems 13, no. 9 (December 6, 2022): 823–29. http://dx.doi.org/10.32985/ijeces.13.9.11.
Full textShakouri, Erfan, Behzad Ebrahimi, Nima Eslami, and Mohammad Chahardori. "Single-Ended 10T SRAM Cell with High Yield and Low Standby Power." Circuits, Systems, and Signal Processing 40, no. 7 (January 11, 2021): 3479–99. http://dx.doi.org/10.1007/s00034-020-01636-y.
Full textDohar, Suraj Singh, Siddharth R. K., Vasantha M. H., and Nithin Kumar Y. B. "A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application." IEEE Transactions on Electron Devices 68, no. 5 (May 2021): 2265–70. http://dx.doi.org/10.1109/ted.2021.3064899.
Full textDolatshah, Amir, Erfan Abbasian, Maryam Nayeri, and Sobhan Sofimowloodi. "A sub-threshold 10T FinFET SRAM cell design for low-power applications." AEU - International Journal of Electronics and Communications 157 (December 2022): 154417. http://dx.doi.org/10.1016/j.aeue.2022.154417.
Full textMANSORE, Shivram, and Radheshyam GAMAD. "A data-aware write-assist 10T SRAM cell with bit-interleaving capability." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 26, no. 5 (September 28, 2018): 2361–73. http://dx.doi.org/10.3906/elk-1801-272.
Full textJahinuzzaman, Shah M., David J. Rennie, and Manoj Sachdev. "A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability." IEEE Transactions on Nuclear Science 56, no. 6 (December 2009): 3768–73. http://dx.doi.org/10.1109/tns.2009.2032090.
Full textAbbasian, Erfan, Farzaneh Izadinasab, and Morteza Gholipour. "A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins." IEEE Transactions on Circuits and Systems I: Regular Papers 69, no. 4 (April 2022): 1606–16. http://dx.doi.org/10.1109/tcsi.2021.3138849.
Full textSachdeva, Ashish, and V. K. Tomar. "Design of 10T SRAM cell with improved read performance and expanded write margin." IET Circuits, Devices & Systems 15, no. 1 (December 15, 2020): 42–64. http://dx.doi.org/10.1049/cds2.12006.
Full textShirode, Ujwal R., Rajendra D. Kanphade, and Ajjay S. Gaadhe. "Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node." Key Engineering Materials 945 (May 19, 2023): 41–46. http://dx.doi.org/10.4028/p-73f387.
Full textKrishna, R., and Punithavathi Duraiswamy. "Low leakage 10T SRAM cell with improved data stability in deep sub-micron technologies." Analog Integrated Circuits and Signal Processing 109, no. 1 (May 6, 2021): 153–63. http://dx.doi.org/10.1007/s10470-021-01870-7.
Full textBansal, Saloni, and V. K. Tomar. "Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices." IOP Conference Series: Materials Science and Engineering 1116, no. 1 (April 1, 2021): 012111. http://dx.doi.org/10.1088/1757-899x/1116/1/012111.
Full textLo, Cheng-Hung, and Shi-Yu Huang. "P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation." IEEE Journal of Solid-State Circuits 46, no. 3 (March 2011): 695–704. http://dx.doi.org/10.1109/jssc.2010.2102571.
Full textFuketa, Hiroshi, Masanori Hashimoto, Yukio Mitsuyama, and Takao Onoye. "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM." IEEE Transactions on Nuclear Science 58, no. 4 (August 2011): 2097–102. http://dx.doi.org/10.1109/tns.2011.2159993.
Full textHarada, R., S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe. "Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM." IEEE Transactions on Nuclear Science 59, no. 6 (December 2012): 2791–95. http://dx.doi.org/10.1109/tns.2012.2224373.
Full textEslami, Nima, Behzad Ebrahimi, Erfan Shakouri, and Deniz Najafi. "A single-ended low leakage and low voltage 10T SRAM cell with high yield." Analog Integrated Circuits and Signal Processing 105, no. 2 (June 8, 2020): 263–74. http://dx.doi.org/10.1007/s10470-020-01669-y.
Full textSheu, Ming-Hwa, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, and Jin-Fa Lin. "A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications." Sensors 21, no. 19 (October 2, 2021): 6591. http://dx.doi.org/10.3390/s21196591.
Full textSHIBATA, Nobutaro, Yoshinori GOTOH, and Takako ISHIHARA. "A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications." IEICE Transactions on Electronics E99.C, no. 6 (2016): 717–26. http://dx.doi.org/10.1587/transele.e99.c.717.
Full textUpadhyay, Prashant, Rajib Kar, Durbadal Mandal, and Sakti Prasad Ghoshal. "Characteristic analysis of a novel low power 10T SRAM cell during read and write operations." International Journal of Computer Aided Engineering and Technology 7, no. 4 (2015): 496. http://dx.doi.org/10.1504/ijcaet.2015.072603.
Full textSable, Varun, and Shyam Akashe. "Noise Voltage Apportioned a New Reliability Concern in Low Power 10T SRAM Cell Using FinFET Device." Journal of Nanoelectronics and Optoelectronics 10, no. 6 (December 1, 2015): 745–48. http://dx.doi.org/10.1166/jno.2015.1833.
Full textSable, et al., Varun. "Static Noise Margin Enhanced in FinFET Based 10T SRAM Cell at 45 nm using EDA Tool." International Journal of Computing and Digital Systemss 5, no. 6 (November 1, 2016): 451–56. http://dx.doi.org/10.12785/ijcds/050603.
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