Relevant bibliographies by topics / 10T SRAM CELL

Contents

  1. Journal articles

Academic literature on the topic '10T SRAM CELL'

Author: Grafiati
Published: 11 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic '10T SRAM CELL.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "10T SRAM CELL"

1

Elangovan, M., and K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 10 (2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.

Full text
Abstract:
The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.
APA, Harvard, Vancouver, ISO, and other styles
2

Reddy Gujjula, Nagarjuna, and Rameshbabu Kellampalli. "Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor." International Journal of Scientific Methods in Engineering and Management 01, no. 01 (2023): 47–57. http://dx.doi.org/10.58599/ijsmem.2023.1105.

Full text
Abstract:
SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.
APA, Harvard, Vancouver, ISO, and other styles
3

Ganesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.

Full text
Abstract:
This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.
APA, Harvard, Vancouver, ISO, and other styles
4

Rao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, et al. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications." Journal of Electrical and Computer Engineering 2023 (June 7, 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.

Full text
Abstract:
Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.
APA, Harvard, Vancouver, ISO, and other styles
5

Islam, A., and M. Hasan. "Leakage Characterization of 10T SRAM Cell." IEEE Transactions on Electron Devices 59, no. 3 (2012): 631–38. http://dx.doi.org/10.1109/ted.2011.2181387.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Chaurasia, Ranu, Brijesh Kumar, Sudhanshu Verma, and Akhilesh Kumar. "Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques." IOP Conference Series: Materials Science and Engineering 1272, no. 1 (2022): 012007. http://dx.doi.org/10.1088/1757-899x/1272/1/012007.

Full text
Abstract:
This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.
APA, Harvard, Vancouver, ISO, and other styles
7

Liu, Changjun, Hongxia Liu, and Jianye Yang. "A Novel Low-Power and Soft Error Recovery 10T SRAM Cell." Micromachines 14, no. 4 (2023): 845. http://dx.doi.org/10.3390/mi14040845.

Full text
Abstract:
In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the ‘0’ storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit.
APA, Harvard, Vancouver, ISO, and other styles
8

Zhou, Hong Gang, Qiang Song, Chun Yu Peng, and Shou Biao Tan. "A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture." Applied Mechanics and Materials 263-266 (December 2012): 9–14. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.9.

Full text
Abstract:
A new 10T SRAM cell is proposed in this paper for simultaneously addressing the half select problem and improving the read/write stability. Without the half select condition, the proposed 10T cell allows efficient bit-interleaving to provide soft error rate protection and the dynamic power is also decreased significantly due to the reduction in the number of bitlines discharged and charged during the read and write operation. In the new 10T SRAM cell, one side of the cross-coupled inverters cuts off the pull up path or pull down path through adding two gated transistors according to the write ‘0’ or ‘1’ operation. It brings a great improvement for write stability without considering the half select disturb during the write operation. The simulation results indicate that the RSNM and WM of the proposed SRAM cell are enhanced by 130% and 58%, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology.
APA, Harvard, Vancouver, ISO, and other styles
9

Singh, Arjun, and Sangeeta Nakhte. "Optimized High Performance 10T SRAM Cell Characterization." International Journal of Computer Applications 134, no. 5 (2016): 29–33. http://dx.doi.org/10.5120/ijca2016907964.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Gupta, Neha, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl, and Patrick Girard. "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications." Electronics 10, no. 14 (2021): 1718. http://dx.doi.org/10.3390/electronics10141718.

Full text
Abstract:
This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.
APA, Harvard, Vancouver, ISO, and other styles
More sources
You might also be interested in the extended bibliographies on the topic '10T SRAM CELL' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography