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Journal articles on the topic 'Μm TSMC'

Author: Grafiati

Published: 28 June 2021

Last updated: 9 February 2022

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1

CHENG, KUO-HSING, SHUN-WEN CHENG, and WEN-SHIUAN LEE. "64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS." Journal of Circuits, Systems and Computers 15, no. 01 (February 2006): 13–27. http://dx.doi.org/10.1142/s0218126606002915.

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This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

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2

Shokrani, Mohammad Reza, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie. "An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/963709.

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This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

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3

Pandey, Neeta, and Rajeshwari Pandey. "Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA." Active and Passive Electronic Components 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/967057.

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This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

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4

Li, Zhi Yuan, and Xiang Ning Fan. "Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process." Applied Mechanics and Materials 364 (August 2013): 429–33. http://dx.doi.org/10.4028/www.scientific.net/amm.364.429.

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The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.

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5

Wang, Bin, and Qing Sheng Hu. "A High-Speed 64b/66b Decoder Used in SerDes." Applied Mechanics and Materials 556-562 (May 2014): 1549–52. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1549.

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A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.

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6

Yu, Zhou, Xiang Ning Fan, Zai Jun Hua, and Chen Xu. "Design of a 0.7~2.6GHz Wideband Power Amplifier in 0.18-μm CMOS Process." Applied Mechanics and Materials 618 (August 2014): 543–47. http://dx.doi.org/10.4028/www.scientific.net/amm.618.543.

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A power amplifier (PA) for multi-mode multi-standard transceiver which is implemented in a TSMC 0.18μm process is presented. The proposed PA uses matching compensation, lossy matching network and negative feedback technique to improve bandwidth. To achieve the linearity performance, the two-stage PA operates in Class-A regime. Simulation results show that the power amplifier achieves maximum output power of more than 24dBm in 0.7~2.6GHz. The output P1dBof the PA is larger than 22dBm. The simulated power gain is more than 27dB. The S11 is less than-10dB and the S22 is under-5dB.

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7

Lee, Chae-Eun, Younginha Jung, and Yoon-Kyu Song. "8-Channel Biphasic Current Stimulator Optimized for Retinal Prostheses." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4298–302. http://dx.doi.org/10.1166/jnn.2021.19405.

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Retinal prostheses substitute the functionality of damaged photoreceptors by electrically stimulating retinal ganglion cells (RGCs). RGCs, densely packed in a small region, needs a high spatial resolution of the microelectrode, which in turn raises its impedance. Therefore, the high output impedance circuit and the high compliance output voltage are the key characteristics of the current-source-based stimulator. Also, as the system is intended to implant in the retina, the stimulation parameter should be optimized for efficiency and safety. Here we designed 8-channel neural stimulator customized to the retinal ganglion cell. Designed IC is fabricated in the TSMC 0.18 μm 1P6M RF CMOS process with 3.3 V supply voltage, occupying the 1060 μm×950 μm area.

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8

Mohan, Jitendra, and Sudhanshu Maheshwari. "Cascadable Current-Mode First-Order All-Pass Filter Based on Minimal Components." Scientific World Journal 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/859784.

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A novel current-mode first-order all-pass filter with low input and high output impedance feature is presented. The circuit realization employs a single dual-X-second-generation current conveyor, one grounded capacitor, and one grounded resistor, which is a minimum component realization. The theoretical results are verified using PSPICE simulation program with TSMC 0.35 μm CMOS process parameters.

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9

Bouzerara, Lyes, and Mohand Belaroussi. "Current mode approach: High performance 0.35 μm CMOS class AB push-pull current amplifier." Facta universitatis - series: Electronics and Energetics 16, no. 2 (2003): 195–204. http://dx.doi.org/10.2298/fuee0302195b.

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A very high bandwidth class AB (Push-Pull) current amplifier using the compensation resistor technique is presented and analyzed. Such technique stands as a powerful method of bandwidth enhancement for general circuits using CMOS current mirrors. The proposed bandwidth is enhanced from 675 MHz for the uncompensated current amplifier to 745MHz for the compensated one without affecting the current gain and other design parameters such as power consumption and output swing. The circuit exhibits a current gain of 20 dB and consumes 1.48 mW for ?2.5V power supply voltage. All simulation results were performed using Hspice tool with 0.35^m CMOS TSMC parameters.

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10

FAN, CHIH-PENG, and CHIA-HAO FANG. "LOW-POWER INSTRUCTION ADDRESS BUS CODING WITH XOR–BITS ARCHITECTURE." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 45–57. http://dx.doi.org/10.1142/s0218126609004910.

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In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR–BITS) code. The XOR–BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR–BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 μm CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 μm CMOS technology.

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11

ZHU, ZHANGMING, HONGBING WU, GUANGWEN YU, YANHONG LI, LIANXI LIU, and YINTANG YANG. "A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350018. http://dx.doi.org/10.1142/s0218126613500187.

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A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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12

Pandey, Neeta, Aseem Sayal, Richa Choudhary, and Rajeshwari Pandey. "Design of CDTA and VDTA Based Frequency Agile Filters." Advances in Electronics 2014 (December 23, 2014): 1–15. http://dx.doi.org/10.1155/2014/176243.

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This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.

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13

Pandey, Neeta, Sakshi Arora, Rinku Takkar, and Rajeshwari Pandey. "DVCCCTA-Based Implementation of Mutually Coupled Circuit." ISRN Electronics 2012 (September 24, 2012): 1–6. http://dx.doi.org/10.5402/2012/303191.

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This paper presents implementation of mutually coupled circuit using differential voltage current-controlled conveyor transconductance amplifier (DVCCCTA). It employs only two DVCCCTAs, one grounded resistor, and two grounded capacitors. The primary, secondary, and mutual inductances of the circuit can be independently controlled and tuned electronically. The effect of non-ideal behaviour of DVCCCTA on the proposed circuit is analyzed. The functionality of the proposed circuit is verified through SPICE simulation using 0.25 μm TSMC CMOS technology parameters.

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14

ZHU, ZHANGMING, YU XIAO, LIANG LIANG, LIANXI LIU, and YINTANG YANG. "A 3.03 μW 10-BIT 200 KS/s SAR ADC IN 0.18 μM CMOS." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350026. http://dx.doi.org/10.1142/s0218126613500266.

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Based on TSMC 0.18 μm 1.8 V CMOS process, a low power 10-bit 200 KS/s successive approximation register (SAR) analog-to-digital (ADC) is realized. This paper mainly considers the improvement of linearity and the optimization of power consumption. And a novel switching sequence is proposed which allows both to achieve a better compromise. Moreover, the fully dynamic comparator, which consumes no static power, and the optimization of SAR control logic, further reduce power consumption. The simulation results show that at 1.0 V supply and 200 KS/s, the ADC achieves an signal-to-noise and distortion-ration (SNDR) of 59.78 dB and consumes 3.03 μW, resulting in a figure-of-merit (FOM) of 19.0 fJ/conversion-step. The ADC core occupies an active area of only 260 × 220 μm2.

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15

Pandey, Neeta, and Sajal K. Paul. "VM and CM Universal Filters Based on Single DVCCTA." Active and Passive Electronic Components 2011 (2011): 1–7. http://dx.doi.org/10.1155/2011/929507.

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A universal voltage-mode filter (VM) and a current-mode filter (CM) based on recently proposed active building block, namely, differential voltage current conveyor transconductance amplifier (DVCCTA) are proposed. Both the circuits use a single DVCCTA, two capacitors, and a single resistor. The filters enjoy low-sensitivity performance and low component spread and exhibit electronic tunability of filter parameters via bias currents of DVCCTA. SPICE simulation using 0.25 μm TSMC CMOS technology parameters is included to show the workability of the proposed circuits.

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16

YUCE, ERKAN, KIRAT PAL, and SHAHRAM MINAEI. "A HIGH INPUT IMPEDANCE VOLTAGE-MODE ALL-PASS/NOTCH FILTER USING A SINGLE VARIABLE GAIN CURRENT CONVEYOR." Journal of Circuits, Systems and Computers 17, no. 05 (October 2008): 827–34. http://dx.doi.org/10.1142/s0218126608004733.

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In this paper, a novel circuit for realizing voltage-mode first-order and second-order all-pass filter responses as well as second-order notch filter response depending on the passive component choice, is presented. This circuit has high input impedance; thus, it is easy to cascade the introduced filter with other voltage-mode topologies. Also, it uses a single Variable Gain Current Conveyer — VGCCII and only grounded capacitors. SPICE simulation results based on 0.35 μm TSMC CMOS technology parameters are given to confirm the theory.

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17

Chu, Hung-Chi, Jin-Fa Lin, and Dong-Ting Hu. "Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications." ISRN Electronics 2013 (May 25, 2013): 1–4. http://dx.doi.org/10.1155/2013/187127.

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A low complexity dual-mode pulse-triggered FF design for wireless baseband processing is presented in this paper. It supports both single-edge- and double-edge-triggered operations subject to a mode select control. Due to the novelty in pulse generator design, the layout area overhead is only 8% when compared with other single-mode counterpart design. Postlayout simulations in TSMC 1P6M 0.18 μm CMOS process model also indicate that the proposed design is as efficient as its single-mode counterpart in various performance metrics.

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Wei, Hung Che, and Chih Lung Hsiao. "A Low Power CMOS Bulk-Controlled Sub-Harmonic Mixer for LTE-Advanced Applications." Applied Mechanics and Materials 284-287 (January 2013): 2423–27. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2423.

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In this paper, a 3.5 GHz CMOS sub-harmonic mixer for LTE-advanced applications is presented. The mixer with the bulk-controlled technique improves the linearity and mitigates the power of the local oscillator. The proposed mixer is implemented by tsmc 0.18 μm Mixed Signal RF CMOS 1P6M process and consumes 2.2 mA from a 1.2 V supply. The proposed mixer operates at 3.5GHz LTE-advanced bands and achieves maximum input third-order intercept point (IIP3) of 2.3dBm, power conversion gains of 1.3 dB.

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19

ESMAILI, ARASH, HADISEH BABAZADEH, KHAYROLLAH HADIDI, and ABDOLLAH KHOEI. "A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER." Journal of Circuits, Systems and Computers 23, no. 06 (May 14, 2014): 1450090. http://dx.doi.org/10.1142/s021812661450090x.

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A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

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20

Pandey, Neeta, and Sajal K. Paul. "Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing." Journal of Electrical and Computer Engineering 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/361384.

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A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25 μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.

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21

MAHMOUD, SOLIMAN A. "LOW POWER LOW-PASS FILTER WITH PROGRAMMABLE CUTOFF FREQUENCY BASED ON A TUNABLE UNITY GAIN FREQUENCY OPERATIONAL AMPLIFIER." Journal of Circuits, Systems and Computers 19, no. 08 (December 2010): 1651–63. http://dx.doi.org/10.1142/s0218126610006979.

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In this paper, a sixth-order reconfigurable low pass filter (LPF) is realized using 0.25 μm TSMC CMOS technology. The filter is based on a cascading connection of bi-quadratic active-Gm-RC cells. The active-Gm-RC cells are realized using compensated op-amps with variable transconductance gain and variable compensation capacitors (variable Gm–Cc op-amp). The tuning range of the filter's cutoff frequency is from 77.4 KHz to 37.78 MHz. The filter operates from a single supply of 1.5 V. Simulations results using PSPICE for the proposed reconfigurable LPF are presented.

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22

Fathi, Amir, Abdollah Khoei, and Khayrollah Hadidi. "High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550048. http://dx.doi.org/10.1142/s0218126615500486.

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This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

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23

Jang, Sheng-Lyang, and Tsung-Chao Fu. "Effects of Hot-Carrier Stress on the RF Performance of a 0.18-μm MOS Divide-by-4 LC Injection-Locked Frequency Divider." Fluctuation and Noise Letters 13, no. 02 (June 2014): 1450009. http://dx.doi.org/10.1142/s0219477514500096.

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The effect of ac hot-carrier stress on the performance of a wide locking range divide-by-4 injection-locked frequency divider (ILFD) is investigated. The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the resonators. Radio frequency (RF) circuit parameters such as oscillation frequency, tuning range, phase noise, and locking range before and after RF stress at an elevated supply voltage for 5 h have been examined by experiment. The measured locking range, operation range and phase noise after RF stress shows significant degradation from the fresh circuit condition.

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24

Gupta, Kirti, Neeta Pandey, and Maneesha Gupta. "Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits." ISRN Electronics 2012 (December 5, 2012): 1–7. http://dx.doi.org/10.5402/2012/529194.

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Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.

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25

YEH, MEI-LING, YAO-CHIAN LIN, and CHUNG-CHENG CHANG. "A LOW-PHASE-NOISE CMOS VCO FOR K-BAND APPLICATION." Journal of Circuits, Systems and Computers 22, no. 06 (July 2013): 1350040. http://dx.doi.org/10.1142/s0218126613500400.

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A new high figure-of-merit (FOM) and low-phase-noise 20.73-GHz voltage-controlled oscillator is designed for K-band applications in this paper. The capacitive feedback technique is used for the low-phase-noise VCO design. The VCO can be tuned from 20.817 GHz to 20.266 GHz. The measured phase noise is -115.57 dBc/Hz at 1 MHz offset from the carrier frequency. The corresponding FOM is calculated to be -190 dBc/Hz. The VCO is implemented with the TSMC 0.18 μm one-poly-six-metal 1.7 V mixed-signal/RF CMOS technology, and the chip size is 0.51 × 0.74 mm2.

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ZHU, ZHANGMING, WEITIE WANG, YUHENG GUAN, SHUBIN LIU, YU XIAO, LIANXI LIU, and YINTANG YANG. "A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC." Journal of Circuits, Systems and Computers 22, no. 07 (August 2013): 1350061. http://dx.doi.org/10.1142/s0218126613500618.

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A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

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Pandey, Rajeshwari, Neeta Pandey, and Navin Singhal. "Single VDTA Based Dual Mode Single Input Multioutput Biquad Filter." Journal of Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/1674343.

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This paper presents a dual mode, single input multioutput (SIMO) biquad filter configuration using single voltage differencing transconductance amplifier (VDTA), three capacitors, and a grounded resistor. The proposed topology can be used to synthesize low pass (LP), high pass (HP), and band pass (BP) filter functions. It can be configured as voltage mode (VM) or current mode (CM) structure with appropriate input excitation choice. The angular frequency (ω0) of the proposed structure can be controlled independently of quality factor (Q0). Workability of the proposed biquad configuration is demonstrated through PSPICE simulations using 0.18 μm TSMC CMOS process parameters.

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Pandey, Neeta, and Sajal K. Paul. "Single CDTA-Based Current Mode All-Pass Filter and Its Applications." Journal of Electrical and Computer Engineering 2011 (2011): 1–5. http://dx.doi.org/10.1155/2011/897631.

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This paper presents a single current difference transconductance amplifier (CDTA) based all-pass current mode filter. The proposed configuration makes use of a grounded capacitor which makes it suitable for IC implementation. Its input impedance is low and output impedance is high, hence suitable for cascading. The circuit does not use any matching constraint. The nonideality analysis of the circuit is also given. Two applications, namely, a quadrature oscillator and a highQband pass filter are developed with the proposed circuit. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

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Prasad, Dinesh, Mayank Srivastava, and D. R. Bhaskar. "Transadmittance Type Universal Current-Mode Biquad Filter Using VDTAs." International Scholarly Research Notices 2014 (August 19, 2014): 1–4. http://dx.doi.org/10.1155/2014/762845.

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A new resistorless single-input-multi-output (SIMO) universal transadmittance (TA) type filter employing two voltage differencing transconductance amplifiers (VDTA) and two grounded capacitors is proposed. The proposed topology realizes simultaneously low pass (LP), high pass (HP), and band pass (BP) filter functions. Band rejects (BR) and all pass (AP) filters are also realizable through appropriate connections of currents. The proposed configuration also offers independent control of natural angular frequency (ω0) and bandwidth (BW) and low active and passive sensitivities. The workability of proposed configuration has been demonstrated through PSPICE simulations with TSMC CMOS 0.18 μm process parameters.

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Heidari Jobaneh, Hemad. "The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology." Active and Passive Electronic Components 2020 (March 30, 2020): 1–12. http://dx.doi.org/10.1155/2020/8537405.

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The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.

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31

Valenzuela, Wladimir, Javier E. Soto, Payman Zarkesh-Ha, and Miguel Figueroa. "Face Recognition on a Smart Image Sensor Using Local Gradients." Sensors 21, no. 9 (April 21, 2021): 2901. http://dx.doi.org/10.3390/s21092901.

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In this paper, we present the architecture of a smart imaging sensor (SIS) for face recognition, based on a custom-design smart pixel capable of computing local spatial gradients in the analog domain, and a digital coprocessor that performs image classification. The SIS uses spatial gradients to compute a lightweight version of local binary patterns (LBP), which we term ringed LBP (RLBP). Our face recognition method, which is based on Ahonen’s algorithm, operates in three stages: (1) it extracts local image features using RLBP, (2) it computes a feature vector using RLBP histograms, (3) it projects the vector onto a subspace that maximizes class separation and classifies the image using a nearest neighbor criterion. We designed the smart pixel using the TSMC 0.35 μm mixed-signal CMOS process, and evaluated its performance using postlayout parasitic extraction. We also designed and implemented the digital coprocessor on a Xilinx XC7Z020 field-programmable gate array. The smart pixel achieves a fill factor of 34% on the 0.35 μm process and 76% on a 0.18 μm process with 32 μm × 32 μm pixels. The pixel array operates at up to 556 frames per second. The digital coprocessor achieves 96.5% classification accuracy on a database of infrared face images, can classify a 150×80-pixel image in 94 μs, and consumes 71 mW of power.

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Ma, Peng, and Xiang Ning Fan. "A Wideband 9 GHz LC-VCO with Tail Current Source Array in 0.18-μm RF CMOS Process." Applied Mechanics and Materials 364 (August 2013): 434–38. http://dx.doi.org/10.4028/www.scientific.net/amm.364.434.

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A wideband 9 GHz LC-VCO with tail current source array based on TSMC 0.18-μm RF CMOS process is presented in this paper. After discussing the start-up conditions, the structure of tail current source array is utilized to lower the power consumption in high frequency bands and guarantee start-up at low frequency bands. Furthermore, to extend the frequency range, a 4-bit switched capacitor array is used. Based on our analysis, a NMOS cross-coupled VCO with 4-bit PMOS tail current source array is implemented. Post-simulation results show that the tuning range is from 6.372GHz to 9.154GHz and the phase noise at 1MHz offset is less than-110dBc/Hz in the entire tuning range. The operating current of the VCO core is from 8.24mA to 13.362mA in the entire tuning range under 1.8V supply voltage. And the area of the proposed VCO is 1177.775μm × 577.54μm, with two buffer stages and pads.

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Srivastava, Richa, Maneesha Gupta, and Urvashi Singh. "Fully Programmable Gaussian Function Generator Using Floating Gate MOS Transistor." ISRN Electronics 2012 (November 20, 2012): 1–5. http://dx.doi.org/10.5402/2012/148492.

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Floating gate MOS (FGMOS) based fully programmable Gaussian function generator is presented. The circuit combines the tunable property of FGMOS transistor, exponential characteristics of MOS transistor in weak inversion, and its square law characteristic in strong inversion region to implement the function. Two-quadrant current mode squarer is the core subcircuit of Gaussian function generator that helps to implement full Gaussian function for positive as well as negative input current. FGMOS implementation of the circuit reduces the current mismatching error and increases the tunability of the circuit. The performance of circuit is verified at 1.8 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

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Han, Tsung Han, Meng Ting Hsu, and Cheng Chuan Chung. "Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits." Applied Mechanics and Materials 479-480 (December 2013): 1010–13. http://dx.doi.org/10.4028/www.scientific.net/amm.479-480.1010.

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In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

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ÖLMEZ, SİNEM, and UĞUR ÇAM. "REALIZATION OF SQUARE ROOT DOMAIN TOW–THOMAS BIQUADRATIC FILTER." Journal of Circuits, Systems and Computers 19, no. 05 (August 2010): 1015–24. http://dx.doi.org/10.1142/s0218126610006578.

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In this paper, a Tow–Thomas biquadratic filter designed in square root domain is proposed. The presented filter is constructed with a lossy integrator, a lossless integrator, and a summer block. To the best knowledge of the authors, the filter is the first square root domain Tow–Thomas filter in the literature. The state space synthesis method is used to design the biquadratic filter. The filter operated at 2.5 V supply voltage is simulated by using SPICE simulation program with 0.25 μm TSMC CMOS model parameters. Simulation results are in good agreement with theoretical results that the cut-off frequency and quality factor of the filter are tunable electronically.

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MAHESHWARI, SUDHANSHU, JITENDRA MOHAN, and DURG SINGH CHAUHAN. "HIGH INPUT IMPEDANCE VOLTAGE-MODE UNIVERSAL FILTER AND QUADRATURE OSCILLATOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1597–607. http://dx.doi.org/10.1142/s0218126610006943.

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A new single input and five outputs high input impedance voltage-mode universal biquadratic filter using three DVCCs, five passive components is presented. The proposed circuit offers the following features: high input impedance, realization of all the standard filter functions, that is, high-pass, band-pass, low-pass, band reject and all-pass filters simultaneously, the use of grounded capacitor, orthogonal control of ω0 and Q, no need to employ inverting type input signals, and no need to impose component choice except realizing the all-pass filter signal. A new quadrature oscillator circuit is also realized. PSPICE simulations using 0.35 μm TSMC CMOS parameters confirm the validity of the proposed circuit.

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KAÇAR, FIRAT. "A NEW TUNABLE FLOATING CMOS FDNR AND ELLIPTIC FILTER APPLICATIONS." Journal of Circuits, Systems and Computers 19, no. 08 (December 2010): 1641–50. http://dx.doi.org/10.1142/s0218126610006967.

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A new tunable CMOS FDNR circuit is proposed. The circuit is based on the transcapacitive gyrator approach with both transcapacitive stages realized by MOS transistors configuration. This FDNR element lends itself well to the design of low-pass ladder filters and its use will result in a more efficient integrated circuit implementation than filters that simulate floating inductors utilizing resistive gyrators. The applications of FDNR to realize a current-mode fifth-order elliptic filter and current mode sixth-order elliptic band-pass filter are given. The proposed FDNR is simulated using CMOS TSMC 0.35 μm technology. Simulation results are given to confirm the theoretical analysis.

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TSAI, CHIA-CHUN, SHENG-BIN DAI, and TRONG-YEN LEE. "THE RF CIRCUIT DESIGN OF POWER AND DATA CONTACTLESS TRANSMISSION FOR ISO/IEC 14443-2 TYPE B." Journal of Circuits, Systems and Computers 20, no. 08 (December 2011): 1637–58. http://dx.doi.org/10.1142/s0218126611008092.

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In this paper, we design and implement an integrated circuit system for contactless interface transmission to conform the transfer protocol of ISO/IEC 14443-2 Type B. The system consists of two major parts, interrogator and transponder, for magnetic power and data transmission. The power and data can synchronously be transferred from the interrogator to the transponder with 10% amplitude shift keying modulation of mixing both carrier 13.56 MHz and data rate 106 Kbps. Another data can be backward to the interrogator from the transponder with the mixed binary phase shift keying modulation. Simulation results to the whole chip based on TSMC 0.35 μm CMOS process have approved using HSPICE.

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HORNG, JIUN-WEI, TO-YAO CHIU, CHING-PAO HSIAO, and GUANG-TING HUANG. "THREE-INPUTS-ONE-OUTPUT CURRENT-MODE UNIVERSAL BIQUAD USING TWO CURRENT CONVEYORS." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340001. http://dx.doi.org/10.1142/s021812661340001x.

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A current-mode universal biquadratic filter with three input terminals and one output terminal is presented. The architecture uses two current conveyors (CCs), two grounded capacitors and two grounded resistors; and can realize all standard second-order filter functions — highpass, bandpass, lowpass, notch and allpass. Moreover, the circuit still offers the following advantage features: very low active and passive sensitivities, using of grounded capacitors and resistors which is ideal for integrated circuit implementation, without requirements for critical component matching conditions and very high output impedance. The workability of the proposed circuit has been verified via HSPICE simulations using TSMC 0.18 μm, level 49 MOSFET technology.

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Tangsrirat, Worapong. "Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier." Scientific World Journal 2013 (2013): 1–8. http://dx.doi.org/10.1155/2013/201565.

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This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells (Gms) as core circuits. The advantage of this element is that the current transfer ratios (iz/ipandix/iz) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated.

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Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.

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Kushwaha, Ajay K., Ashok Kumar, and Prakash Pareek. "Current Mode and Voltage Mode Third Order Sinusoidal Oscillator Using CCDDCCTA." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 486–92. http://dx.doi.org/10.2174/2210681209666190820102339.

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Objective: In this paper, a novel third order sinusoidal oscillator based on current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA) is proposed. Methods: The proposed circuit configuration consist of single CCDDCCTA, two grounded resistor and three capacitors. It can concurrently yield output voltage and current. The amplitude of output current can be easily tuned by the bias current. The non-ideality and Monte-Carlo analysis are discussed and presented. Results: The stated results agree well with the theoretical estimation. Conclusion: The performance ofa proposed oscillator are analyzed with ORCAD 16.6 simulator and the analog block has been depicted using 0.25 μm CMOS TSMC technology parameters.

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Lei, Zhu, Ying Mei Chen, Ling Tian, and Li Zhang. "A 10Gb/s Low-Power Front-End Amplifier for Optical Receiver in 0.18μm CMOS Technology." Advanced Materials Research 588-589 (November 2012): 872–75. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.872.

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A Front-End Amplifier for the STM-64(10Gb/s) optical receiver in SDH system has been proposed in TSMC 0.18 μm CMOS technology. The common-gate feedforward configuration with an active inductor is employed in the input stage of transimpedance amplifier to increase the bandwidth. A 3-order interleaving active feedback configuration is employed to expand the bandwidth in the gain stage of transimpedance amplifier and limiting amplifier. Simulation results show that the output swing is 190mV (Vpp) when the input current varies from 20μA to 400μA. The power consumption is only 98.2mW with 1.8V power supply and the chip area is 496μm×480μm.

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Zhang, Yi, Qiao Meng, Changchun Zhang, Ying Zhang, Yufeng Guo, Youtao Zhang, Xiaopeng Li, and Lei Yang. "A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology." Journal of Sensors 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/3984526.

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A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

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Farah, Fouad, Mustapha El Alaoui, Abdelali El Boutahiri, Mounir Ouremchi, Karim El Khadiri, Ahmed Tahiri, and Hassan Qjidaa. "High Efficiency Buck-Boost Converter with Three Modes Selection for HV Applications using 0.18 μm Technology." ECTI Transactions on Electrical Engineering, Electronics, and Communications 18, no. 2 (August 31, 2020): 137–44. http://dx.doi.org/10.37936/ecti-eec.2020182.222580.

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In this paper, we aim to make a detailed study on the evaluation and the characteristics of the non-inverting buck–boost converter. In order to improve the behaviour of the buck-boost converter for the three operating modes, we propose an architecture based on peak current-control. Using a three modes selection circuit and a soft start circuit, this converter is able to expand the power conversion efficiency and reduce inrush current at the feedback loop. The proposed converter is designed to operate with a variable output voltage. In addition, we use LDMOS transistors with low on-resistance, which are adequate for HV applications. The obtained results show that the proposed buck-boost converter perform perfectly compared to others architecture and it is successfully implemented using 0.18 μm CMOS TSMC technology, with an output voltage regulated to 12V and input voltage range of 4-20 V. The power conversion efficiency for the three operating modes buck, boost and buck-boost are 97.6%, 96.3% and 95.5% respectively at load current of 4A.

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Mačaitis, Vytautas, and Vaidotas Barzdėnas. "DESIGN AND INVESTIGATION OF 65 NM RF CMOS TECHNOLOGY LC-VCO’S / AUKŠTADAŽNIŲ, 65 NM KMOP TECHNOLOGIJOS, LC ĮTAMPA VALDOMŲ GENERATORIŲ PROJEKTAVIMAS IR TYRIMAS." Mokslas – Lietuvos ateitis 6, no. 2 (April 24, 2014): 198–201. http://dx.doi.org/10.3846/mla.2014.29.

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In this paper, two LC Voltage-Controlled Oscillators (LC-LC-VCO1 and LC-VCO2) are designed using TSMC 65 nm LP/MS/RF CMOS technology. Two arrays, one of which is a 6-bit capacitor array and the other – an array of MOS varactors, provide a wide LC-VCO frequency tuning range. Post-layout simulation results unveiled that at 1.8 V supply voltage the tuning range of LC-VCO1 spans from 5.17 GHz to 6.76 GHz and for LC-VCO2 the range spans from 6.33 GHz to 8.08 GHz. The phase noise at 1 MHz offset frequency is about −123.1 dBc/Hz for LC-VCO1 and −121.6 dBc/Hz for LC-VCO2. The power dissipation at maximum carrier is 30.47 mW for LC-VCO1 and 30.5 mW for LC-VCO2. The layout area is 285×335 μm and 255×305 μm, respectively for LC-VCO1 and LC-VCO2. Straipsnyje nagrinėjami ir projektuojami LC įtampa valdomi generatoriai (LC-ĮVG), plačiai taikomi šiuolaikiniuose daugiastandarčiuose ir daugiajuosčiuose siųstuvuose-imtuvuose. Naudojant TSMC kompanijos 65 nm LP/MS/RF KMOP integrinių grandynų gamybos technologiją suprojektuoti ir išanalizuoti du skirtingų dažnio diapazonų LC-ĮVG. Generuojamas dažnis yra valdomas dviem būdais, t. y. galimas apytikslis bei tikslus dažnio nustatymas. Norint apytiksliai nustatyti dažnį naudojamas 6 bitais skaitmeniškai valdomas perjungiamų kondensatorių blokas, o norint tiksliai parinkti valdymą – NMOP varaktorių blokas. Kompiuterinio modeliavimo metu gauti tokie pagrindiniai LC-ĮVG parametrai: valdomo dažnio diapazonas – nuo 5,17 GHz iki 6,76 GHz (LC-ĮVG1) ir nuo 6,33 GHz iki 8,08 GHz (LC-ĮVG2); fazinis triukšmas, esant 1 MHz poslinkio dažniui ir maksimaliam nešlio dažniui: –123,1 dBc/Hz (LC-ĮVG1) ir –121,6 dBc/Hz (LC-ĮVG2); vartojamoji galia, esant maksimaliam nešlio dažniui: –30,47 mW (LC-ĮVG1) ir 30,5 mW (LC-ĮVG2). Suprojektuotų LC-ĮVG1 ir LC-ĮVG2 topologijų plotas yra atitinkamai lygus 0,078 mm2 ir 0,096 mm2.

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Ardali, Sadegh Raiessi, Sajad Ghatreh Samani, and Babak Arzanifar. "Oscillation Amplitude Analysis of MOS Hartley Oscillator Using a General Model." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 60–67. http://dx.doi.org/10.29292/jics.v6i1.339.

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New analytical equations for amplitude analysis of MOS Hartley oscillator are presented. Using exact large-signal circuit analysis, analytical equations for estimating the amplitude of Hartley oscillator are derived that considers all operation regions of transistor; including saturation, triode and cutoff. The analysis is based on a reasonable estimation for the output waveform. The estimated waveform should satisfy the nonlinear differential equations describing the circuit. Using this novel point, we can simply find the unknown parameters of the waveform, especially amplitude. The validity of the resulted equations is verified through simulations using TSMC 0.18 μm CMOS process. The amplitude calculated from this approach has a very good agreement with simulation for a large range of circuit parameters.

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Shi, Jiang Yi, Jie Pang, Zhi Xiong Di, Yao Hui Liu, and Yun Song Li. "High Throughput VLSI Architecture of MQ-Coder for JPEG2000." Advanced Materials Research 403-408 (November 2011): 2321–24. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.2321.

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In this paper, a design of high throughput VLSI architecture of MQ-Coder is proposed. Usually, because the regular operation of the MQ-Coder is sequential, the coding speed will be bottlenecked at the interface between the output of the Bit-Plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture can process two symbols for each clock cycle. The main characteristics are the prediction of index, the simplified condition of renormalization, and the partly parallel architecture in renormalization. From synthesis results of the DC tools, using the TSMC 0.18 μm technology library, the frequency can reach 285.4MHz, which is comparable to that of other architectures and suitable for chip implementation.

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Li, Weng Yuan, and Teng Xiao Jiang. "A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit." Applied Mechanics and Materials 513-517 (February 2014): 4555–58. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4555.

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In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

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CHANG, ROBERT C., PO-CHUNG HUNG, and HSIN-LEI LIN. "LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 15, no. 04 (August 2006): 491–504. http://dx.doi.org/10.1142/s0218126606003271.

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A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the conventional CMOS case. Operation of an 8-bit ERCPL CLA fabricated using the TSMC 0.35 μm 1P4M CMOS technology has been experimentally verified.

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