Zeitschriftenartikel: „Xilinx ISE“

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Palanisamy, R., C. S. Boopathi, K. Selvakumar und K. Vijayakumar. „Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor“. International Journal of Electrical and Computer Engineering (IJECE) 10, Nr. 2 (01.04.2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

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Palanisamy, R., und K. Vijayakumar. „Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor“. International Journal of Reconfigurable and Embedded Systems (IJRES) 8, Nr. 2 (01.07.2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

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G, Rekha, Arunkumar P. Chavan und Ravish Aradhya H. V. „Bio-Inspired Motion Detector Model Simulated on Xilinx ISE“. International Journal of Computer Applications 72, Nr. 13 (26.06.2013): 23–32. http://dx.doi.org/10.5120/12554-9129.

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SALEH, ANDHI RACHMAN, und SUNNY ARIEF SUDIRO. „CRC 8-bit Encoder-Decoder Component in FPGA using VHDL“. ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, Nr. 1 (31.01.2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i

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., Swati Sharma. „DESIGNING OF CORDIC PROCESSOR IN VERILOG USING XILINX ISE SIMULATOR“. International Journal of Research in Engineering and Technology 03, Nr. 05 (25.05.2014): 342–49. http://dx.doi.org/10.15623/ijret.2014.0305064.

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Chetia, Rajib. „Behavioral Design and Synthesis of 64 BIT ALU using Xilinx ISE“. IOSR Journal of Electronics and Communication Engineering 7, Nr. 4 (2013): 37–41. http://dx.doi.org/10.9790/2834-0743741.

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Abdulraheem Fadhel, Mohammed, Omran Al-Shamaa und Bahaa Husain Taher. „Real-Time detection and tracking moving vehicles for video surveillance systems using FPGA“. International Journal of Engineering & Technology 7, Nr. 2.31 (29.05.2018): 117. http://dx.doi.org/10.14419/ijet.v7i2.31.13422.

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With the growth of the electronic and communication devices, computer vision has become an significant application of smart cities. A smart city is controlled by smart autonomous systems. Many algorithms have been developed to satisfy these smart cities. This paper concerned with addressing the moving objects (vehicles) by using morphological techniques. For computational cheapness. The simulation has been built by a MATLAB 2012a and its implementation was done using Xilinx-ISE 14.6 (2013) XC3S700A-FPGA board that provides an exceptional tool for mixing between two platforms, the ISE 14.6(2013) and the MATLAB (2012a) platforms. MATLAB provides components for FPGA that invoke Verilog code of Xilinx platform, to avoid the size weakness of XC3S700A-FPGA board.

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Muslim, Imaduddin Amrullah, R. Rizal Isnanto und Eko Didik Widianto. „Perancangan dan Implementasi Algoritma DES untuk Mikroprosesor Enkripsi dan Dekripsi pada FPGA“. Jurnal Teknologi dan Sistem Komputer 3, Nr. 2 (20.04.2015): 259. http://dx.doi.org/10.14710/jtsiskom.3.2.2015.259-266.

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Seiring dengan semakin luasnya penerapan teknologi komputasi di sekitar kita, menjadikan informasi menjadi sangat mudah dan cepat untuk disebarkan. Kita dapat mengakses informasi dan data-data yang kita butuhkan dengan mudah. Namun permasalahan yang kita hadapi saat ini kerhasiaan informasi menjadi sangat riskan. Oleh karena itu Sistem keamanan merupakan hal penting yang perlu diperhatikan dalam mengembangkan suatu sistem komputer hal ini lah yang menjadikan enkripsi dan dekripsi data menjadi hal yang penting. Modul rancangan IP Core ini dirancang menggunakan aplikasi Xilinx ISE Design Suite 12.4. Kemudian rancangan IP Core ini diimplementasikan pada papan Xilinx FPGA Spartan-3E XC3S500E-4FG320C dari keluarga Xilinx FPGA Spartan-3E dengan 500K sistem gerbang. Verifikasi fungsional dari IP Core yang dirancang menggunakan testbench dan simulasi diagram pewaktuan menggunakan aplikasi Xilinx ISE Simulator. Tugas akhir ini ditujukan untuk mengembangkan IP Core yang mampu menjalankan fungsi enkripsi DES (Data Encryption Standard) dan ditulis menggunakan bahasa Verilog. Implementasi algoritma enkripsi dan dekripsi algoritma DES telah berhasil dilakukan. Hasil analisis menunjukkan sistem telah dapat melakukan enkripsi dan dekripsi data sesuai dengan spesifikasi algoritma DES. Sebaiknya penelitian ini dikembangkan kembali dengan menguji sistem untuk melakukan transmisi data berupa file ataupun teks. Selain itu juga perlu meningkatkan unjuk kerja sistem dengan optimasi sumber daya dan kecepatan waktu proses pada perancangan rekonstruksi kode verilog.

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Kamar, Sara, Abdelmoniem Fouda, Abdelhalim Zekry und Abdelmoniem Elmahdy. „FPGA implementation of RS codec with interleaver in DVB-T using VHDL“. International Journal of Engineering & Technology 6, Nr. 4 (28.11.2017): 171. http://dx.doi.org/10.14419/ijet.v6i4.8205.

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Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.This paper presents VHDL program for Reed-Solomoncodec (204, 188) and convolutional interleaver/deinterleaver, used in Digital Video Broadcasting-terrestrial system (DVB-T), according to ETSI EN 300 744 V1.5.1 standard. The VHDL programs are implemented on Xilinx 12.3 ISE and then simulated and tested via ISE simulator then the code is synthesized on FPGA device the results are compared with IP core for Xilinx 12.3 ISE, which gives the same results.

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rani, Archana, und Naresh Grover. „Area & Power Optimization of Asynchronous Processor Using Xilinx ISE & Vivado“. International Journal of Information Engineering and Electronic Business 10, Nr. 4 (08.07.2018): 8–15. http://dx.doi.org/10.5815/ijieeb.2018.04.02.

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Kaur, Harkinder. „Design and Performance Analysis of RAM_WR_ Control Module using Xilinx ISE 14.2“. Indian Journal of Science and Technology 9, Nr. 1 (20.01.2016): 1–5. http://dx.doi.org/10.17485/ijst/2016/v9i46/106915.

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Alidoust Aghdam, Farid, und Siamak Saeidi Haghi. „Implementation of High Performance Microstepping Driver Using FPGA with the Aim of Realizing Accurate Control on a Linear Motion System“. Chinese Journal of Engineering 2013 (18.12.2013): 1–8. http://dx.doi.org/10.1155/2013/425093.

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This paper presents an FPGA-based microstepping driver which drives a linear motion system with a smooth and precise way. Proposed driver built on a Spartan3 FPGA (XC3S400 core) development board from Xilinx. Implementation of driver realized by an FPGA and using Verilog hardware description language in the Xilinx ISE environment. The driver’s control behavior can be adapted just by altering Verilog scripts. In addition, a linear motion system developed (with 4 mm movement per motor revolution) and coupled it to the stepper motor. The performance of the driver is tested by measuring the distance traveled on linear motion system. The experimental results verified using hardware-in-loop Matlab and Xilinx cosimulation method. This driver accomplishes a firm and accurate control and is responsive.

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Kadam, Sarika, und S. D. Mali. „DESIGN OF RISC PROCESSOR USING VHDL“. International Journal of Research -GRANTHAALAYAH 4, Nr. 6 (30.06.2016): 131–38. http://dx.doi.org/10.29121/granthaalayah.v4.i6.2016.2646.

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The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan-3A XC3S50A XILINX Tool.

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M S, Harish M. S., und Jayadevappa D. „Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog“. International Journal of Engineering & Technology 7, Nr. 4.36 (09.12.2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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M S, Harish M. S., und Jayadevappa D. „Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog“. International Journal of Engineering & Technology 7, Nr. 4.36 (09.12.2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23810.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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Mahmoud, Mohamed Ibrahim, Sayed Mohamed El-Araby, Safey Ahmed Shehata, Refaat Mohamed Fikry AbouZaid und Fathi Abd El-Samie. „Design and Implementation of a Fast General Purpose Fuzzy Processor“. International Journal of System Dynamics Applications 2, Nr. 4 (Oktober 2013): 1–18. http://dx.doi.org/10.4018/ijsda.2013100101.

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In this paper, a Fast Fuzzy processor (FP) is proposed. This processor, which is implemented using FPGA, has four inputs and one output with 8-bits width for each. The proposed processor is synthesized, functionally verified and implemented using Xilinx Integrated Software Environment (ISE) and is tested using Xilinx Spartan 3E starter kit. A PC Graphical User Interface (GUI) is programmed using C# programming language to select and download the parameters of the processor through the serial port communication. The proposed processor is experimentally tested through water sprinkler system example. The experimental results approve the excellent performance of the proposed processor.

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Prayitno, Ragiel Hadi, Ary Bima Kurniawan und Antonius Irianto. „PERANCANGAN ANTARMUKA PENGENALAN OBJEK MENGGUNAKAN PERANGKAT LUNAK XILINX ISE DESIGN SUITE VERSI 14.5“. SENSI Journal 4, Nr. 1 (01.02.2018): 120–29. http://dx.doi.org/10.33050/sensi.v4i1.719.

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Pengenalan citra (Image Recognition) banyak digunakan dalam berbagai hal, baik dalam bidang industri, kedokteran, keamanan dan lain sebagainya. Pengenalan citra/objek memiliki tingkat kebutuhan yang besar. Penerapan antarmuka ini memerlukan sistem yang mempunyai kecepatan yang tinggi dalam prosesnya. Namun dalam penerapan antarmukanya sistem berbasis perangkat keras memiliki kecepatan proses yang lebih tinggi, dibandingkan dengan sistem berbasis perangkat lunak. Penelitian ini membuat rancangan antarmuka perangkat keras untuk sistem pengenalan objek dengan menggunakan modul kamera OmniVision (OV) 7670. Penelitian ini memiliki 3 komponen utama yaitu modul kamera ov7670, antarmuka kamera dan monitor. Hasil penelitian menghasilkan susunan blok – blok antarmuka modul kamera ov7670 yang dapat berjalan sesuai dengan fungsinya masing – masing. Susunan blok yang dirancang terdiri dari top_level, freq_divider, debounce, ov7670_capture, vga_pll, ov7670_controller, frame_buffer, adress_generator, RGB, dan VGA. Dalam penelitian ini secara umum hasil sintesis dapat diterjemahkan kedalam bentuk skematik.

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Rivera-Ordoñez, Cesar, Jhon Jairo Santiago und Julián Ferreira-Jaimes. „Reconocimiento de caracteres por medio de una red neuronal artificial“. Respuestas 14, Nr. 1 (05.05.2016): 30–39. http://dx.doi.org/10.22463/0122820x.523.

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En este trabajo se presenta la implementación de un sistema de reconocimientode caracteres en una tarjeta de desarrollo FPGA de propósito general. La clasificación de los caracteres se realiza por medio de un modelo de red neuronal conocido como Feed-forward backpropagation. Se utiliza la herramienta de redes neuronales NNTool de Matlab, para crear, entrenar y simular este tipo de Red Neuronal Artificial (RNA) con cinco diferentes patrones de entrenamiento. Para realizar la implementación, estas RNAs, son traducidas del modelo computacional a un modelo realizable en hardware, el cual es descrito mediante bloques en Matlab/Simulink y Xilinx System Generator (XSG). El archivo de configuración bitstream, necesario para la programación del FPGA, es generado por XSG para posteriormente ser implementado con Xilinx ISE foundation en la FPGA.Palabras Clave: FPGA, Matlab / Simulink, reconocimiento de caracteres, red neuronal artificial, Xilinx System Generator.

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Kumar, Kandagatla Ravi, Cheeli Priyadarshini, Kanakam Bhavani, Ankam Varun Sundar Kumar und Palanki Naga Nanda Sai. „Design of High Speed and Low Area Confined Multiplier on FPGA“. Revista Gestão Inovação e Tecnologias 11, Nr. 4 (22.07.2021): 2736–46. http://dx.doi.org/10.47059/revistageintec.v11i4.2315.

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In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

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Ryang, Cho Lung, und Da Ling Wang. „Resource Efficient Architecture for Current Control Loop of Two PMSMs“. Applied Mechanics and Materials 741 (März 2015): 619–22. http://dx.doi.org/10.4028/www.scientific.net/amm.741.619.

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This paper presents a novel closed current control loop of permanent magnet synchronous motor (PMSM). Conventional current control loops need two PI controllers per one PMSM. The paper provides a method for reduction of the resource consumption by using one PI controller for two PMSM. Combining with Black Box Blockset written by Verilog HDL based on Xilinx System Generator, one effective PI controller is designed instead of four PI controllers and simulated using Simulink. The utilization of FPGA resources is verified by Xilinx ISE 14.7 tool. The results show that the proposed method can reduce resource consumption and do not influence system performances observably.

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Bespalov, Nikolay, und Yury Goryachkin. „Device for Current Test Pulse Development Through a Diode in a Direct Direction“. International Journal of Engineering & Technology 7, Nr. 3.19 (07.09.2018): 81. http://dx.doi.org/10.14419/ijet.v7i3.19.16991.

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The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.

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Zulfikar, Zulfikar, Shuja A. Abbasi und Abdulrahman M. Alamoud. „FPGA Realizations of Walsh Transforms for Different Transform and Word lengths into Xilinx and Altera Chips“. International Journal of Electrical and Computer Engineering (IJECE) 8, Nr. 6 (01.12.2018): 4981. http://dx.doi.org/10.11591/ijece.v8i6.pp4981-4994.

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This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here even though this is not an apple to apple comparison. Finally, it can be concluded that Walsh transforms can be realized not only for the applications that have been done here, but it is potential can be used for other applications.

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Krim, Saber, Soufien Gdaim, Abdellatif Mtibaa und Mohamed Faouzi Mimouni. „FPGA-Based Implementation Direct Torque Control of Induction Motor“. International Journal of Power Electronics and Drive Systems (IJPEDS) 5, Nr. 3 (01.02.2015): 293. http://dx.doi.org/10.11591/ijpeds.v5.i3.pp293-304.

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This paper proposes a digital implementation of the direct torque control (DTC) of an Induction Motor (IM) with an observation strategy on the Field Programmable Gate Array (FPGA). The hardware solution based on the FPGA is caracterised by fast processing speed due to the parallel processing. In this study the FPGA is used to overcome the limitation of the software solutions (Digital Signal Processor (DSP) and Microcontroller). Also, the DTC of IM has many drawbacks such as for example; The open loop pure integration has from the problems of integration especially at the low speed and the variation of the stator resistance due to the temperature. To tackle these problems we use the Sliding Mode Observer (SMO). This observer is used estimate the stator flux, the stator current and the stator resistance. The hardware implementation method is based on Xilinx System Generator (XSG) which a modeling tool developed by Xilinx for the design of implemented systems on FPGA; from the design of the DTC with SMO from XSG we can automatically generate the VHDL code. The model of the DTC with SMO has been designed and simulated using XSG blocks, synthesized with Xilinx ISE 12.4 tool and implemented on Xilinx Virtex-V FPGA.

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Singh, Gurpadam, und Neelam R. Prakash. „FPGA Implementation of Higher Order FIR Filter“. International Journal of Electrical and Computer Engineering (IJECE) 7, Nr. 4 (01.08.2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.

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Agarwal, Charul, Ashutosh Gupta und Haneet Rana. „Performance Analysis and FPGA Implementation of Digital PID Controller for Speed Control of DC Motor“. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, Nr. 3 (10.06.2013): 638–45. http://dx.doi.org/10.24297/ijct.v7i3.3443.

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This paper deals with the performance analysis and implementation of PID(Proportional-Integral-Derivative) Controller on FPGA platform.The hardware implementation has been done on Xilinx Spartan 3E FPGA board.The software implementation has been done using Xilinx ISE 8.1i as a tool and simulation is performed using ModelSim 5.4a as a simulator.The PWM signal is generated by FPGA board,which further given to dc motor for its speed control. A new technique has been introduced for the generation of the control input as a PWM signal for controlling the motor driver circuit and decoding the optical encoder data for using it for the speed feedback in the PID control loop. The VHDL algorithm for the proposed implementation has been presented in this paper. Performance analysis of PID controller using MATLAB software shows the effectiveness of the proposed method.

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Mandalapu, Harinath, und B. Murali Krishna. „FPGA implementation of DS-CDMA Transmitter and Receiver“. International Journal of Reconfigurable and Embedded Systems (IJRES) 6, Nr. 3 (28.05.2018): 179. http://dx.doi.org/10.11591/ijres.v6.i3.pp179-185.

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Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.

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Y. David Solomon Raju, Kesari Ananda Samhitha,. „Design and Implementation of the Turbo Encoder by using Magnitude Comparator in IVS Chip“. Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, Nr. 6 (05.04.2021): 1537–45. http://dx.doi.org/10.17762/turcomat.v12i6.2692.

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This research studies the concept and application of the Turbo_encoder to be an integrated module in the In-Vehicle Device (IVS) embedded module by using the magnitude comparator. To create the Turbo_encoder Module, the complex PLDS are used. The variants of series and parallel Turbo_encoders are discussed. It is shown that proportional to chip size processing time also increased in the Turbo_encoder parallel computing variant system. The magnitude comparator with parallel computing variant system is implemented in this project. The usage of proposed logic resulted in efficient area and power usage. The architecture construction using Verilog HDL and implementation and simulation are executed in the Xilinx-ise tool. To incorporate the built module, Xilinx Vertex Low Power is used. The Turbo_encoder module on a single programmable computer is planned to be part of the IVS chip.

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T. Gadawe, Nour, und Sahar L. Qaddoori. „Design and implementation of smart traffic light controller using VHDL language“. International Journal of Engineering & Technology 8, Nr. 4 (15.12.2019): 596. http://dx.doi.org/10.14419/ijet.v8i4.29478.

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The purpose of this paper is to design and implementation of smart traffic light controller system using VHDL language and FPGA. A structure of four road intersection has been selected. The intersection to be controlled is between a busy (main street), and somewhat less busy (side street), with sensor for the side street and walk request button. Also, the system contains switches to control the traffic light manually. The intersection uses four timing parameters with ability to change these parameters manually. The system has been successfully tested with VHDL using Xilinx ISE 14.7i software environment and Chip-Scope, while, it is implemented in hardware using Xilinx Spartan 3E FPGA. It is easy to use and the cost for the same is also less as compared to the others. The designed traffic light control system is presented to work correctly as predictable.

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Amar, Hebibi, Arres Bartil und Lahcene Ziet. „Comparison of two new methods for implementa BPSK modulator using FPGA“. Indonesian Journal of Electrical Engineering and Computer Science 19, Nr. 2 (01.08.2020): 819. http://dx.doi.org/10.11591/ijeecs.v19.i2.pp819-827.

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The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.

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Al-Gailani, M. F., und Alshaima Q. Al-Khafaji. „Loop Unrolling Implementation of an AES Algorithm using Xilinx System Generator“. Iraqi Journal of Information & Communications Technology 2, Nr. 3 (27.12.2019): 38–45. http://dx.doi.org/10.31987/ijict.2.3.85.

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Cryptographic algorithm is a tool that is used to secure the transmitted data on the network. The current standard algorithm the Advanced Encryption Standard (AES) is used to maintain the security and reliability of the encrypted data whether these data are stored in computer or in transmit. AES can be implemented either in hardware or software, however hardware implementation is more sensible for high speed applications. In this paper, AES-128 algorithm is implemented in hardware in order to achieve a high-speed data processing. It is implemented on an FPGA platform using HLL language and Xilinx ISE software. The design is effectively optimized and Synthesizable with high accuracy using the conventional blocks of Xilinx System Generator. The results of implementation have enhanced the performance in terms of resource utilization, speed and power consumption as compared with other related works. The circuit operates at a maximum frequency of 800.000 MHz which offers a high throughput of 102.4 Gbps on virtex6 xc6vlx130t-3ff1156, in addition it occupies only 2,405 slices.

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ALMILADI, ABDURAZZAG, und MOHAMAD IBRAHIM. „HIGH PERFORMANCE SCALABLE RADIX-2n GF(2m) SERIAL–SERIAL MULTIPLIERS“. Journal of Circuits, Systems and Computers 18, Nr. 01 (Februar 2009): 11–30. http://dx.doi.org/10.1142/s0218126609004892.

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In this paper, a new architecture for radix-2n serial–serial multiplication/reduction for the finite field GF(2m) is presented. The input operands are serially entered one digit at a time and the output result is computed serially one digit at a time. The reduction polynomial is also fed serially to the structure so that changing the reduction polynomial will not require rewriting or rewiring the structure. The structure utilizes a serial transfer which reduces the bus width needed to transfer data back and forth between memory and multiplication unit. The structure possesses features of regularity, modularity and scalability which are a design requirement for an efficient utilization of FPGA resources. Also, a systolic scalable area efficient design which provides a 50% reduction in hardware without degrading the speed performance is proposed. A radix-4 version of the proposed architecture has been designed, simulated and synthesized using Xilinx ISE 10.1 targeting a Xilinx Virtex-5 FPGA.

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Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi und K. Karthik. „Comparative Analysis of High Speed Carry Skip Adders“. International Journal of Engineering & Technology 7, Nr. 2.24 (25.04.2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

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In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-Stone adder here so it reduces the critical path delay. In Kogge-stone adder power is highly consumed due to more no of wiring connections so another adder was designed to reduce power consumption which is Sklansky adder which reduces power Consumption. This is done in Xilinx ISE 14.7 and power was analyzed using Xilinx power analyzer.

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Wang, Lie, Xiao Jie Xu und Jian Chen. „The Research of Reconfigurable Embedded System Based on FPGA“. Applied Mechanics and Materials 665 (Oktober 2014): 718–23. http://dx.doi.org/10.4028/www.scientific.net/amm.665.718.

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Design a reconfigurable modulator by applying the method of hardware and software co-design on an FPGA chip. The system is divided into a fixed region and a reconfigurable region, and is used to realize the reconstruction of modulating by ASK, FSK or PSK. We completed the design using three tools, EDK,ISE and PlanAhead which are provided by Xilinx, and verified it on the ML403 development board. It was showed that the system realized the partial reconfigurable function, and improved the resource utilization and reconfiguration time.

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Hari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran und K. Sowmya. „Linear convolution using UT Vedic multiplier“. International Journal of Engineering & Technology 7, Nr. 2.8 (19.03.2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.

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Linear Convolution is one of the elemental operations of Signal processing systems and is used by some Multiplication Algorithms. In our project we perform Linear Convolution using ancient Multiplication Algorithm called UrdhvaTriyagbhyam (UT) which is one among the 16 sutras in Vedic mathematics. This provides best results in speed when compared to other multipliers. UrdhvaTriyagbhyam technique is used to increase the timing performance of the design. Our aim is to design 8 bit convolution using UT. The synthesis and simulation is done by using XILINX ISE Design.

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EL GOURI, Rachid, Wassima Ait Ahmed, Ahmed Lichioui und Laamari Hlou. „Conception and Implementation of a BCH Code on a FPGA Board“. International Journal of Engineering & Technology 2, Nr. 4 (28.11.2013): 293. http://dx.doi.org/10.14419/ijet.v2i4.1430.

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In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGAs Board will be shown at last.

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Wang, Guang, und Xiang Jun Li. „A Design of SIMD Core Based on PIM Technology“. Advanced Materials Research 753-755 (August 2013): 2498–502. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2498.

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An exhaustive design to the micro-architecture of SIMD core based on PIM technology is made; meanwhile the system architecture is implemented completely by applying Verilog hardware description language, and is simulated by the simulation software Xilinx ISE, the verification of the functional correctness is obtained as well via the simulation waveform. As the result, it can be concluded that the bandwidth and the delay of data accessing can be increased and reduced respectively by making full use of PIM technology, and then the performance of the entire system can be greatly improved accordingly.

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Prof. Sharayu Waghmare. „Vedic Multiplier Implementation for High Speed Factorial Computation“. International Journal of New Practices in Management and Engineering 1, Nr. 04 (31.12.2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.

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Vedic Mathematics arise from the prehistoric classification of Indian mathematics that was recreated by Tirthaji. Ancient mathematical operations are depending on sixteen methods. In this article, a new VLSI architecture to compute factorial of the given number with Vedic based multiplier is proposed. Simulations are performed using Xilinx ISE 14.2. Effective comparative analysis is made with existing multipliers to prove the momentous development in competence and high speed operation. This efficient multiplier is implemented in the proposed factorial architecture which significantly reduces the path delay and provides better optimization.

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Thakur, Garima, Harsh Sohal und Shruti Jain. „High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier“. International Journal of Engineering & Technology 7, Nr. 3.4 (25.06.2018): 213. http://dx.doi.org/10.14419/ijet.v7i3.4.16777.

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In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite.

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Shaik, Samdhani, und P. Balanagu. „Functional Verification Architecture Implementation for Power Optimized FIR Filter“. International Journal of Engineering & Technology 7, Nr. 2.20 (18.04.2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.

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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.

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Meddah, Karim, Malika Kedir Talha, Hadjer Zairi, Mohammed Nouah, Said Hadji, Mohammed A. Ait, Besma Bessekri und Hachemi Cherrih. „FPGA IMPLEMENTATION SYSTEM FOR QRS COMPLEX DETECTION“. Biomedical Engineering: Applications, Basis and Communications 32, Nr. 01 (Februar 2020): 2050005. http://dx.doi.org/10.4015/s1016237220500052.

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Due to the rising number of cardiovascular diseases death, the monitoring of cardiac patients has become a primary objective in the world. In this context, a fully FPGA-based system, for ECG signal monitoring and cardiac arrhythmia detection, has been proposed. The proposed QRS detection method is inspired by the Pan and Tompkins algorithm. It is optimized to be implemented in FPGA board Spartan 3 E (Nexys 2) using the VHDL language on the Xilinx ISE 14.2. In order to evaluate the effectiveness and reliability of our system, three comparative studies have been performed. The first comparison targeted the different results obtained with a floating-point representation under Matlab on one hand, and a fixed point representation under Xilinx ISE on the other hand, both using the MIT-BIH arrhythmia database records. The second comparison concerns the results obtained from the records of eight preselected subjects, with a commercialized electronic armband device ROMED BP-WR20 in a real-time test. The third is a comparison between the performance of our proposed method with the recent works in terms of reducing the FPGA resources list. The full embedded system has been realized completely from the signal acquisition to the display using the analog discovery device. The designed architecture has been validated using records obtained from the Massachusetts Institute of Technology — Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real-time via the analog discovery device. The overall accuracy and sensitivity are obtained as 97.6% and 97.3%, respectively.

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Maity, Heranmoy. „A New Approach to Design and Implementation of 2-Input XOR Gate Using 4-Transistor“. Micro and Nanosystems 12, Nr. 3 (01.12.2020): 240–42. http://dx.doi.org/10.2174/1876402912666200309120205.

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Aim: This paper proposed the design and implementation of a 2-input XOR gate using 4- transistor. Method : The XOR gate can be designed using NOT gate and 2:1 multiplexer. The NOT gate is designed using two metal–oxide–semiconductor field-effect transistors MOSFETs and an approximate 2:1 multiplexer. The 2:1 multiplexer is designed using two MOSFETs. So, an XOR gate can be designed using four transistors. Results: The proposed work theoretically and experimentally describes the 2-input XOR gate using 4- transistor. The proposed work was verified using Xilinx (ISE Design Suite).

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Kumar, Tanesh, Bishwajeet Pandey, S. M. Mohaiminul Islam, Narpath Singh, S. Mahbubul Alam und Teerath Das. „Mapping Based Energy Efficient Counter Design on FPGA“. Advanced Materials Research 984-985 (Juli 2014): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/amr.984-985.1085.

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— In this work, 8-bit counter power optimized counter is designed with help of energy efficient techniques called mapping and simulation activity file in format of Value Change Dump (VCD) file and setting file (*.xpa) to define toggle rate, activity rate and enable rate for the power consumption estimation in order to get energy efficient design. With mapping, there is 33.33%, 34.61%, 36.5%, 36.49%, 36.86%, 36.9% dynamic power reduction in counter when device is operating on 10MHz, 100MHz, 1GHz, 10GHz, 100GHz and 1 THz frequency. This reduction achieved by mapping control signal to control port in place of mapping control signal to LUT (Look Up Table) input. In Resource utilization, when we are mapping the control signal to control port, there is 70.58% less number of LUT and 39.89% less number of IO usage than mapping the control signal to LUT inputs. Spartan-3 FPGA is taken as target device and Xilinx 14.1 ISE is taken as design, synthesis and implementation tools. Verilog HDL(Hardware Description Language) is used to synthesize the counter on FPGA. The power dissipation of the FPGA based energy efficient design is verified using Xilinx XPower tool.

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Kulkarni, Rutuja Nandkumar, und Pradip C. Bhaskar. „Decision Based Median Filter algorithm using Resource Optimized FPGA to Extract Impulse Noise“. International Journal of Reconfigurable and Embedded Systems (IJRES) 3, Nr. 1 (01.03.2014): 1. http://dx.doi.org/10.11591/ijres.v3.i1.pp1-10.

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Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents an accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by using median value when other pixel values, 0’s or 255’s are present in the selected window and when all the pixel values are 0’s and 255’s then the noise pixel is replaced by mean value of all the elements present in the selected window. Similarly algorithm checks for five different conditions to preserve image details, object boundary in high level of noise densities. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

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Kavitha, V., und S. Mohanraj. „Power Efficient MAC Unit Based Digital PID Controllers“. JOURNAL OF ADVANCES IN CHEMISTRY 12, Nr. 9 (03.11.2016): 4324–29. http://dx.doi.org/10.24297/jac.v12i9.4090.

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Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product.

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Cecilia Sandoval, Cecilia. „Diseño de un codificador y decodificador digital Reed-Solomon usando programación en VHDL“. Nexo Revista Científica 21, Nr. 01 (02.06.2011): 2–10. http://dx.doi.org/10.5377/nexo.v21i01.393.

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En este artículo se presenta un procedimiento práctico para el diseño de un codificador/decodificador Reed-Solomon a través de la descripción funcional usando lenguaje descriptor de hardware (VHDL) con la herramienta de programación Xilinx ISE 9.2i. Este trabajo propone un diseño que usa los beneficios que presenta la programación VHDL, su característica de modularidad, y la estrategia de seccionar el diseño en componentes menos complejos para facilitar el proceso. Además, se detalla la metodología del diseño del decodificador a través de procesamiento paralelo. Para la validación del comportamiento del codificador/decodificador, se realizaron simulaciones con el programa ModelSim XE 5.7c.Palabras claves: codificador Reed-Solomon; diseño de hardware; VHDL

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Mohammad, Imran, und Ramananjaneyulu K. „FPGA Implementation of a 64-Bit RISC Processor Using VHDL“. International Journal of Reconfigurable and Embedded Systems (IJRES) 1, Nr. 2 (01.07.2012): 59. http://dx.doi.org/10.11591/ijres.v1.i2.pp59-66.

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In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.

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Bani-Hani, Raed, Khaldoon Mhaidat und Salah Harb. „Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications“. Journal of Circuits, Systems and Computers 25, Nr. 07 (22.04.2016): 1650080. http://dx.doi.org/10.1142/s0218126616500808.

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In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

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Khan, Angshuman, Sudip Halder und Shubhajit Pal. „Design of ASIC Square Calculator Using AncientVedic Mathematics“. International Journal of Engineering & Technology 7, Nr. 2.23 (20.04.2018): 464. http://dx.doi.org/10.14419/ijet.v7i2.23.15334.

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This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

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Saraswathi, N., Lokesh Modi und Aatish Nair. „Complex Number Vedic Multiplier and its Implementation in a Filter“. International Journal of Engineering & Technology 7, Nr. 2.24 (25.04.2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.

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Complex numbers multiplication is a fundamental mathematical process in systems like digital signal processors (DSP). The main objective of complex number multiplication is to perform operations at lightning fast speed with less intake of power. In this paper, the best possible architecture is designed for a Real vedic multiplier based on the ancient Indian mathematical procedure known as URDHVA TIRYAKBHYAM SUTRA i.e. the structure of a MxM Vedic real multiplier architecture is developed. Then, a Vedic real multiplier solution of a complex multiplier is presented and its simulation results are obtained. The MxM Vedic real multiplier architecture, architecture of the Real Vedic multiplier solution for 32 x 32 bit complex numbers multiplication of complex multiplier and the architecture of a FIR filter has been code in Verilog and implementation is done through Modelsim 5.6 and Xilinx ISE 7.1 navigator.

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Bibilo, P. N., Yu Yu Lankevich und V. I. Romanov. „Logical minimization for combinatorial structure in FPGA“. Informatics 18, Nr. 1 (29.03.2021): 7–24. http://dx.doi.org/10.37661/1816-0301-2021-18-1-7-24.

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The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

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