Thematische Bibliographien / Triple gate transistor

Inhaltsverzeichnis

  1. Zeitschriftenartikel
  2. Dissertationen
  3. Buchteile
  4. Konferenzberichte

Auswahl der wissenschaftlichen Literatur zum Thema „Triple gate transistor“

Autor: Grafiati
Veröffentlicht am 25. Mai 2024
Zuletzt aktualisiert am 31. Juli 2025

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Zeitschriftenartikel zum Thema "Triple gate transistor"

1

Grossl Bade, Tamiris, Hassan Hamad, Adrien Lambert, Hervé Morel, and Dominique Planson. "Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs." Electronics 12, no. 11 (2023): 2529. http://dx.doi.org/10.3390/electronics12112529.

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The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a Vth measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the Vth measurement, even for measurements following degrading voltage
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Cho, Seong-Kun, and Won-Ju Cho. "Highly Sensitive and Transparent Urea-EnFET Based Point-of-Care Diagnostic Test Sensor with a Triple-Gate a-IGZO TFT." Sensors 21, no. 14 (2021): 4748. http://dx.doi.org/10.3390/s21144748.

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In this study, we propose a highly sensitive transparent urea enzymatic field-effect transistor (EnFET) point-of-care (POC) diagnostic test sensor using a triple-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film pH ion-sensitive field-effect transistor (ISFET). The EnFET sensor consists of a urease-immobilized tin-dioxide (SnO2) sensing membrane extended gate (EG) and an a-IGZO thin film transistor (TFT), which acts as the detector and transducer, respectively. To enhance the urea sensitivity, we designed a triple-gate a-IGZO TFT transducer with a top gate (TG) at the top of the chan
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Conde, Jorge E., Antonio Cereira, and M. Estrada. "Distortion Analysis of Triple-Gate Transistor in Saturation." ECS Transactions 9, no. 1 (2019): 67–73. http://dx.doi.org/10.1149/1.2766875.

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4

Gay, R., V. Della Marca, H. Aziza, et al. "Gate stress reliability of a novel trench-based Triple Gate Transistor." Microelectronics Reliability 126 (November 2021): 114233. http://dx.doi.org/10.1016/j.microrel.2021.114233.

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5

P., Kiran Kumar, Sunil Kumar G., and Karthik A. "Triple Gate Spin Field-Effect Transistor Modeling and Applications." Journal of VLSI Design and its Advancement 6, no. 1 (2023): 7–13. https://doi.org/10.5281/zenodo.7751334.

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<em>In this research, a mathematical model is used to simulate a Triple Gate Spin-FET with Indium Arsenide in the channel. DC simulations verify the simulation results. Later, different logic functions are achieved by specifying the appropriate channels and several other parameters like spin injection, spin detection, etc. Each gate terminal receives a unique set of inputs. One multi gate spin-FET is used to attain the desired functionality. Using conventional CMOS to achieve the same goals would require a far greater number of chips. The attained capabilities are competitive with designs usin
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SHAHHOSEINI, ALI, KAMYAR SAGHAFI, MOHAMMAD KAZEM MORAVVEJ-FARSHI, and RAHIM FAEZ. "TRIPLE-TUNNEL JUNCTION SINGLE ELECTRON TRANSISTOR (TTJ-SET)." Modern Physics Letters B 25, no. 17 (2011): 1487–501. http://dx.doi.org/10.1142/s0217984911026346.

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We propose a triple-tunnel junction single electron transistor (TTJ-SET). The proposed structure consists of a metallic quantum-dot island that is capacitive coupled to a gate contact and surrounded by three tunnel junctions. To the best of our knowledge, this is the first instance of introducing this new structure that is suitable for both digital and analog applications. I–V D characteristics of the proposed TTJ-SET, simulated by a HSPICE macro model for various gate voltages, are in excellent agreement with those obtained by SIMON, which is a Monte-Carlo based simulator. We show how one can
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Pandey, Neeta, Kirti Gupta, and Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation." VLSI Design 2016 (September 19, 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is a
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Manikandan, S., P. Suveetha Dhanaselvam, and M. Karthigai Pandian. "A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor." Journal of Nanoelectronics and Optoelectronics 16, no. 2 (2021): 318–23. http://dx.doi.org/10.1166/jno.2021.2951.

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A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along
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de Araujo, Gustavo Vinicius, Joao Martino, and Paula Agopian. "Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1861. http://dx.doi.org/10.1149/ma2023-01331861mtgabs.

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The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2]. The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage
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Fui, Tan Chun, Ajay Kumar Singh, and Lim Way Soong. "Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)." International Journal of Robotics and Automation Technology 8 (December 31, 2021): 83–89. http://dx.doi.org/10.31875/2409-9694.2021.08.8.

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Abstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the performance of the conventional FET. In the proposed structure, the gate region is divided into three dielectric materials: TiO2/Al2O3/SiO2. This approach is chosen because high dielectric material alone near the source cannot improve the perfor
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Dissertationen zum Thema "Triple gate transistor"

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Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture
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Andrade, Maria Glória Caño de. "Estudo de transistores de porta tripla de corpo." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10062013-150025/.

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O objetivo principal deste trabalho é o estudo de transistores MuGFETs de porta tripla de Corpo de canal tipo-n com e sem a aplicação da configuração DTMOS. Este estudo será realizado através de simulações numéricas tridimensionais e por caracterizações elétricas. A corrente de dreno, a transcondutância, a resistência, a tensão de limiar, a inclinação de sublimiar e a Redução da Barreira Induzida pelo Dreno (DIBL) serão analisadas em modo DTMOS e em configuração de polarização convencional. Importantes figuras de mérito para o desempenho analógico como transcondutância-sobre-corrente de dreno,
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Bertoldo, Marcelo. "Efeitos da radiação de prótons em FinFET\'s de porta tripla de corpo (Bulk-FinFET)." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-24012017-082703/.

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O transistor de efeito de campo por aletas de porta tripla de corpo (Bulk-FinFET) é um dispositivo com aplicações comerciais e possui algumas vantagens sobre os FinFETs de porta tripla SOI (Silício sobre Isolante - Silicon on Insulator). Estas vantagens são devidas ao custo da lâmina mais competitivo e maior quantidade de fabricantes de lâmina de silício, além da compatibilidade com processos de tecnologias convencionais de substrato de silício e melhor dissipação térmica. Aplicações aeroespaciais estão sujeitas à incidência das radiações ionizantes de partículas e eletromagnéticas. Os efeitos
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Huang, Ming-Jiu, and 黃明俥. "The Optical Responses of Dual-Gate and Triple-Gate Carbon Nanotube Thin Film Transistors and its Correlation with Electrical Behaviors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/31221307755751646598.

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碩士<br>清雲科技大學<br>電子工程研究所<br>95<br>In recent years, carbon nanotube field effect transistors (CNT-FETs) had great advance in emission light. But the mechanism of optical responses and its correlation with the FET’s electrical behavior are still unclear. In this thesis, we design the dual-gate and triple-gate structure in our CNT FETs and then measure their electrical and optical responses. First, the FET is screened by traditional tri-point measurement. Based on their Id-Vds characteristics and on/off current ratio, those devices are classified as metal, semiconductor and ambipolar and unipolar
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Buchteile zum Thema "Triple gate transistor"

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Dutta, Ritam, and Nitai Paitya. "Effect of Pocket Intrinsic Doping on Double and Triple Gate Tunnel Field Effect Transistors." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0829-5_25.

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Saraswathi, D., N. B. Balamurugan, G. Lakshmi Priya, and S. Manikandan. "A Compact Analytical Model for 2D Triple Material Surrounding Gate Nanowire Tunnel Field Effect Transistors." In Intelligent Computing and Applications. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2268-2_35.

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Dutta, Ritam, and Nitai Paitya. "Novel InAs/Si Heterojunction Dual-Gate Triple Metal P-i-N Tunneling Graphene Nanoribbon Field Effect Transistοr (DG-TM-TGNFET) Fοr High-Frequency Applicatiοns." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4947-9_17.

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Kandpal, Jyoti, and Ekta Goel. "Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS." In Nanoscale Field Effect Transistors: Emerging Applications. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815165647123010005.

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Low-power application devices and inexpensive transistors are essential for today's technological world. A 3 nm MOSFET nanoelectronic device has just been created by researchers. Even though a MOSFET shrinks in size and uses less power, SCEs still cause a few problems, leakage current, including Hot electron, Impact Ionization, threshold voltage roll-off, Drain Induced Barrier Lowering (DIBL), and others. One of the best-proposed structures to replace the MOSFET structure is the FIN FET structure, which overcomes the limitations brought on by the CMOS transistor. For low-power applications, th
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Konferenzberichte zum Thema "Triple gate transistor"

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Maity, Indranil, Arighna Bhattacharjee, and Arijit Mondal. "Modulation of Electronic Properties in Triple Metal Gate Vertical Tunnel Field Effect Transistors by the Variation of Gate Dielectrics." In 2024 IEEE Calcutta Conference (CALCON). IEEE, 2024. https://doi.org/10.1109/calcon63337.2024.10914239.

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Bin Kashem, Md Tashfiq, and Samia Subrina. "Characteristics of Triple Material Gate AlGaN/GaN High Electron Mobility Transistor." In 2015 International Conference on Advances in Electrical Engineering (ICAEE). IEEE, 2015. http://dx.doi.org/10.1109/icaee.2015.7506867.

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Dewan, Monzurul Islam, Md Tashfiq Bin Kashem, and Samia Subrina. "Characteristic analysis of triple material tri-gate junctionless tunnel field effect transistor." In 2016 9th International Conference on Electrical and Computer Engineering (ICECE). IEEE, 2016. http://dx.doi.org/10.1109/icece.2016.7853924.

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Okuyama, Kiyoshi, Koji Yoshikawa, and Hideo Sunami. "Proposal of 3-Dimensional Independent Triple-Gate MOS Transistor with Dynamic Current Control." In 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA). IEEE, 2007. http://dx.doi.org/10.1109/vtsa.2007.378951.

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Malik, Gul Faroz Ahmad, Mubashir Ahmad, Farooq Ahmad Khanday, and Nusrat Parveen. "Simulation of Triple Gate Spin Field-Effect Transistor and its Applications to Digital Logic." In 2020 IEEE VLSI Device Circuit and System (VLSI DCS). IEEE, 2020. http://dx.doi.org/10.1109/vlsidcs47293.2020.9179894.

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Chatterjee, Soumya, Sreyan Ray, Sovan Kumar Dey, Subhadip Hazra, Soumik Kar, and Sulagna Chatterjee. "Triple gate Field Effect Transistor (TGFET) with voltage control potential wells (VCPWs) along the channel." In 2016 IEEE 7th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON). IEEE, 2016. http://dx.doi.org/10.1109/iemcon.2016.7746348.

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Berthollet, F., S. Cremer, G. Bossu, et al. "Low cost and high performance p-doped triple-gate access transistor for embedded DRAM memory cell." In 2009 Proceedings of the European Solid State Device Research Conference (ESSDERC). IEEE, 2009. http://dx.doi.org/10.1109/essderc.2009.5331317.

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Chang, C. H., C. Y. Chou, C. N. Han, C. T. Peng, and Kuo-Ning Chiang. "Local-strain effect of the SiN/Si stacking and nanoscale triple gate Si/SiGe MOS transistor." In Microelectronics, MEMS, and Nanotechnology, edited by Alex J. Hariz. SPIE, 2005. http://dx.doi.org/10.1117/12.638567.

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Lamba, V. K., Derick Engles, and S. S. Malik. "Modeling and Designing a Device Using MuGFETs." In ASME 2008 3rd Energy Nanotechnology International Conference collocated with the Heat Transfer, Fluids Engineering, and Energy Sustainability Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/enic2008-53015.

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This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studi
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Paz, Bruna Cardoso, Marcelo Antonio Pavanello, Mikael Casse, et al. "From double to triple gate: Modeling junctionless nanowire transistors." In 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 2015. http://dx.doi.org/10.1109/ulis.2015.7063759.

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