Zeitschriftenartikel: „Trench transistor“

1

Shichijo, H., S. K. Banerjee, S. D. S. Malhi, G. P. Pollack, W. F. Richardson, D. M. Bordelon, R. H. Womack et al. „Trench transistor DRAM cell“. IEEE Electron Device Letters 7, Nr. 2 (Februar 1986): 119–21. http://dx.doi.org/10.1109/edl.1986.26313.

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2

Gupta, Aakashdeep, K. Nidhin, Suresh Balanethiram, Shon Yadav, Anjan Chakravorty, Sebastien Fregonese und Thomas Zimmer. „Static Thermal Coupling Factors in Multi-Finger Bipolar Transistors: Part I—Model Development“. Electronics 9, Nr. 9 (19.08.2020): 1333. http://dx.doi.org/10.3390/electronics9091333.

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In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

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3

Banerjee, S., und D. M. Bordelon. „A model for the trench transistor“. IEEE Transactions on Electron Devices 34, Nr. 12 (Dezember 1987): 2485–92. http://dx.doi.org/10.1109/t-ed.1987.23339.

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4

Mukherjee, Kalparupa, Carlo De Santi, Matteo Borga, Karen Geens, Shuzhen You, Benoit Bakeroot, Stefaan Decoutere et al. „Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization“. Materials 14, Nr. 9 (29.04.2021): 2316. http://dx.doi.org/10.3390/ma14092316.

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The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

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5

Dai, Tian Xiang, A. B. Renz, Luyang Zhang, Oliver J. Vavasour, G. W. C. Baker, Vishal Ajit Shah, Philip A. Mawby und Peter M. Gammon. „Design and Optimisation of Schottky Contact Integration in a 4H-SiC Trench MOSFET“. Materials Science Forum 1004 (Juli 2020): 808–13. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.808.

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Planar Schottky contact and various trench Schottky contacts have been integrated into the edge termination region of a 4H-SiC trench metal-oxide-semiconductor field-effect-transistor (MOSFET). The forward and reverse characteristics of various design splits have been benchmarked to determine the optimum method of the Schottky contact integration. As a result, the trench Schottky diode with Schottky metal contact in both the planar surface and the trench sidewall surface has been able to offer the best performance.

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6

Chen, Q., B. You, A. Q. Huang und J. K. O. Sin. „A new trench base-shielded bipolar transistor“. IEEE Transactions on Electron Devices 47, Nr. 8 (2000): 1662–66. http://dx.doi.org/10.1109/16.853045.

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7

Wang, Bo. „Analysis of base characteristics of trench gate field termination IGBT“. E3S Web of Conferences 237 (2021): 02023. http://dx.doi.org/10.1051/e3sconf/202123702023.

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Trench gate structure represents the latest structure of Insulated Gate Bipolar Transistor(IGBT). Because there are great differences in model analysis coordinate system and carrier transport between trench gate structure and planar gate structure, the modeling method using planar gate structure will inevitably have great deviation. Based on the characteristics of trench gate structure and model analysis coordinate system, the base region is divided into PNP and PIN by considering the two-dimensional effect of carriers. According to whether the trench of PIN part can be covered by depletion layer of PNP part, the specific base region current is analyzed. Finally, simulation and experimental verification are carried out.

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Manosukritkul, Phasapon, Amonrat Kerdpardist, Montree Saenlamool, Ekalak Chaowicharat, Amporn Poyai und Wisut Titiroongruang. „An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer“. Advanced Materials Research 717 (Juli 2013): 158–63. http://dx.doi.org/10.4028/www.scientific.net/amr.717.158.

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In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakdown voltage increased by approximately 30% compared with conventional NPT-TIGBT.

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Yang, Ling Ling. „A Novel Structure Trench IGBT with Full Hole-Barrier Layer“. Applied Mechanics and Materials 543-547 (März 2014): 757–61. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.757.

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A Full Hole-barrier Trench gate Insulated Gate Bipolar Transistor (FH-TIGBT) device structure is proposed for the first time. Compared with Carrier Stored Trench IGBT (CSTBT), which adds a carrier stored n layer between p base and n base in Trench IGBT (TIGBT), the new structure appends an n region located in the bottom of the trench gate. The result of Process and device simulations shows that the proposed device has lowered saturation voltage and larger capability of carrying current compared to either conventional trench IGBT or CSTBT. And the characteristics of turn-off time and breakdown voltage have negligibly changed. Further more, it has strongly positive temperature coefficient of on-state voltage, which means paralleling is very simple for the new device.

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10

Hung, Chia Lung, Yi Kai Hsiao, Chang Ching Tu und Hao Chung Kuo. „Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications“. Materials Science Forum 1088 (18.05.2023): 41–49. http://dx.doi.org/10.4028/p-56sbi2.

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A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

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11

Shu, Lei, Huai-Lin Liao, Zi-Yuan Wu, Xing-Yu Fang, Shi-Wei Liang, Tong-De Li, Liang Wang, Jun Wang und Yuan-Fu Zhao. „Effects of Gamma Irradiation on Switching Characteristics of SiC MOSFET Power Devices of Different Structures“. Electronics 12, Nr. 10 (11.05.2023): 2194. http://dx.doi.org/10.3390/electronics12102194.

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The switching characteristics of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices of different structures were experimented after exposure to a gamma irradiation environment. The experimental results for on-state were studied. The comparisons are shown for SiC MOSFET power devices with planar, trench and double trench structures tested for total ionizing dose (TID). A higher degradation of the switching characteristics was observed for the double trench structure. The physical mechanisms for these switching characteristics variations were analyzed. In addition, they were confirmed by technology computer-aided design (TCAD) simulation.

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12

Wang, Bo. „Analysis of junction capacitance characteristics of trench gate IGBT“. E3S Web of Conferences 237 (2021): 02024. http://dx.doi.org/10.1051/e3sconf/202123702024.

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Trench gate field termination IGBT represents the latest structure of insulated gate bipolar transistor (IGBT). Because the internal current of IGBT includes the charging and discharging current of gate capacitance and internal junction capacitance during switching transient, the influence of junction capacitance should be considered. The conductive channel of trench gate structure is different from that of planar gate structure, and the analysis method of junction capacitance using planar gate structure will inevitably bring some deviation. Based on the characteristics of trench gate structure, this paper analyzes the different expressions of internal gate-drain junction capacitance in two cases according to whether the base depletion layer can be widened to cover the trench gate, and finally carries out simulation and experimental verification.

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13

Banzhaf, Christian T., Michael Grieb, Achim Trautmann, Anton J. Bauer und Lothar Frey. „Investigation of Trenched and High Temperature Annealed 4H-SiC“. Materials Science Forum 778-780 (Februar 2014): 742–45. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.742.

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This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight enlargement of the trench width along with a considerable increase of the substrate surface roughness. In addition, X-ray photoelectron spectroscopy (XPS) depth profiles indicate an increased carbon atom concentration at the 4H-SiC surface after the high temperature PTA. The non-stoichiometric surface composition affects the quasi-static capacitance-voltage (QSCV) behavior of MOS structures using a deposited gate oxide (GOX). We assume that a sacrificial oxidation directly after the PTA could restore a stoichiometric 4H-SiC surface.

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14

Shah, A. H., C. Wang, R. H. Womack, J. D. Gallia, H. Shichijo, H. E. Davis, M. Elahy et al. „A 4-Mbit DRAM with trench-transistor cell“. IEEE Journal of Solid-State Circuits 21, Nr. 5 (Oktober 1986): 618–26. http://dx.doi.org/10.1109/jssc.1986.1052586.

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15

Huang, Q., und G. A. J. Amaratunga. „Analysis of double trench insulated gate bipolar transistor“. Solid-State Electronics 38, Nr. 4 (April 1995): 829–38. http://dx.doi.org/10.1016/0038-1101(94)00110-2.

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16

Aur, S., und Ping Yang. „IVB-6 hot-carrier reliability of trench transistor“. IEEE Transactions on Electron Devices 34, Nr. 11 (November 1987): 2374. http://dx.doi.org/10.1109/t-ed.1987.23289.

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17

Banerjee, S., D. Coleman, W. Richardson und A. Shah. „Leakage mechanisms in the trench transistor DRAM cell“. IEEE Transactions on Electron Devices 35, Nr. 1 (Januar 1988): 108–16. http://dx.doi.org/10.1109/16.2425.

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18

Hueting, R. J. E., J. W. Slotboom, J. Melai, P. Agarwal und P. H. C. Magnee. „A New Trench Bipolar Transistor for RF Applications“. IEEE Transactions on Electron Devices 51, Nr. 7 (Juli 2004): 1108–13. http://dx.doi.org/10.1109/ted.2004.829867.

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19

Kakarla, Bhagyalakshmi, Thomas Ziemann, Selamnesh Nida, Elias Doenni und Ulrike Grossner. „Planar to Trench: Short Circuit Capability Analysis of 1.2 kV SiC MOSFETs“. Materials Science Forum 924 (Juni 2018): 782–85. http://dx.doi.org/10.4028/www.scientific.net/msf.924.782.

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This paper presents an insight into the short circuit (SC) capability of Rohm’s discrete 1.2 kV, 80 mΩ state-of-the-art silicon carbide (SiC) double trench metal-oxide-semiconductor field effect transistor (MOSFET). SC measurements are performed to compare the behavior of Wolfspeed’s similarly rated 1.2 kV, 80 mΩ planar MOSFET with the Rohm trench devices. Short circuit withstand time (SCWT) of both designs under nominal operating conditions at room temperature is measured by performing destructive SC tests.

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20

Sugiyama, Naohiro, Yuuichi Takeuchi, Mitsuhiro Kataoka, Adolf Schöner und Rajesh Kumar Malhan. „Growth Mechanism and 2D Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region“. Materials Science Forum 600-603 (September 2008): 171–74. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.171.

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The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.

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21

Jiang, Dandan, Lei Jin und Zongliang Huo. „A Quantitative Approach to Characterize Total Ionizing Dose Effect of Periphery Device for 65 nm Flash Memory“. Nanoscience and Nanotechnology Letters 10, Nr. 3 (01.03.2018): 378–82. http://dx.doi.org/10.1166/nnl.2018.2604.

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To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized. For a W =10 μm HVN device, the main transistor Vth shows a shift of <0.1 V with a TID of 100 krad (Si), while the parasitic transistor shows shift >0.5 V with 100 krad (Si) radiation. It is concluded that the net positive charge accumulating in the shallow trench isolation oxide is responsible for the TID induced leakage and the Vth shift in the flash technology periphery device.

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Zhang, Meng, Baikui Li, Zheyang Zheng, Xi Tang und Jin Wei. „A New SiC Planar-Gate IGBT for Injection Enhancement Effect and Low Oxide Field“. Energies 14, Nr. 1 (25.12.2020): 82. http://dx.doi.org/10.3390/en14010082.

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A new silicon carbide (SiC) planar-gate insulated-gate bipolar transistor (IGBT) is proposed and comprehensively investigated in this paper. Compared to the traditional SiC planar-gate IGBT, the new IGBT boasts a much stronger injection enhancement effect, which leads to a low on-state voltage (VON) approaching the SiC trench-gate IGBT. The strong injection enhancement effect is obtained by a heavily doped carrier storage layer (CSL), which creates a hole barrier under the p-body to hinder minority carriers from being extracted away through the p-body. A p-shield is located at the bottom of the CSL and coupled to the p-body of the IGBT by an embedded p-MOSFET (metal-oxide-semiconductor field effect transistors). In off-state, the heavily doped CSL is shielded by the p-MOSFET clamped p-shield. Thus, a high breakdown voltage is maintained. At the same time, owing to the planar-gate structure, the proposed IGBT does not suffer the high oxide field that threatens the long-term reliability of the trench-gate IGBT. The turn-off characteristics of the new IGBT are also studied, and the turn-off energy loss (EOFF) is similar to the conventional planar-gate IGBT. Therefore, the new IGBT achieves the benefits of both the conventional planar-gate IGBT and the trench-gate IGBT, i.e., a superior VON-EOFF trade-off and a low oxide field.

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Son, Won-So, Young-Ho Sohn und Sie-young Choi. „SOI RESURF LDMOS transistor using trench filled with oxide“. Electronics Letters 39, Nr. 24 (2003): 1760. http://dx.doi.org/10.1049/el:20031115.

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24

Cai, J., J. K. O. Sin, P. K. T. Mok, Wai-Tung Ng und P. P. T. Lai. „A new lateral trench-gate conductivity modulated power transistor“. IEEE Transactions on Electron Devices 46, Nr. 8 (1999): 1788–93. http://dx.doi.org/10.1109/16.777171.

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25

Spulber, O., M. Sweet, K. Vershinin, C. K. Ngw, L. Ngwendson, J. V. S. C. Bose, M. M. De Souza und E. M. Sanakara Narayanan. „A novel trench clustered insulated gate bipolar transistor (TCIGBT)“. IEEE Electron Device Letters 21, Nr. 12 (Dezember 2000): 613–15. http://dx.doi.org/10.1109/55.887483.

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26

Na, Jaeyeop, Jinhee Cheon und Kwangsoo Kim. „4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics“. Materials 14, Nr. 13 (25.06.2021): 3554. http://dx.doi.org/10.3390/ma14133554.

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In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

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Li, Xuan, Xing Tong, Alex Q. Huang, Shi Qiu, Xu She, Xiao Сhuan Deng und Bo Zhang. „Shielded Gate SiC Trench Power MOSFET with Ultra-Low Switching Loss“. Materials Science Forum 924 (Juni 2018): 765–69. http://dx.doi.org/10.4028/www.scientific.net/msf.924.765.

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A shielded gate trench silicon carbide (SiC) metal oxide semiconductor field effect transistor (SG-TMOS) is proposed and investigated by simulation in this paper. The impact of shielded gate design in SG-TMOS on Miller charge (Qgd) as well as conduction resistance (Ron) are comprehensively discussed, showing a tradeoff between Qgdand Ron. Furthermore, the Huang’s Figure of Merit (HFOM) of the SG-TMOS with reasonable design of SG is reduced more than 20%, compared with the conventional trench MOSFET (C-TMOS). Therefore, the proposed SG-TMOS is a competitive next generation device structure for ultra-high switching speed SiC MOSFET.

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Shu, Lei, Huai-Lin Liao, Zi-Yuan Wu, Yan-Yan Li, Xing-Yu Fang, Shi-Wei Liang, Tong-De Li, Liang Wang, Jun Wang und Yuan-Fu Zhao. „Comparison of Gamma Irradiation Effects on Short Circuit Characteristics of SiC MOSFET Power Devices between Planar and Trench Structures“. Electronics 12, Nr. 13 (30.06.2023): 2891. http://dx.doi.org/10.3390/electronics12132891.

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The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation.

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Takeuchi, Wakana, Eiji Kagoshima, Kazushi Sumitani, Yasuhiko Imai, Shigehisa Shibayama, Mitsuo Sakashita, Shigeru Kimura et al. „Visualization of local strain in 4H-SiC trench metal-oxide-semiconductor field-effect transistor using synchrotron nanobeam X-ray diffraction“. Japanese Journal of Applied Physics 61, SC (21.03.2022): SC1072. http://dx.doi.org/10.35848/1347-4065/ac4c6d.

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Abstract We investigated the local strain in a silicon carbide (4H-SiC) (0001) trench metal-oxide semiconductor field-effect transistor (MOSFET) using synchrotron nanobeam X-ray diffraction (nano-XRD) at the SPring-8 BL13XU beamline. Using X-rays incident on the 4H-SiC trench cross section, diffraction measurements were performed on the ( 11 2 ¯ 0 ) and ( 11 2 ¯ 4 ) planes. Intensity maps of the 11 2 ¯ 0 and 11 2 ¯ 4 diffractions yielded images reflecting the trench structure. The spatial resolution of the 4H-SiC 11 2 ¯ 4 intensity map in the [0001] direction was higher than that for the 11 2 ¯ 0 diffraction because the angle of incidence was close to perpendicular to the sample. From two-dimensional reciprocal space maps of the symmetric and asymmetric diffractions, the tilt and the ( 11 2 ¯ 0 ) - and (0004)-plane strain components were individually separated and visualized. A tensile strain of approximately 0.1% was found in the region between the trenches. These results indicate the effectiveness of nano-XRD for strain visualization in trench MOSFETs and similar electronic devices.

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Zhou, Xuanze, Yongjian Ma, Guangwei Xu, Qi Liu, Jinyang Liu, Qiming He, Xiaolong Zhao und Shibing Long. „Enhancement-mode β-Ga₂O₃ U-shaped gate trench vertical MOSFET realized by oxygen annealing“. Applied Physics Letters 121, Nr. 22 (28.11.2022): 223501. http://dx.doi.org/10.1063/5.0130292.

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Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of the sample surfaces of different annealing temperature was characterized by x-ray photoelectron spectroscopy measurements, indicating good process controllability. Furthermore, photoluminescence spectra were measured to study the effect of oxygen annealing. The fabricated UMOSFET showed normally off with a Vth of 11.5 V, an on-state resistance of 1.48 Ω cm2, a maximum on-state current of 11 A/cm2, an on–off ratio of 6 × 104, and a three-terminal breakdown voltage over 100 V. This work paves a way to form a CBL and broadens the design space for high-power β-Ga2O3 vertical transistors.

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Na, Jaeyeop, Jinhee Cheon und Kwangsoo Kim. „High performance 4H-SiC MOSFET with deep source trench“. Semiconductor Science and Technology 37, Nr. 4 (17.02.2022): 045004. http://dx.doi.org/10.1088/1361-6641/ac5103.

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Abstract In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s figure of merit of DST-MOSFET improved by 9% and 104%, respectively, in comparison with those of UMOSFET; and by 37% and 64%, respectively, compared to those of DT-MOSFET. Additionally, the SPR reduced the gate-to-drain capacitance of the DST-MOSFET and improved the switching characteristics. Consequently, the total switching energy loss of the proposed DST-MOSFET reduced by 63% and 47% in comparison with those of the UMOSFET and DT-MOSFET, respectively.

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Jeong, Jee-Hun, Ju-Hong Cha, Goon-Ho Kim, Sung-Hwan Cho und Ho-Jun Lee. „Study of a SiC Trench MOSFET Edge-Termination Structure with a Bottom Protection Well for a High Breakdown Voltage“. Applied Sciences 10, Nr. 3 (21.01.2020): 753. http://dx.doi.org/10.3390/app10030753.

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A novel edge-termination structure for a SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) power device is proposed. The key feature of the proposed structure is a periodically formed SiC trench with a bottom protection well (BPW) implantation region. The trench can be filled with oxide or gate materials. Indeed, it has almost the same cross-sectional structure as the active region of a SiC trench MOSFET. Therefore, there is little or no additional process loads. A conventional floating field ring (FFR) structure utilizes the spreading of the electric field in the periodically depleted surface region formed between a heavily doped equipotential region. On the other hand, in the trenched ring structure, an additional quasi-equipotential region is provided by the BPW region, which enables deeper and wider field-spreading profiles, and less field crowding at the edge region. The two-dimensional Technology Computer Aided Design (2D-TCAD) simulation results show that the proposed trenched ring-edge termination structures have an improved breakdown voltage compared to the conventional floating field ring structure.

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Zhang, Meng, Baikui Li und Jin Wei. „Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs“. Crystals 10, Nr. 5 (23.05.2020): 417. http://dx.doi.org/10.3390/cryst10050417.

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The state-of-the-art silicon insulated-gate bipolar transistor (IGBT) features a trench gate, since it enhances the conductivity modulation. The SiC trench IGBT, however, faces the critical challenge of a high electric field in the gate oxide, which is a crucial threat to the device’s reliability. In this work, we explore the possibility of using a SiC planar IGBT structure to approach high performance to the level of a SiC trench IGBT, without suffering the high gate oxide field. The proposed SiC planar IGBT features buried p-layers directly under the p-bodies, and thus can be formed using the same mask set. The region between the buried p-layer and the p-body is heavily doped with n-type dopants so that the conductivity modulation is improved. Comprehensive TCAD simulations have been carried out to verify this concept, and the simulation results show the new SiC planar IGBT exhibits a high performance comparable to the trench IGBT, and also exhibits a low gate oxide field.

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Yang, Jianan, John P. Denton und Gerold W. Neudeck. „Edge transistor elimination in oxide trench isolated N-channel metal–oxide–semiconductor field effect transistors“. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 19, Nr. 2 (2001): 327. http://dx.doi.org/10.1116/1.1358854.

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35

Qian, Zhehong, Wenrong Cui, Tianyang Feng, Hang Xu, Yafen Yang, Qingqing Sun und David Wei Zhang. „A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness“. Micromachines 15, Nr. 6 (22.05.2024): 680. http://dx.doi.org/10.3390/mi15060680.

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A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times.

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Zeng, J., P. A. Mawby, M. S. Towers und K. Board. „THERMO‐ELECTRIC STUDY OF THE TRENCH‐GATE POWER VDMOS TRANSISTOR“. COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, Nr. 4 (April 1994): 735–42. http://dx.doi.org/10.1108/eb051891.

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Rongyao, Ma, Li Zehong, Hong Xin und Zhang Bo. „Carrier stored trench-gate bipolar transistor with p-floating layer“. Journal of Semiconductors 31, Nr. 2 (Februar 2010): 024004. http://dx.doi.org/10.1088/1674-4926/31/2/024004.

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38

Hieda, K., F. Horiguchi, H. Watanabe, K. Sunouchi, I. Inoue und T. Hamamoto. „Effects of a new trench-isolated transistor using sidewall gates“. IEEE Transactions on Electron Devices 36, Nr. 9 (September 1989): 1615–19. http://dx.doi.org/10.1109/16.34221.

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39

Ma, Rongyao, Ruoyu Wang, Hao Fang, Ping Li, Longjie Zhao, Hao Wu, Zhiyong Huang, Jingyu Tao und Shengdong Hu. „A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance“. Micromachines 15, Nr. 6 (23.05.2024): 684. http://dx.doi.org/10.3390/mi15060684.

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In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively.

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Akiyama, Satoru, Haruka Shimizu, Natsuki Yokoyama, Tomohiro Tamaki, Sadayuki Koido, Yoshikazu Tomizawa, Toyohiko Takahashi und Takamitsu Kanazawa. „A 69-mΩ 600-V-Class Hybrid JFET“. Materials Science Forum 740-742 (Januar 2013): 925–28. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.925.

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A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

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Wu, Jiale, Houyong Zhou und Yi Chen. „A Novel Super-junction MOSFET with Enhanced Switching Performance and Ruggedness“. Journal of Physics: Conference Series 2524, Nr. 1 (01.06.2023): 012028. http://dx.doi.org/10.1088/1742-6596/2524/1/012028.

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Abstract In this paper, a novel super-junction (SJ) MOSFET with enhanced switching performance and ruggedness is proposed and investigated by the method of TCAD simulations. An N+/P- polysilicon junction gate electrode and separation layer between P-base and P-pillar are introduced to the trench SJ-MOSFET. For the N+/P- junction trench gate, the P- polysilicon located in the bottom of the trench plays the role of insulating layer, which efficiently reduces the gate charge (QG), thus increasing the switching speed and reducing the switching loss. The P-pillar does not contact with P-base so a depletion region is formed and the gate to drain charge (QGD) is reduced. Besides, the specific separation layer also inhibits the activation of the parasitic bipolar transistor (BJT) to improve the unclamped inductive switching (UIS) capability. The results of the simulation reveal that the proposed SJ-MOSFET is better in switching performance and ruggedness.

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Maralani, A., Michael S. Mazzola, David C. Sheridan, Igor Sankin und Volodymyr Bondarenko. „Characterization and Modeling of SiC LTJFET for Analog Integrated Circuit Simulation and Design“. Materials Science Forum 615-617 (März 2009): 915–18. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.915.

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The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

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Yahata, Akihiro, Satoshi Urano, Tomoki Inoue und Takashi Shinohe. „Improvement of Channel Mobility for Trench Metal-Oxide-Semiconductor Field Effect Transistor by Smoothing Trench Sidewall Surface“. Japanese Journal of Applied Physics 40, Part 1, No. 1 (15.01.2001): 116–17. http://dx.doi.org/10.1143/jjap.40.116.

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Ni, Wei, Kenta Emori, Toshiharu Marui, Yuji Saito, Shigeharu Yamagami, Tetsuya Hayashi und Masakatsu Hoshi. „SiC Trench MOSFET with an Integrated Low Von Unipolar Heterojunction Diode“. Materials Science Forum 778-780 (Februar 2014): 923–26. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.923.

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We demonstrate a SiC trench MOSFET with an integrated low Von unipolar heterojunction diode (MOSHJD). A region of the heterojunction diode (HJD) was fabricated in a trench with p+-type poly-crystalline silicon on an n--type epitaxial layer of 4H-SiC. The measured on-resistance (Ron) of the transistor action was 15 mΩcm2. The measured Von of the diode action was 2.2 V at a forward current density of 100 A/cm2. The fabrication process of the MOSHJD is simple. First, the trenches of the MOSFET region and the HJD region are formed simultaneously; then poly-crystalline silicon is deposited to form the gate electrode of the MOSFET region and the anode electrode of the HJD region at the same time.

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Chong, Chen, Hongxia Liu, Shougang Du, Shulong Wang und Hao Zhang. „Study on the Simulation of Biosensors Based on Stacked Source Trench Gate TFET“. Nanomaterials 13, Nr. 3 (28.01.2023): 531. http://dx.doi.org/10.3390/nano13030531.

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In order to detect biomolecules, a biosensor based on a dielectric-modulated stacked source trench gate tunnel field effect transistor (DM-SSTGTFET) is proposed. The stacked source structure can simultaneously make the on-state current higher and the off-state current lower. The trench gate structure will increase the tunneling area and tunneling probability. Technology computer-aided design (TCAD) is used for the sensitivity study of the proposed structured biosensor. The results show that the current sensitivity of the DM-SSTGTFET biosensor can be as high as 108, the threshold voltage sensitivity can reach 0.46 V and the subthreshold swing sensitivity can reach 0.8. As a result of its high sensitivity and low power consumption, the proposed biosensor has highly promising prospects.

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Lee, Hoontaek, Junsoo Kim, Kumjae Shin und Wonkyu Moon. „Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing“. Micromachines 12, Nr. 11 (23.10.2021): 1303. http://dx.doi.org/10.3390/mi12111303.

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We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The I-V characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

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Volcheck, V. S., und V. R. Stempitsky. „Gallium nitride heterostructure field-effect transistor with a heat-removal system based on a trench in the passivation layer filled by a high thermal conductivity material“. Doklady BGUIR 19, Nr. 6 (01.10.2021): 74–82. http://dx.doi.org/10.35596/1729-7648-2021-19-6-74-82.

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The self-heating effect poses a main problem for high-power electronic and optoelectronic devices based on gallium nitride. A non-uniform distribution of the dissipated power and a rise of the average temperature inside the gallium nitride heterostructure field-effect transistor lead to the formation of a hot spot near the conducting channel and result in the degradation of the drain current, output power and device reliability. The purpose of this work is to develop the design of a gallium nitride heterostructure field-effect transistor with an effective heat-removal system and to study using numerical simulation the thermal phenomena specific to this device. The objects of the research are the device structures formed on sapphire, each of whom features both a graphene heat-eliminating element on its top surface and a trench in the passivation layer filled by a high thermal conductivity material. The subject of the research is the electrical and thermal characteristics of these device structures. The simulation results verify the effectiveness of the integration of the heat-removal system into the gallium nitride heterostructure field-effect transistor that can mitigate the self-heating effect and improve the device performance. The advantage of our concept is that the graphene heat-eliminating element is structurally connected with a heat sink and is designed for removing the heat immediately from the maximum temperature area through the trench in which a high thermal conductivity material is deposited. The results can be used by the electronics industry of the Republic of Belarus for developing the hardware components of gallium nitride power electronics.

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Volcheck, V. S., und V. R. Stempitsky. „Large Signal Performance of the Gallium Nitride Heterostructure Field-Effect Transistor With a Graphene Heat-Removal System“. Doklady BGUIR 20, Nr. 1 (01.03.2022): 40–47. http://dx.doi.org/10.35596/1729-7648-2022-20-1-40-47.

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The self-heating effect exerts a considerable influence on the characteristics of high-power electronic and optoelectronic devices based on gallium nitride. An extremely non-uniform distribution of the dissipated power and a rise in the average temperature in the gallium nitride heterostructure field-effect transistor lead to the formation of a hot spot near the conductive channel and result in the degradation of the drain current, power gain and device reliability. The purpose of this work is to design a gallium nitride heterostructure field-effect transistor with an effective graphene heat-removal system and to study using numerical simulation the thermal phenomena specific to it. The object of the research is the device structure formed on sapphire with a grapheme heat-spreading element placed on its top surface and a trench in the passivation layer filled with diamond grown by chemical vapor deposition. The subject of the research is the large signal performance quantities. The simulation results confirm the effectiveness of the heat-removal system integrated into the heterostructure field-effect transistor and leading to the suppression of the self-heating effect and to the improvement of the device performance. The advantage of our concept is that the heat-spreading element is structurally connected with a heat sink and is designed to remove the heat immediately from the maximum temperature area through the trench in which a high thermal conductivity material is deposited. The results of this work can be used by the electronics industry of the Republic of Belarus for developing the hardware components of gallium nitride power electronics.

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Bellini, Marco, und Lars Knoll. „Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs“. Materials Science Forum 1004 (Juli 2020): 865–71. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.865.

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This paper introduces novel TCAD post-processing techniques for SiC MOSFETs with the aim of understanding which parts of the device limit the on-state performance. Typically, analytical models of MOSFETs are used as a starting point for the TCAD design process or as a simple way to understand the influence of complex design choices, as discussed in the works of [1-3]. These lumped element models result in a relatively straightforward approach because they explicitly identify the contributions of the regions of the transistor, facilitating the understanding of basic design choices and performance trade-offs. However, the simplifications introduced in analytical models limit their applicability to advanced device structures such as aggressively scaled transistors or trench MOSFETs with cellular layout. This paper presents mathematical techniques based on post-processing of TCAD simulations that combine the accuracy of numerical Finite Element studies with the interpretability of lumped element analytical models.

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Deng, Xiao Chuan, Hao Zhu, Xuan Li, Xiao Jie Xu, Kun Zhou, Zhi Qiang Li, Song Bai, You Run Zhang und Bo Zhang. „Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs“. Materials Science Forum 1004 (Juli 2020): 837–42. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.837.

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In this paper, avalanche ruggedness of the commercial 1.2kV 45mΩ asymmetric silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is investigated by single-pulse unclamped inductive switching (UIS) test. The avalanche safe operation area (SOA) of the MOSFET is established. The impact of inductance and temperature on avalanche capability is exhibited, which is valuable for many application circuits. The variation in critical avalanche energy with peak avalanche current, peak avalanche current with avalanche time, and temperatures dependence of critical avalanche energy are confirmed.

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