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1
Gay, Roméric. „Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)“. Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.
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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture et le mode de fonctionnement d’un nouveau composant, appelé transistor triple grille, ont été présentés. Sur la base de cette nouvelle architecture, composée de grilles de contrôle indépendantes, différents transistors multigrilles ont été fabriqués. Par la même occasion, leur comportement électrique a été analysé. Dans la continuité, des études de fiabilité, portant notamment sur les oxydes de grilles, ont été menées. L’objectif de ces études a été d’étudier l’impact d’une contrainte électrique, appliquée sur une grille du transistor, sur les autres grilles non soumises à cette même contrainte. Des caractérisations électriques ainsi que des simulations TCAD, ont permis d’améliorer la compréhension des résultats obtenus. Finalement, la structure du transistor triple grille a été modélisée à l’aide d’un modèle compact de transistor de type PSP. Cette modélisation a pour objectif de permettre l’évaluation du comportement et des performances électriques de ce transistor au niveau circuitThe aim of this work is to improve the performance, cost and area of a microcontroller manufactured in a 40 nm CMOS embedded memory technology (eNVM), by developing new transistor architectures suitable for the IoT market. The context is first presented with a focus on the technological and economical limitations of the CMOS technology. In a second part, the eNVM manufacturing process as well as the architecture and operation mode of a new component called triple gate transistor are presented. Based on this new architecture which provides independent control gates, various multigate transistors are manufactured and their electrical behaviour is analysed. Reliability studies are then carried out, to assess the reliability of the gate’s oxides. The objective is to study the impact of an electrical stress applied to one transistor gate on the gates not subject to this same stress. Electrical characterizations and TCAD simulations are also conducted to improve the understanding. Finally, the structure of the triple gate transistor is modelled using a compact PSP transistor model. The aim is to evaluate the behaviour but also the electrical performance of this transistor at the circuit level
2
Forsberg, Markus. „Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing“. Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.
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3
Ramadout, Benoit. „Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives“. Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.
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Les capteurs d'images CMOS ont connu au cours des six dernières années une réduction de la taille des pixels d'un facteur quatre. Néanmoins, cette miniaturisation se heurte à la diminution rapide du signal maximal de chaque pixel et à l'échange parasite entre pixels (diaphotie). C'est dans ce contexte qu'a été développé le Pixel à Tranchées Profondes Capacitives et Grille de Transfert verticale (pixel CDTI+VTG). Basé sur la structure d'un pixel « 4T », il intègre une isolation électrique par tranchées, une photodiode profonde plus volumineuse et une grille verticale permettant le stockage profond et le transfert des électrons. Des procédés de fabrication permettant cette intégration spécifique ont tout d'abord été développés. Parallèlement, une étude détaillée des transistors du pixel, également isolés par CDTI a été menée. Ces tranchées capacitives d'isolation actionnées en tant que grilles supplémentaires ouvrent de nombreuses applications pour un transistor multi-grille compatible avec un substrat massif. Un démonstrateur de 3MPixels intégrant des pixels d'une taille de 1.75*1.75 μm² a été réalisé dans une technologie CMOS 120 nm. Les performances de ce capteur ont pu être déterminées, en particulier en fonction de la tension appliquée aux CDTI. Un bas niveau de courant d'obscurité a tout particulièrement été obtenu grâce à la polarisation électrostatique des tranchées d'isolationCMOS image sensors showed in the last few years a dramatic reduction of pixel pitch. However pitch shrinking is increasingly facing crosstalk and reduction of pixel signal, and new architectures are now needed to overcome those limitations. Our pixel with Capacitive Deep Trench Isolation and Vertical Transfer Gate (CDTI+VTG) has been developed in this context. Innovative integration of polysilicon-filled deep trenches allows high-quality pixel isolation, vertically extended photodiode and deep vertical transfer ability. First, specific process steps have been developed. In parallel, a thorough study of pixel MOS transistors has been carried out. We showed that capacitive trenches can be also operated as extra lateral gates, which opens promising applications for a multi-gate transistor compatible with CMOS-bulk technology. Finally, a 3MPixel demonstrator integrating 1.75*1.75 μm² pixels has been realized in a CMOS 120 nm technology. Pixel performances could be measured and exploited. In particular, a low dark current level could be obtained thanks to electrostatic effect of capacitive isolation trenches
4
Maglie, Rodolphe de. „Modélisation de différentes technologies de transistors bipolaires à grille isolée pour la simulation d'applications en électronique de puissance“. Toulouse 3, 2007. https://tel.archives-ouvertes.fr/tel-00153597.
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L'analyse et la conception des systèmes en électronique de puissance nécessitent la prise en compte de phénomènes complexes propres à chaque composant du système mais aussi en accord avec son environnement. La description précise du comportement d'un système passe par la simulation utilisant des modèles suffisamment précis de tous ces composants. Dans notre étude, les modèles basés sur la physique des semiconducteurs permettent de décrire le comportement de la charge stockée dans la base large et peu dopée des composants bipolaires. Cette description fine est indispensable à la bonne précision de nos modèles car l'évolution des porteurs dans la base est indissociable du comportement en statique et en dynamique du composant. Ainsi, les modèles physiques analytiques de diode PiN mais surtout d'IGBT NPT ou PT, ayant une technologie de grille 'planar' ou à tranchées sont présentés puis validés. La modélisation de systèmes complexes en électronique de puissance est abordée au travers de deux études. La première concerne l'association des modèles de semiconducteurs avec des modèles de la connectique dans un module de puissance du commerce (3300V /1200A). Une analyse sur les déséquilibres en courant entre les différentes puces en parallèle est donnée. La seconde présente une architecture innovante issue de l'intégration fonctionnelle. Cette architecture faibles pertes permet d'améliorer le compromis chute de tension à l'état passant/ énergie de commutation à l'ouverture inhérent aux composants IGBT. Sa réalisation technologique est présentée au travers de mesureAnalysis and systems design in power electronics must taking into account of specific complex phenomena to each components of the system but also in agreement with its environment. Accurate description of a system needs for simulations sufficiently accurate models of all its components. In our study, the models based on the semiconductor physics make it possible to describe the behavior of the stored charge in the deep and low doped base in the bipolar devices. This fine description is essential to the good precision of our models because the evolution of the carriers in the base is indissociable of the in static and dynamic behaviors of the component. Thus, the analytical physical models of PiN diode, NPT or PT IGBT with planar or trench gate structure are presented then validated. The modeling of complex systems in power electronics is approached through two studies. The first deals with to the association of our semiconductor models and wiring model of an industrial power module (3300V /1200A). An analysis on imbalances between the different chips in parallel is given. The second study presents a innovating architecture resulting from the functional integration. This low losses improve the tradeoff between on-state drop voltage and turn-off transient energy in IGBT component. Its technological realization is presented through measurements
5
Ng, Chun Wai. „On the inversion and accumulation layer mobilities in N-channel trench DMOSFETS /“. View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20NG.
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6
Heinle, Ulrich. „Vertical High-Voltage Transistors on Thick Silicon-on-Insulator“. Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-3179.
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More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silicon-on-Insulator (SOI) substrates. MOSFETs possess a number of features which makes them indispensable for Power Integrated Circuits (PICs): high switching speed, high efficiency, and simple drive circuits. SOI substrates combined with trench technology is superior to traditional Junction Isolation (JI) techniques in terms of cross-talk and leakage currents. Vertical DMOS transistors on SOI have been manufactured and characterized, and an analytical model for their on-resistance is presented. A description of self-heating and operation at elevated temperatures is included. Furthermore, the switching dynamics of these components is investigated by means of device simulations with the result that the dissipated power during unclamped inductive switching tests is reduced substantially compared to bulk vertical DMOSFETs. A large number of defects is created in the device layer if the trenches are exposed to high temperatures during processing. A new fabrication process with back-end trench formation is introduced in order to minimize defect generation. In addition, a model for the capacitive coupling between trench-isolated structures is developed.
7
Melul, Franck. „Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration“. Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.
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L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle architecture mémoire a été proposée : la cellule BitErasable. Elle a montré une excellente fiabilité et a permis d’apporter des éléments de compréhension sur les mécanismes de dégradation présents dans ces dispositifs mémoires à transistor de sélection enterré. Cette nouvelle architecture offre de plus la possibilité d’effacer les cellules d’un plan mémoire de façon individuelle : bit à bit. Conscient du grand intérêt que présente l’effacement bit à bit, un nouveau mécanisme d’effacement pour injection de trous chauds a été proposé pour la cellule eSTM. Il a montré des performances et un niveau de fiabilité parfaitement compatible avec les exigences industrielles des applications Flash-NORThe objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications
8
Grimminger, Marsha Loth. „PERIODIC TRENDS IN STRUCTURE FUNCTION RELATIONSHIP OF ORGANIC HETEROACENES“. UKnowledge, 2011. http://uknowledge.uky.edu/gradschool_diss/850.
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Our group has previously shown that small changes to molecular structure result in large changes to device properties and stability in organic electronic applications. By functionalizing aromatic heteroacenes with group 14 and group 16 elements, it is possible to control morphology and improve stability for a variety of applications such as thin film transistors and solar cells. Functionalization within the heteroacene core led to changes in electronic structure as observed by electrochemistry and light absorption. By substituting down the periodic table, the carbon heteroatom bond length increased, leading to subtle changes in crystal packing. Absorption maxima were red-‐shifted and stability to light decreased. Substitution of group 14 elements to the solubilizing ethynyl groups attached to the heteroacene also had an effect on crystallization and stability. Substitution of silicon with carbon decreased solubility as well as stability to light. Substitution with germanium also decreased stability to light, but close contacts within the crystal structure and solubility in nonpolar organic solvents increased.
9
Tavernier, Aurélien. „Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées“. Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.
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Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités.
10
Tai, Shih-Hsiang, und 戴士翔. „Optimal Design of Trench Gate Insulted Gate Bipolar Transistor“. Thesis, 2002. http://ndltd.ncl.edu.tw/handle/99755982922692722594.
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碩士國立臺灣科技大學
電子工程系
90
In recent years, the performance and fabrication of IGBT’s have been significantly improved and the application field of IGBT have widely been expending, especially in high power electronic device. It is reported that the Trench-Gate IGBT has superior characteristics in power loss compared to conventional planar IGBT. In this thesis, the Trench-Gate IGBT has a high power gain, high input impedance, and high switching speed. Due to these advantage, the effort to improve the Trench-Gate IGBT performances operating above 600V and 100A/cm² are the goal in this thesis. We use TSUPREM-4 process simulator and MEDICI device simulator to modulate parameters for increasing operating speed and reducing on-state voltage drop. In order to reduce on-state voltage drop and turn-off time, the doping concentration and the size of each region are needed to modulate for optimization. In the aspect of device characteristic, it is necessary to spend a long time for switching in operating a high current density. Thus, the switching speed of this device will be slow. But, a high operating current density is good for device because that makes the on-state voltage reducing. Therefore, the trade-off between the on-state voltage drop and turn-off time is important to find the optimal parameters for this device.
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HUA, CHEN PING, und 陳秉樺. „Asymmetric Gate with Trench Structure for Juntionless Field-Effect Transistor“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/78037389074916331457.
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碩士國立聯合大學
電子工程學系碩士班
103
This study describes the fabrication of a trench junctionless field-effect transistor (trench JL-FET) and asymmetric gate trench junctionless field-effect transistor (AG trench JL-FET). This study uses the dry oxidation to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL-FET and it could get larger grain size and less grain boundary than directly depositing the thin-film. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device. The sub-threshold swing (SS) is 89mV/decade, and the ION/IOFF current ratio up to 106 due to the excellent gate controllability and ultra-thin channel. The trench JL-FET have a low drain induced barrier lowering (DIBL~0mV/V), indicating greater suppression of the short channel effect than in asymmetric gate JL-FET. Firstly, this work focuses on the device process and basic device characteristics analysis. Next, the reliability analysis of trench JL-FET include high temperature performance, breakdown mechanism and hot carrier stress are investigated in this the analysis.
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Lai, Guan-Fu, und 賴冠甫. „Design of Nanoscale Lateral Trench-Type Tunneling Field-Effect Transistor“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/28823414545853161968.
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碩士國立臺灣科技大學
電子工程系
103
In the progress of the electronics industry, the scaled down of the conventional MOSFET device will emerge some reliability problems, such as short-channel effect, hot-carrier effect, and gate-induced-drain leakage (GIDL). Tunneling Field Effect transistors (TFETs) are semiconductor devices that carry current via inter-band source-to- channel tunneling rather than by carrier transport over the source barrier. In other words, TFET has the immunity from these problems in high scaling fabrication due to its operation mechanism is different from the MOSFET device. Although tunneling-field effect transistors (TFETs) can improve disadvantages of conventional MOSTFT and become very promising candidates for future low power applications, some problems of TFET are still needed to be resolved such as very low on-state current compared to the conventional MOSFETs. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. In this study, there is a newly designed TFET structure called“the trench TFET with n-pocket”. For nanoscale devices, as compared to the planar TFET, the trench TFET with n-pocket can lead to a much smaller off-state current but comparable on-state current, due to the corner effect. Consequently, the trench TFET with n-pocket can be promising for nanoscale integrated-circuit devices.
13
LI, DONG-QI, und 李東奇. „The simulation and modeling of a trench-isolated MOS transistor“. Thesis, 1990. http://ndltd.ncl.edu.tw/handle/91684391077102611194.
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14
Liu, Chu-Kuang, und 劉莒光. „Power Trench Junction Field Effect Transistor Integrated with Schottky Barrier Diode“. Thesis, 2009. http://ndltd.ncl.edu.tw/handle/49020093428820678056.
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碩士國立交通大學
理學院碩士在職專班應用科技學程
97
Nowadays, Power MOSFETs are dominant products of switching converters in the application field of power supply. For high power conversion efficiency and high frequency operating consideration, adopting synchronous buck converter (SBC) design would meet this requirement. However, for the low-side switch device of SBC, there are still some drawback characteristics such as physical limit of on-state resistance of channel, high power loss during the dead time due to the inherent PN body diode etc. In this study, a novel structure of power trench junction field effect transistor (JFET) integrated with Schottky barrier diode (SBD) is the first time being proposed. This design provides a new alternative solution for the low side switch of synchronous buck converter. From the simulation result, we find the larger pitch size of JFET and mesa width of SBD causing higher pinch-off voltage, lower breakdown voltage of drain to source if it was under the same pinch-off voltage. On the other hand, it would result in lower specific on-resistance due to the larger channel width. There is no significant correlation between different mesa widths of Schottky diode and reverse recovery characteristics of diode. The lighter epitaxial doping concentration would get the lower pinch-off voltage. The lower resistively of epitaxial layer is in inverse proportional to breakdown voltage, but is in proportional to on-state resistance of drain to source. This novel structure is achievable for ultra high cell density, competitive on-state resistance, desirable breakdown voltage, excellent low reverse leakage level and lower forward voltage drop. The overall characteristic comparison shows it is a good candidate for switch device of DC-DC convertor application.
15
Lee, Lung-Chieh, und 李龍杰. „Design and Simulation of SiC Dual Trench Accumulation Channel Field Effect Transistor (ACCUFET) Structure“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/87879839116508197352.
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碩士國立臺灣大學
工程科學及海洋工程學研究所
102
To improve the energy conversion efficiency of power electronic systems, it is necessary to reduce the power losses during switching and on-state conduction of power semiconductor devices. SiC power devices are the best candidates because they have excellent material properties for high power density and high temperature applications. Among all sorts of power devices, SiC power MOSFET attracts the most attention because of its high frequency switching capability. However, low channel mobility, high interface state density as well as inferior oxide reliability still remain to be major obstacles to the development of SiC power MOSFET over the years. Therefore, it is imperative for us to overcome these issues. One way is to devise new power device structure. In this thesis, a novel device structure called “dual trench ACCUFET” is proposed. We then simulate its electric performance and fabrication processes by using Silvaco software. After that, we analyze the simulation results and optimize the device’s performance by parameter, such as doping concentration, thickness and width, hoping to design a device exhibiting the breakdown voltage of 1200 volts, the on-resistance under 5 and the threshold voltage between 2 to 4 volts.
16
Lin, Yang-You, und 林揚祐. „Lateral trench-type insulated-gate bipolar transistor triggered by using tunneling-field-effect structure“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/52173970303839533036.
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碩士國立臺灣科技大學
電子工程系
103
The lateral insulated-gate bipolar transistor power device has been proposed that a smaller on-state voltage drop compared with metal-oxide-semiconductor field-effect transistor power device and tunneling-field-effect transistor power device. Because the P+-anode/N- drift junction of the device turn on, the large series resistance in the drift region can be effectively reduced. In this thesis, the results of different gate-positions of planar TFET-IGBT have been discussed, there is a trade-off between the electric field in P+-cathode/N- drift junction and N- drift region. Furthermore, planar TFET-IGBT with removal of P-well and ion implant to form n-pocket can significantly enhance the band-to-band tunneling near the P+-cathode/N- drift junction, and the on-current of the device would be obviously increased. Nevertheless, a large electric field in the depletion region of P+-cathode/N- drift junction would result in breakdown voltage degradation. Therefore, the optimization of the characteristics of planar TFET-IGBT requires a trade-off between forward current and reverse blocking voltage. For improving the blocking voltage of the device, trench-type TFET-IGBT be studied with better breakdown characteristic. It is found that the usage of n-pocket can enhance the electric field of trench-type TFET-IGBT not only near the P+-cathode/N- drift junction but also in N- drift region. As a result, the on-state capability and blocking voltage characteristic of trench-type TFET-IGBT can be obviously improved compared with those of MOS-IGBT.
17
Wang, Yi-Ting, und 王怡婷. „A Design and Analysis of 600V Trench Gate Reverse Conducting Insulated Gate Bipolar Transistor“. Thesis, 2012. http://ndltd.ncl.edu.tw/handle/47047701468172285686.
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碩士國立中央大學
電機工程研究所
100
Most of the development trend of electronic products has always been to achieve high performance and multi-function by consuming more power. In the energy industry equipment used by semiconductor, power semiconductors, the proportion of over 50%. Power semiconductors are widely used in the fields of home appliances, computers, automotive and railway. Since these applications are expected to expand the popularity of the use of power semiconductors has risen, the power semiconductor market will expand year by year growth. With crude oil prices rising year by year, the timing of the development of energy-saving products and energy products in the world is becoming increasingly mature, full propulsion of electric vehicles to replace petrol cars. In power semiconductors, IGBT market scale expanding background is an increase in demand for hybrid and electric cars. Recently, car manufacturers competing yield hybrid plan, and intends to replace the original car''s gasoline hybrid in one fell swoop. Thus more visible IGBT there is enormous potential in the future market development. In recent years, because semiconductor components were integrated and the IGBT modules which paralleled diode were used in circuit applications, Reverse Conducting- IGBT that could combine the IGBT and Diode structure were developed, in order to save the circuit from additional parts. In this paper, I will use the Thin Wafer technology and Field-Sop structure to design 600V RC-IGBT. In addition, I will do a series of research and discussion for how to achieve low on-state voltage, high breakdown voltage and improve the reverse recovery characteristics of RC-IGBT, designing to optimize RC-IGBT. Through the Silvaco software ATHENA and ATLAS simulate component process method and conduct electrical analysis and design, showed the RC-IGBT that has Carried Stored N layer can reach more than 600 V withstand voltage. Compared with the RC-IGBT without Carried Stored N layer , it can effectively improve the on-state voltage about 13% and improve built-in diode reverse recovery performance, that the reverse peak current decreased approximately 0.4A and the reverse recovery charge can reduce more than 17%.
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Wu, Min-Hsin, und 吳明欣. „Study of Ultra-Thin Body Junctionless Poly-Si Fin Field-Effect Transistor with a Trench Structure“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/12621370582891883921.
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碩士國立清華大學
工程與系統科學系
102
In this study, we describe the fabrication of a trench junctionless poly-Si field-effect transistor (trench JL-FET) with 2.4 nm ultra-thin channels. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device. This work use the dry etching to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL FETs and it could get larger grain size and less grain boundary than directly depositing the thin-film. The trench JL-FET has superior SS value about 100 mV dec-1, high ION/IOFF ratio up to 107 and practically negligible DIBL value. To confirm the stable process of trench and potential of advanced CMOS process, we have shown the trench JL-FET with different channel width and gate length. In this study of characteristics analysis, we firstly focus on detail fabricating process and typical electrical characteristics. It’s compare the trench JL-FETs (TCH=2.4nm) with the conventional JL-FETs (TCH=2.4nm). It’s worth to be mentioned that the saturation currents of trench JL-FETs are higher than that of conventional JL-FETs, owing to quantum confinement effect (QCE) in ultra-thin channel. The quantum confinement effect can improve the carrier mobility and electron velocity which is confirmed by TCAD simulation. Next, this work had shown the reliability analysis including high temperature performance and high voltage breakdown mechanism. This study investigated the temperature dependence on ID-VG curves of trench JL-FETs and conventional JL-FETs. The VTH and SS of trench JL-FETs are less sensitive to temperature than that of conventional JL-FETs that maybe due to the single crystal-like channel and fully-depleted state in the ultra-thin channel. Additionally, The trench JL-FET devices exhibit extremely small leakage currents as increasing temperature due to the energy subbands of quantum confinement effect. Finally, the breakdown mechanisms of JL-FETs and inversion mode (IM) FETs with different gate bias condition (on-state and off-state) are discussed completely and confirmed by experimental and simulated results. The simulated results show the maximum electric field of JL-FET is smaller than IM-FET, so the measured breakdown voltage (VBD) of JL device is 73V which is better than that of IM device. the trench JL-FET has a great potential for using in advanced AMLCD, 3D stacked applications, low power consumption applications , system-on-panel and high voltage power MOS devices.
19
Chiu, Hsien-Nan, und 邱憲楠. „Characteristics of a New Trench Oxide Layer Polysilicon Thin-Film Transistor and its 1T-DRAM Applications“. Thesis, 2010. http://ndltd.ncl.edu.tw/handle/62184136431112541817.
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碩士國立中山大學
電機工程學系研究所
98
In this thesis, we propose a simple trench oxide layer polysilicon thin-film Transistor (TO TFT) process and the self-heating effects can be significantly reduced because of its structural advantages. According to the ISE-TCAD simulation results, our proposed TO TFT structure has novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~ 84%) and the retention time (~ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.
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CHO, YU-HSIANG, und 卓裕翔. „A Novel Design of Four-Masks Bottom-Gate Poly-Si Thin Film Transistor and Study of High Voltage Planar-Gate Trench-Source VDMOSFET“. Thesis, 2019. http://ndltd.ncl.edu.tw/handle/dgax22.
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碩士逢甲大學
電子工程學系
107
Most of the early monitors were cathode ray tube(CRT) screens, but cathode ray tubes have the disadvantages of large volume, heavy weight, high radiation and poor image quality. In recent years, with the polycrystalline germanium film transistor Thin Film Transistor(TFT) has a large number of research and structural breakthroughs, and its sophisticated technology is widely used in Active Matrix Liquid Crystal Display(AMLCD) and Three Dimensional-integrated Circuit(3D-IC). Compared with amorphous bismuth thin film transistors, polycrystalline germanium thin film transistors use recrystallization to increase the size of crystal grains and have higher carrier mobility, which allows the use of smaller component sizes, which represents better aperture ratio and higher brightness. The polycrystalline germanium thin film transistor can be divided into a top gate and a bottom gate. Compared with the top gate (TG) polysilicon TFT, since the bottom gate (BG) polysilicon TFT deposits the gate oxide layer and the channel at one time, it has better interface characteristics. And the bottom gate polysilicon film transistor can achieve higher circuit density. However, the conventional BG-TFT requires five masks to complete its process. In order to achieve low-cost manufacturing, many studies have been made to fabricate Poly-Si BG-TFT structures, but no research has been proposed to combine chemical mechanical polishing (CMP) to make the process. Therefore, we propose a " A Novel Design of Four-Masks Bottom-Gate Poly-Si Thin Film Transistor " to achieve the purpose of reducing manufacturing costs, the application of CMP design and ISE TCAD simulation Estimating its characteristics, the new structure designed by our simulation analysis, although its component characteristics are not improved compared with the traditional structure, it reduces the mask in the process compared with the traditional structure, because the implantation are saved. The process of the cloth value and the reticle it requires, although the CMP process is used, the manufacturing cost of the structure can be significantly reduced relative to the conventional structure due to the process steps saved above. In this paper, we use the component simulation software ISE (Integrated System Engineering) to simulate the component process and component design, and simulate the traditional Planar 600V MOSFET structure. From the simulation results, we can find that the traditional 600V MOSFET has a high on-resistance value. Therefore, in order to increase the breakdown voltage and reduce the on-resistance, and not completely adopt the Super-junction design, a new structure is proposed. However, this structure is not easy to manufacture from the analysis of the process, because it is necessary to dig the trench. After the trough, P-type ion implantation is performed twice to form a columnar region (Pillar), and the dose and energy of the implant need to be changed according to the resistance value of the drift zone. Going to the required location is also a big problem. Therefore, in order to improve the process difficulty of the component, we proposed " Study of High Voltage Planar-Gate Trench-Source VDMOSFET ", which replaces the Pillar region of the original structure by increasing the depth of the trench. Modulate the data of each component of the component, analyze the trend of component characteristics change, and use double-layer epi to further reduce the on-resistance. Although the performance of the breakdown voltage value is slightly worse than the structure proposed by others under the same epi parameter. A little bit, but the process difficulty is relatively reduced a lot, and compared with the traditional structure, the proposed structure is much improved in characteristics.
21
Liao, Li-Feng, und 廖麗鳳. „Structure Design of Trench Type Insulated-Gate Bipolar Transistors“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/44730090880226936125.
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碩士國立臺灣科技大學
電子工程系
102
Power devices act as a switch to control the power delivered to the load. In this thesis, a novel trench-type insulated-gate bipolar transistor device has been proposed without p-n-p-n latch-up phenomenon, which shows better characteristics as compared with the conventional trench-gate power MOSFET. Moreover, by using the design of device structure and/or fabrication process to enhance the band-to-band tunneling or increase the electric field in drift region, the on-current of the trench-gate TFET-IGBT can be effectively improved. Accordingly, proper p+ source implantation profile and trench-gate dimension can be employed to optimize the electrical characteristics. As a result, the trench-gate TFET-IGBT is capable of causing smaller on-resistance than the conventional trench-gate power MOSFET, with avoiding the latch-up problem in the conventional trench-gate MOSFET-IGBT.
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Liu, Hsu-Tang, und 劉旭唐. „Investigations of Rounding Corner Trench Structure for Organic Thin Film Transistors“. Thesis, 2013. http://ndltd.ncl.edu.tw/handle/43347580576415006054.
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碩士國立暨南國際大學
電機工程學系
102
In this work, the organic thin film transistors (OTFTs) with periodical groove channels were fabricated by nano imprint lithography (NIL) technology. The periodical groove channels with sharp and rounded corners were first fabricated. Then, the device performances with various periods and different morphologies of groove channels were studied. The periodical groove channels were fabricated, on n+-Si substrate, by nano imprint technology. The sharp corners were rounded by thermal oxidation. Then the dielectric layers, HfO2/SiO2, were deposited by MOCVD and thermal oxidation on the periodical groove channels. The pentacene and S/D electrode (Au) were deposited by thermal evaporation. The groove channels cross-section and the pentacene surface morphology was investigated by scanning electron microscope (SEM) and atomic force microscope (AFM), respectively. As the results, the groove channels with the various periods and different morphologies were fabricated successfully. The transfer characteristic and electrical outputs of OTFTs are all improved with periodical grooves and rounded corners.
23
Lin, Ko Wei, und 林个惟. „Study of Trench Junctionless Fin Field-Effect Transistors with Different Gate Structure“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/dv4bx4.
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碩士國立清華大學
工程與系統科學系
103
With the development of Moore's Law, short channel effect (SCE) has been always a serious issue for CMOS technology. This study, we describe the fabrication of a trench junctionless poly-Si fin field-effect transistor (trench JL-FET) to further improve short channel effect. This trench JL Fin-FET enhances the gate control over its silicon channel. The trench JL Fin-FET can easily to form the ultra-thin channel thickness (TCH) and control the gate length (LG) by dry etching. And, having the heavily doping channel and source/drain (S/D) regions, the SCE in JL-FET can be suppressed. Even if JL-FET requires the ultra-thin channel thickness to lead to the fully-depletion condition that would make the JL-FET turns off, the trench structure can easily integrated into the JL-FET device. In the past, if we want to manufacture ultra-thin channel usually directly depositing the thin-film as the poly-Si channel. And now we use the dry etching to form the ultra-thin channel in JL FETs and it could get larger grain size and less grain boundary than directly depositing the thin-film. In this study of characteristics analysis, the trench JL-FET has superior SS value about 111 mV dec-1, high ION/IOFF ratio up to 108 and practically negligible DIBL value. Trench JL Fin-FET with gated raised source/drain relieves drain-induced barrier lowering (DIBL) effect and channel length modulation effect. In addition, at a high voltage operation (over flat-band voltage of JL device), trench JL Fin-FET with gated raised source/drain reveals a low parasitic S/D resistance due to the formation of an accumulation layer at S/D, which is suit for multi-gate-oxide applications. Importantly, this trench JL Fin-FET along with simple fabrication is highly favorable for advanced system-on-chip (SOC), low power consumption applications and three-dimensional (3-D) stacked ICs applications.
24
Wang, Cheng Ping, und 王政平. „Study of Hybrid Poly-Si Channel Junctionless Fin Field-Effect Transistors with Trench Structure“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/j4867d.
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碩士國立清華大學
工程與系統科學系
103
Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. The rapid development in electronic industries has led to considerable increases in consumer’s purchasing desire, and triggered electronics industry to improve its products. However, the expectation of transistors in scaling suffered more and more difficult to design, whether the short channel effect in devices or the challenge of process are very important research issues. In this thesis, the hybrid junctionless field-effect-transistors with trench structure are proposed and fabricated; the special fabrication of junctionless is the same doping concentration and doping type in channel, source, and drain, so the channel to source and the channel to drain have no junction. And these devices can avoid the short channel effects and simplify the fabrication compared to inversion mode transistors. The hybrid structure makes the thinner effective channel thickness owing to the depletion layer by the channel and substrate; it can easily fabricate devices on the bulk Si wafer and keep the good electrical characteristics. Then, the trench structure improves the ability of gate control owing to the thin channel by the anisotropic etching process. In the fabrication, the annealing after depositing the thick amorphous silicon gets the larger poly silicon grain size, and it also can improve the active area film quality; finally, it achieves the thin trench channel by the reactive-ion etching process. The hybrid poly silicon channel junctionless field-effect-transistors with trench structure have ten nanowires with omega gate structure. The performance of the hybrid junctionless field-effect-transistors with trench structure is excellent with the small sub-threshold swing (SS) (109mV/dec.), the high current ratio (Ion/Ioff current ratio > 108), and negligible DIBL (9mV/V); then, discuss the electrical characteristics in variable temperature with every 25oC as a step from the 25oC to 200oC, analyze those devices by using the Arrhenius sweeps. Finally, the last result shows the TCAD simulation to assist the analysis and confirms the measured basic electric characteristics. The proposed hybrid JL-FETs with trench structure not only the easy fabrication but also the good characteristics are highly promising for use in advanced system-on-chip and 3D stacked ICs applications.
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Cheng, Che Hsiang, und 鄭哲翔. „Hybrid p-Channel Poly-Si Junctionless Field-Effect Transistors with Trench and Gate-All-Around Structure“. Thesis, 2016. http://ndltd.ncl.edu.tw/handle/44388217998306619184.
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碩士國立清華大學
工程與系統科學系
104
Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. as the feature size of logic device has been scaled continuously, conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as random dopant fluctuation, physical limitation and short channel effect (SCE). Junctionless FET is the one of the solution in the future devices. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FE has a slight (SCEs) and less thermal budget in process of fabrication. In this thesis, hybrid p-channel poly-Si Junctionless field-effect transistors with trench and gate-all-around structure are proposed and fabricated. The hybrid structure makes the thinner effective channel thickness owing to the depletion layer by the channel and substrate. Besides, the annealing after depositing the thick amorphous silicon and use the anisotropic reactive ion etch to form the polycrystalline silicon (poly-Si) UTB. The RIE thinning process could get larger grain size and less grain boundary than directly depositing the thin-film. After RIE thinning process, the nanowires look like the trench structure and the raise S/D structure is completed at the same time.. In addition, gate-all-around (GAA) structure combine with UTB could improve gate control ability, which improve sub-threshold swing (SS) and reduce OFF-state leakage current. The hybrid poly silicon channel junctionless field-effect-transistors with trench structure have ten nanowires with gate-all-around structure. The performance of the device is excellent with the steep sub-threshold swing (SS) (136mV/dec.), the high current ratio (Ion/Ioff current ratio>106), and lower DIBL (60mV/V); then, discuss the electrical characteristics in variable temperature with every 25oC as a step from the 50oC to 200oC, finally, we use Sentaurus TCAD to compare trench structure with without trench structure, the result shows use trench structure can get higher ION/IOFF ratio than without trench structure. The proposed hybrid JL-FETs with trench structure not only the easy fabrication but also has the good characteristics for advanced low power consumption applications and three-dimensional (3-D) stacked ICs applications.
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Du, Yan-Ting, und 杜衍廷. „Analysis of Sub-5 nm Transistors Trend by 3D TCAD Simulation“. Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2ec8c9.
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27
Chen, Chi-Fu, und 陳淇富. „Optimization of the Gate - Drain Capacitance to Improve the Switching Performance of Trench Power Metal-Oxide-Semiconductor Field-Effect Transistors“. Thesis, 2012. http://ndltd.ncl.edu.tw/handle/59181487297802687295.
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碩士國立交通大學
工學院半導體材料與製程設備學程
100
Power MOSFETs are widely used as a switching device for high frequency and low voltage (<200 V) power converter. The switching rate depends on charging and discharging performance of the gate capacitor. Low gate - drain charge and low on-resistance can reduce switching power loss and thus improve the device performance. Many approaches have been developed to increase the unit cell density to reduce the on-resistance in trench type power MOSFETs, but the switching will become slower while the gate parasitic capacitance increases. This thesis presents the investigation on narrowing the trench width to reduce the gate - drain capacitance. For the sake of cost considerations, the i-line stepper was used for the wafer production process instead of deep-UV stepper, therefore the trench width was limited by the lithography resolution. After the first step of hard mask etching, a TEOS thin film was deposited on the edge of the hard mask region to form a sidewall spacer, which defined the second hard mask for bulk etching. The spacer could narrow the width of the etched trench to 0.15 ?慆. Combining precise control of ion implantation and furnace drive-in processes for the P-WELL region, optimization of the trench width and depth using the new hard mask approach can effective reduce the gate – drain capacitance, and thus the feedback capacitance of the MOSFET.