Thematische Bibliographien / Trench transistor

Inhaltsverzeichnis

Zeitschriftenartikel
Dissertationen
Bücher
Buchteile
Konferenzberichte

Auswahl der wissenschaftlichen Literatur zum Thema „Trench transistor“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

Geben Sie eine Quelle nach APA, MLA, Chicago, Harvard und anderen Zitierweisen an

Wählen Sie eine Art der Quelle aus:

Machen Sie sich mit den Listen der aktuellen Artikel, Bücher, Dissertationen, Berichten und anderer wissenschaftlichen Quellen zum Thema "Trench transistor" bekannt.

Neben jedem Werk im Literaturverzeichnis ist die Option "Zur Bibliographie hinzufügen" verfügbar. Nutzen Sie sie, wird Ihre bibliographische Angabe des gewählten Werkes nach der nötigen Zitierweise (APA, MLA, Harvard, Chicago, Vancouver usw.) automatisch gestaltet.

Sie können auch den vollen Text der wissenschaftlichen Publikation im PDF-Format herunterladen und eine Online-Annotation der Arbeit lesen, wenn die relevanten Parameter in den Metadaten verfügbar sind.

Zeitschriftenartikel zum Thema "Trench transistor"

Shichijo, H., S. K. Banerjee, S. D. S. Malhi, G. P. Pollack, W. F. Richardson, D. M. Bordelon, R. H. Womack et al. „Trench transistor DRAM cell“. IEEE Electron Device Letters 7, Nr. 2 (Februar 1986): 119–21. http://dx.doi.org/10.1109/edl.1986.26313.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Gupta, Aakashdeep, K. Nidhin, Suresh Balanethiram, Shon Yadav, Anjan Chakravorty, Sebastien Fregonese und Thomas Zimmer. „Static Thermal Coupling Factors in Multi-Finger Bipolar Transistors: Part I—Model Development“. Electronics 9, Nr. 9 (19.08.2020): 1333. http://dx.doi.org/10.3390/electronics9091333.

Der volle Inhalt der Quelle

Annotation:

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Banerjee, S., und D. M. Bordelon. „A model for the trench transistor“. IEEE Transactions on Electron Devices 34, Nr. 12 (Dezember 1987): 2485–92. http://dx.doi.org/10.1109/t-ed.1987.23339.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mukherjee, Kalparupa, Carlo De Santi, Matteo Borga, Karen Geens, Shuzhen You, Benoit Bakeroot, Stefaan Decoutere et al. „Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization“. Materials 14, Nr. 9 (29.04.2021): 2316. http://dx.doi.org/10.3390/ma14092316.

Der volle Inhalt der Quelle

Annotation:

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Dai, Tian Xiang, A. B. Renz, Luyang Zhang, Oliver J. Vavasour, G. W. C. Baker, Vishal Ajit Shah, Philip A. Mawby und Peter M. Gammon. „Design and Optimisation of Schottky Contact Integration in a 4H-SiC Trench MOSFET“. Materials Science Forum 1004 (Juli 2020): 808–13. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.808.

Der volle Inhalt der Quelle

Annotation:

Planar Schottky contact and various trench Schottky contacts have been integrated into the edge termination region of a 4H-SiC trench metal-oxide-semiconductor field-effect-transistor (MOSFET). The forward and reverse characteristics of various design splits have been benchmarked to determine the optimum method of the Schottky contact integration. As a result, the trench Schottky diode with Schottky metal contact in both the planar surface and the trench sidewall surface has been able to offer the best performance.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Chen, Q., B. You, A. Q. Huang und J. K. O. Sin. „A new trench base-shielded bipolar transistor“. IEEE Transactions on Electron Devices 47, Nr. 8 (2000): 1662–66. http://dx.doi.org/10.1109/16.853045.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Wang, Bo. „Analysis of base characteristics of trench gate field termination IGBT“. E3S Web of Conferences 237 (2021): 02023. http://dx.doi.org/10.1051/e3sconf/202123702023.

Der volle Inhalt der Quelle

Annotation:

Trench gate structure represents the latest structure of Insulated Gate Bipolar Transistor(IGBT). Because there are great differences in model analysis coordinate system and carrier transport between trench gate structure and planar gate structure, the modeling method using planar gate structure will inevitably have great deviation. Based on the characteristics of trench gate structure and model analysis coordinate system, the base region is divided into PNP and PIN by considering the two-dimensional effect of carriers. According to whether the trench of PIN part can be covered by depletion layer of PNP part, the specific base region current is analyzed. Finally, simulation and experimental verification are carried out.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Manosukritkul, Phasapon, Amonrat Kerdpardist, Montree Saenlamool, Ekalak Chaowicharat, Amporn Poyai und Wisut Titiroongruang. „An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer“. Advanced Materials Research 717 (Juli 2013): 158–63. http://dx.doi.org/10.4028/www.scientific.net/amr.717.158.

Der volle Inhalt der Quelle

Annotation:

In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakdown voltage increased by approximately 30% compared with conventional NPT-TIGBT.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Yang, Ling Ling. „A Novel Structure Trench IGBT with Full Hole-Barrier Layer“. Applied Mechanics and Materials 543-547 (März 2014): 757–61. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.757.

Der volle Inhalt der Quelle

Annotation:

A Full Hole-barrier Trench gate Insulated Gate Bipolar Transistor (FH-TIGBT) device structure is proposed for the first time. Compared with Carrier Stored Trench IGBT (CSTBT), which adds a carrier stored n layer between p base and n base in Trench IGBT (TIGBT), the new structure appends an n region located in the bottom of the trench gate. The result of Process and device simulations shows that the proposed device has lowered saturation voltage and larger capability of carrying current compared to either conventional trench IGBT or CSTBT. And the characteristics of turn-off time and breakdown voltage have negligibly changed. Further more, it has strongly positive temperature coefficient of on-state voltage, which means paralleling is very simple for the new device.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Hung, Chia Lung, Yi Kai Hsiao, Chang Ching Tu und Hao Chung Kuo. „Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications“. Materials Science Forum 1088 (18.05.2023): 41–49. http://dx.doi.org/10.4028/p-56sbi2.

Der volle Inhalt der Quelle

Annotation:

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mehr Quellen

Dissertationen zum Thema "Trench transistor"

Gay, Roméric. „Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)“. Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

Der volle Inhalt der Quelle

Annotation:

L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture et le mode de fonctionnement d’un nouveau composant, appelé transistor triple grille, ont été présentés. Sur la base de cette nouvelle architecture, composée de grilles de contrôle indépendantes, différents transistors multigrilles ont été fabriqués. Par la même occasion, leur comportement électrique a été analysé. Dans la continuité, des études de fiabilité, portant notamment sur les oxydes de grilles, ont été menées. L’objectif de ces études a été d’étudier l’impact d’une contrainte électrique, appliquée sur une grille du transistor, sur les autres grilles non soumises à cette même contrainte. Des caractérisations électriques ainsi que des simulations TCAD, ont permis d’améliorer la compréhension des résultats obtenus. Finalement, la structure du transistor triple grille a été modélisée à l’aide d’un modèle compact de transistor de type PSP. Cette modélisation a pour objectif de permettre l’évaluation du comportement et des performances électriques de ce transistor au niveau circuit
The aim of this work is to improve the performance, cost and area of a microcontroller manufactured in a 40 nm CMOS embedded memory technology (eNVM), by developing new transistor architectures suitable for the IoT market. The context is first presented with a focus on the technological and economical limitations of the CMOS technology. In a second part, the eNVM manufacturing process as well as the architecture and operation mode of a new component called triple gate transistor are presented. Based on this new architecture which provides independent control gates, various multigate transistors are manufactured and their electrical behaviour is analysed. Reliability studies are then carried out, to assess the reliability of the gate’s oxides. The objective is to study the impact of an electrical stress applied to one transistor gate on the gates not subject to this same stress. Electrical characterizations and TCAD simulations are also conducted to improve the understanding. Finally, the structure of the triple gate transistor is modelled using a compact PSP transistor model. The aim is to evaluate the behaviour but also the electrical performance of this transistor at the circuit level

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Forsberg, Markus. „Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing“. Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Ramadout, Benoit. „Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives“. Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.

Der volle Inhalt der Quelle

Annotation:

Les capteurs d'images CMOS ont connu au cours des six dernières années une réduction de la taille des pixels d'un facteur quatre. Néanmoins, cette miniaturisation se heurte à la diminution rapide du signal maximal de chaque pixel et à l'échange parasite entre pixels (diaphotie). C'est dans ce contexte qu'a été développé le Pixel à Tranchées Profondes Capacitives et Grille de Transfert verticale (pixel CDTI+VTG). Basé sur la structure d'un pixel « 4T », il intègre une isolation électrique par tranchées, une photodiode profonde plus volumineuse et une grille verticale permettant le stockage profond et le transfert des électrons. Des procédés de fabrication permettant cette intégration spécifique ont tout d'abord été développés. Parallèlement, une étude détaillée des transistors du pixel, également isolés par CDTI a été menée. Ces tranchées capacitives d'isolation actionnées en tant que grilles supplémentaires ouvrent de nombreuses applications pour un transistor multi-grille compatible avec un substrat massif. Un démonstrateur de 3MPixels intégrant des pixels d'une taille de 1.75*1.75 μm² a été réalisé dans une technologie CMOS 120 nm. Les performances de ce capteur ont pu être déterminées, en particulier en fonction de la tension appliquée aux CDTI. Un bas niveau de courant d'obscurité a tout particulièrement été obtenu grâce à la polarisation électrostatique des tranchées d'isolation
CMOS image sensors showed in the last few years a dramatic reduction of pixel pitch. However pitch shrinking is increasingly facing crosstalk and reduction of pixel signal, and new architectures are now needed to overcome those limitations. Our pixel with Capacitive Deep Trench Isolation and Vertical Transfer Gate (CDTI+VTG) has been developed in this context. Innovative integration of polysilicon-filled deep trenches allows high-quality pixel isolation, vertically extended photodiode and deep vertical transfer ability. First, specific process steps have been developed. In parallel, a thorough study of pixel MOS transistors has been carried out. We showed that capacitive trenches can be also operated as extra lateral gates, which opens promising applications for a multi-gate transistor compatible with CMOS-bulk technology. Finally, a 3MPixel demonstrator integrating 1.75*1.75 μm² pixels has been realized in a CMOS 120 nm technology. Pixel performances could be measured and exploited. In particular, a low dark current level could be obtained thanks to electrostatic effect of capacitive isolation trenches

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Maglie, Rodolphe de. „Modélisation de différentes technologies de transistors bipolaires à grille isolée pour la simulation d'applications en électronique de puissance“. Toulouse 3, 2007. https://tel.archives-ouvertes.fr/tel-00153597.

Der volle Inhalt der Quelle

Annotation:

L'analyse et la conception des systèmes en électronique de puissance nécessitent la prise en compte de phénomènes complexes propres à chaque composant du système mais aussi en accord avec son environnement. La description précise du comportement d'un système passe par la simulation utilisant des modèles suffisamment précis de tous ces composants. Dans notre étude, les modèles basés sur la physique des semiconducteurs permettent de décrire le comportement de la charge stockée dans la base large et peu dopée des composants bipolaires. Cette description fine est indispensable à la bonne précision de nos modèles car l'évolution des porteurs dans la base est indissociable du comportement en statique et en dynamique du composant. Ainsi, les modèles physiques analytiques de diode PiN mais surtout d'IGBT NPT ou PT, ayant une technologie de grille 'planar' ou à tranchées sont présentés puis validés. La modélisation de systèmes complexes en électronique de puissance est abordée au travers de deux études. La première concerne l'association des modèles de semiconducteurs avec des modèles de la connectique dans un module de puissance du commerce (3300V /1200A). Une analyse sur les déséquilibres en courant entre les différentes puces en parallèle est donnée. La seconde présente une architecture innovante issue de l'intégration fonctionnelle. Cette architecture faibles pertes permet d'améliorer le compromis chute de tension à l'état passant/ énergie de commutation à l'ouverture inhérent aux composants IGBT. Sa réalisation technologique est présentée au travers de mesure
Analysis and systems design in power electronics must taking into account of specific complex phenomena to each components of the system but also in agreement with its environment. Accurate description of a system needs for simulations sufficiently accurate models of all its components. In our study, the models based on the semiconductor physics make it possible to describe the behavior of the stored charge in the deep and low doped base in the bipolar devices. This fine description is essential to the good precision of our models because the evolution of the carriers in the base is indissociable of the in static and dynamic behaviors of the component. Thus, the analytical physical models of PiN diode, NPT or PT IGBT with planar or trench gate structure are presented then validated. The modeling of complex systems in power electronics is approached through two studies. The first deals with to the association of our semiconductor models and wiring model of an industrial power module (3300V /1200A). An analysis on imbalances between the different chips in parallel is given. The second study presents a innovating architecture resulting from the functional integration. This low losses improve the tradeoff between on-state drop voltage and turn-off transient energy in IGBT component. Its technological realization is presented through measurements

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Ng, Chun Wai. „On the inversion and accumulation layer mobilities in N-channel trench DMOSFETS /“. View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20NG.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Heinle, Ulrich. „Vertical High-Voltage Transistors on Thick Silicon-on-Insulator“. Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-3179.

Der volle Inhalt der Quelle

Annotation:

More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silicon-on-Insulator (SOI) substrates. MOSFETs possess a number of features which makes them indispensable for Power Integrated Circuits (PICs): high switching speed, high efficiency, and simple drive circuits. SOI substrates combined with trench technology is superior to traditional Junction Isolation (JI) techniques in terms of cross-talk and leakage currents. Vertical DMOS transistors on SOI have been manufactured and characterized, and an analytical model for their on-resistance is presented. A description of self-heating and operation at elevated temperatures is included. Furthermore, the switching dynamics of these components is investigated by means of device simulations with the result that the dissipated power during unclamped inductive switching tests is reduced substantially compared to bulk vertical DMOSFETs. A large number of defects is created in the device layer if the trenches are exposed to high temperatures during processing. A new fabrication process with back-end trench formation is introduced in order to minimize defect generation. In addition, a model for the capacitive coupling between trench-isolated structures is developed.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Melul, Franck. „Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration“. Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.

Der volle Inhalt der Quelle

Annotation:

L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle architecture mémoire a été proposée : la cellule BitErasable. Elle a montré une excellente fiabilité et a permis d’apporter des éléments de compréhension sur les mécanismes de dégradation présents dans ces dispositifs mémoires à transistor de sélection enterré. Cette nouvelle architecture offre de plus la possibilité d’effacer les cellules d’un plan mémoire de façon individuelle : bit à bit. Conscient du grand intérêt que présente l’effacement bit à bit, un nouveau mécanisme d’effacement pour injection de trous chauds a été proposé pour la cellule eSTM. Il a montré des performances et un niveau de fiabilité parfaitement compatible avec les exigences industrielles des applications Flash-NOR
The objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Grimminger, Marsha Loth. „PERIODIC TRENDS IN STRUCTURE FUNCTION RELATIONSHIP OF ORGANIC HETEROACENES“. UKnowledge, 2011. http://uknowledge.uky.edu/gradschool_diss/850.

Der volle Inhalt der Quelle

Annotation:

Our group has previously shown that small changes to molecular structure result in large changes to device properties and stability in organic electronic applications. By functionalizing aromatic heteroacenes with group 14 and group 16 elements, it is possible to control morphology and improve stability for a variety of applications such as thin film transistors and solar cells. Functionalization within the heteroacene core led to changes in electronic structure as observed by electrochemistry and light absorption. By substituting down the periodic table, the carbon heteroatom bond length increased, leading to subtle changes in crystal packing. Absorption maxima were red-‐shifted and stability to light decreased. Substitution of group 14 elements to the solubilizing ethynyl groups attached to the heteroacene also had an effect on crystallization and stability. Substitution of silicon with carbon decreased solubility as well as stability to light. Substitution with germanium also decreased stability to light, but close contacts within the crystal structure and solubility in nonpolar organic solvents increased.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Tavernier, Aurélien. „Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées“. Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.

Der volle Inhalt der Quelle

Annotation:

Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Tai, Shih-Hsiang, und 戴士翔. „Optimal Design of Trench Gate Insulted Gate Bipolar Transistor“. Thesis, 2002. http://ndltd.ncl.edu.tw/handle/99755982922692722594.

Der volle Inhalt der Quelle

Annotation:

碩士
國立臺灣科技大學
電子工程系
90
In recent years, the performance and fabrication of IGBT’s have been significantly improved and the application field of IGBT have widely been expending, especially in high power electronic device. It is reported that the Trench-Gate IGBT has superior characteristics in power loss compared to conventional planar IGBT. In this thesis, the Trench-Gate IGBT has a high power gain, high input impedance, and high switching speed. Due to these advantage, the effort to improve the Trench-Gate IGBT performances operating above 600V and 100A/cm² are the goal in this thesis. We use TSUPREM-4 process simulator and MEDICI device simulator to modulate parameters for increasing operating speed and reducing on-state voltage drop. In order to reduce on-state voltage drop and turn-off time, the doping concentration and the size of each region are needed to modulate for optimization. In the aspect of device characteristic, it is necessary to spend a long time for switching in operating a high current density. Thus, the switching speed of this device will be slow. But, a high operating current density is good for device because that makes the on-state voltage reducing. Therefore, the trade-off between the on-state voltage drop and turn-off time is important to find the optimal parameters for this device.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mehr Quellen

Bücher zum Thema "Trench transistor"

Bi, Zhenxing. Shallow Trench Isolation Recess Process Flow for Vertical Field Effect Transistor Fabrication: United States Patent 9985021. Independently Published, 2020.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Buchteile zum Thema "Trench transistor"

Bharti, Deepshikha, und Aminul Islam. „U-Shaped Gate Trench Metal Oxide Semiconductor Field Effect Transistor: Structures and Characteristics“. In Nanoscale Devices, 69–90. Boca Raton : Taylor & Francis, a CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa, plc, 2019.: CRC Press, 2018. http://dx.doi.org/10.1201/9781315163116-4.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Erlbacher, Tobias. „Lateral Power Transistors with Trench Patterns“. In Power Systems, 133–51. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-00500-3_7.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Dyakonov, M. I., und M. S. Shur. „Field Effect Transistor as Electronic Flute“. In Future Trends in Microelectronics, 251–61. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-1746-0_22.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Horowitz, G. „Organic Transistors — Present and Future“. In Future Trends in Microelectronics, 315–26. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-1746-0_28.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Ghannam, M., J. Nijs und R. Mertens. „Trends in Heterojunction Silicon Bipolar Transistors“. In Ultra-Fast Silicon Bipolar Technology, 111–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 1988. http://dx.doi.org/10.1007/978-3-642-74360-3_7.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Erlbacher, Tobias. „Lateral Power Transistors Combining Planar and Trench Gate Topologies“. In Power Systems, 153–75. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-00500-3_8.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

de Castro, Ana Cristina Honorato, Suchismita Guha und Wendel Andrade Alves. „Organic Electrochemical Transistors in Bioanalytical Chemistry“. In Tools and Trends in Bioanalytical Chemistry, 305–12. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-82381-8_16.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mastrapasqua, M., C. A. King, P. R. Smith und M. R. Pinto. „Charge Injection Transistor and Logic Elements in Si/Si1−xGex Heterostructures“. In Future Trends in Microelectronics, 377–83. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-1746-0_34.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Zaumseil, Jana. „Recent Trends in Light-Emitting Organic Field-Effect Transistors“. In Organic Electronics, 187–213. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2013. http://dx.doi.org/10.1002/9783527650965.ch08.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Manju, C. S., N. Poovizhi und R. Rajkumar. „Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic“. In Emerging Trends in Computing and Expert Technology, 48–61. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32150-5_5.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Konferenzberichte zum Thema "Trench transistor"

Zhang, Jinping, Pengjiao Wang, Rongrong Zhu, Xiang Xiao, Zehong Li und Bo Zhang. „High Performance Carrier Stored Trench Bipolar Transistor with Shield Emitter Trench“. In 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2020. http://dx.doi.org/10.1109/icsict49897.2020.9278308.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Richardson, W. F., D. M. Bordelon, G. P. Pollack, A. H. Shah, S. D. S. Malhi, H. Shichijo, S. K. Banerjee et al. „A trench transistor cross-point DRAM cell“. In 1985 International Electron Devices Meeting. IRE, 1985. http://dx.doi.org/10.1109/iedm.1985.191075.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Chen, Q., und J. K. O. Sin. „A new trench base-shielded bipolar transistor“. In Proceedings of International Symposium on Power Semiconductor Devices and IC's. IEEE, 1998. http://dx.doi.org/10.1109/ispsd.1998.702661.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Ruprecht, Michael W., Shengmin Wen und Rolf-P. Vollertsen. „Sample Preparation for Vertical Transistors in DRAM“. In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0307.

Der volle Inhalt der Quelle

Annotation:

Abstract This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) milling and selective wet chemical etching to expose both gates of the transistor simultaneously. Gate oxide pinholes are decorated by the wet etch to allow efficient inspection in a secondary electron microscope (SEM).

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Spulber, O. „The Trench Planar Insulated Gate Bipolar Transistor (TPIGBT)“. In IEE Colloquium Recent Advances in Power Devices. IEE, 1999. http://dx.doi.org/10.1049/ic:19990603.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Sakao, Takaishi, Kajiyana, Akimoto, Oguro, Shishiguchi und Ohya. „A Straight-Line-Trench Isolation And Trench-Gate Transistor (SLIT) Cell For Giga-bit DRAMs“. In Symposium on VLSI Technology. IEEE, 1993. http://dx.doi.org/10.1109/vlsit.1993.760224.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Pronin, Nick, Stefano Larentis, Carey Wu, Eric Foote, Gary Clark, Khiem Ly, Jacob Levenson et al. „Multilayer pFIB Trenches for Multiple Tip EBAC/EBIRCH Analysis and Internal Node Transistor Characterization“. In ISTFA 2023. ASM International, 2023. http://dx.doi.org/10.31399/asm.cp.istfa2023p0403.

Der volle Inhalt der Quelle

Annotation:

Abstract In this work, we present three case studies that highlight the novelty and effectiveness of using multiple plasma FIB trenches to simultaneously access multiple metal layers for nanoprobing failure analysis. Multilayer access enabled otherwise impossible two-tip current imaging techniques and allowed us to fully characterize suspect logic gate transistors by exposing internal nodes, while preserving higher metal inputs and outputs. The presented case studies focus on late node planar and established FinFET technologies. The delayering techniques used are not necessarily technology dependent, but highly scaled and advanced processes generally require smaller trench areas for multilayer access. The minimum trench dimensions are limited by ion beam imaging resolution and trench-nanoprobe tip geometry.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Chang, H. R., B. J. Baliga, J. W. Kretchmer und P. A. Piacente. „"Insulated gate bipolar transistor (IGBT) with a trench gate structure "“. In 1987 International Electron Devices Meeting. IRE, 1987. http://dx.doi.org/10.1109/iedm.1987.191518.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Hieda, K., F. Horigu, H. Watanabe, K. Sunouchi, I. Inoue und T. Hamamoto. „New effects of trench isolated transistor using side-wall gates“. In 1987 International Electron Devices Meeting. IRE, 1987. http://dx.doi.org/10.1109/iedm.1987.191536.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Dhar, Palasri, Souman Bej, Sunipa Roy und Soumik Poddar. „Biosensing attributes of Trench Double Gate Junctionless Field Effect Transistor“. In 2023 IEEE Devices for Integrated Circuit (DevIC). IEEE, 2023. http://dx.doi.org/10.1109/devic57758.2023.10134820.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Wir bieten Rabatte auf alle Premium-Pläne für Autoren, deren Werke in thematische Literatursammlungen aufgenommen wurden. Kontaktieren Sie uns, um einen einzigartigen Promo-Code zu erhalten!