Thematische Bibliographien / Software analysis and verification

Inhaltsverzeichnis

Zeitschriftenartikel
Dissertationen
Bücher
Buchteile
Konferenzberichte
Berichte der Organisationen

Auswahl der wissenschaftlichen Literatur zum Thema „Software analysis and verification“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 1. Februar 2022

Geben Sie eine Quelle nach APA, MLA, Chicago, Harvard und anderen Zitierweisen an

Wählen Sie eine Art der Quelle aus:

Machen Sie sich mit den Listen der aktuellen Artikel, Bücher, Dissertationen, Berichten und anderer wissenschaftlichen Quellen zum Thema "Software analysis and verification" bekannt.

Neben jedem Werk im Literaturverzeichnis ist die Option "Zur Bibliographie hinzufügen" verfügbar. Nutzen Sie sie, wird Ihre bibliographische Angabe des gewählten Werkes nach der nötigen Zitierweise (APA, MLA, Harvard, Chicago, Vancouver usw.) automatisch gestaltet.

Sie können auch den vollen Text der wissenschaftlichen Publikation im PDF-Format herunterladen und eine Online-Annotation der Arbeit lesen, wenn die relevanten Parameter in den Metadaten verfügbar sind.

Zeitschriftenartikel zum Thema "Software analysis and verification"

V. Gayetri Devi, S., C. Nalini und N. Kumar. „An efficient software verification using multi-layered software verification tool“. International Journal of Engineering & Technology 7, Nr. 2.21 (20.04.2018): 454. http://dx.doi.org/10.14419/ijet.v7i2.21.12465.

Der volle Inhalt der Quelle

Annotation:

Rapid advancements in Software Verification and Validation have been critical in the wide development of tools and techniques to identify potential Concurrent bugs and hence verify the software correctness. A concurrent program has multiple processes and shared objects. Each process is a sequential program and they use the shared objects for communication for completion of a task. The primary objective of this survey is retrospective review of different tools and methods used for the verification of real-time concurrent software. This paper describes the proposed tool ‘F-JAVA’ for multithreaded Java codebases in contrast with existing ‘FRAMA-C’ platform, which is dedicated to real-time concurrent C software analysis. The proposed system is comprised of three layers, namely Programming rules generation stage, Verification stage with Particle Swarm Optimization (PSO) algorithm, and Performance measurement stage. It aims to address some of the challenges in the verification process such as larger programs, long execution times, and false alarms or bugs, and platform independent code verification

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Chaki, Sagar, Edmund Clarke, Natasha Sharygina und Nishant Sinha. „Verification of evolving software via component substitutability analysis“. Formal Methods in System Design 32, Nr. 3 (02.05.2008): 235–66. http://dx.doi.org/10.1007/s10703-008-0053-x.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Chun, Seung Su. „Effective Extraction of State Invariant for Software Verification“. Applied Mechanics and Materials 752-753 (April 2015): 1097–104. http://dx.doi.org/10.4028/www.scientific.net/amm.752-753.1097.

Der volle Inhalt der Quelle

Annotation:

In software design of complex systems, more time and effort are spent on verification than on constructions. Model checking for software verification techniques offer a large potential to obtain and early integration of verification in the design process. This paper describes how to easily specify and the software properties and to understand the software generating automatically invariant. In this paper deal with issue that state invariant is a property that holds in every reachable state. Not only can be used in understanding and analysis of complex software systems. In addition, it can be used for system verifications such as checking safety, consistency, and completeness. For these reasons, there are many vital researches for deriving state invariant from finite state machine models. In this research was to be considered to extract state invariant. Thus it is likely to be too complex for the user to understand. This paper let the user focus on some interested parts (called scopes) rather than a whole state space in a model. Computation Tree Logic (CTL) is used to specify scopes in which he/she is interested. Given a scope in CTL, forward reachability analysis is used to find out a set of states inside it. Obviously, a set of states calculated in this way is a subset of every reachable state. Keywords: Software verification, Invariant, Scopes, Model Checking

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Cao, Zongyu, Wanyou Lv, Yanhong Huang, Jianqi Shi und Qin Li. „Formal Analysis and Verification of Airborne Software Based on DO-333“. Electronics 9, Nr. 2 (14.02.2020): 327. http://dx.doi.org/10.3390/electronics9020327.

Der volle Inhalt der Quelle

Annotation:

With rapid technological advances in airborne control systems, it has become imperative to ensure the reliability, robustness, and adaptability of airborne software since failure of these software could result in catastrophic loss of property and life. DO-333 is a supplement to the DO-178C standard, which is dedicated to guiding the application of formal methods in the review and analysis of airborne software development processes. However, DO-333 lacks theoretical guidance on how to choose appropriate formal methods and tools to achieve verification objectives at each stage of the verification process, thereby limiting their practical application. This paper is intended to illustrate the formal methods and tools available in the verification process to lay down a general guide for the formal development and verification of airborne software. We utilized the Air Data Computer (ADC) software as the research object and applied different formal methods to verify software lifecycle artifacts. This example explains how to apply formal methods in practical applications and proves the effectiveness of formal methods in the verification of airborne software.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Sa'd, M. Al, J. Graham und G. P. Liney. „A software tool for 3D dose verification and analysis“. Journal of Physics: Conference Series 444 (26.06.2013): 012087. http://dx.doi.org/10.1088/1742-6596/444/1/012087.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Liu, Hua Xiao, Peng Zhang, Li Wen Mu, Ying Jin und Xue Hang Chi. „A Verification Method of Software Acceptability“. Applied Mechanics and Materials 411-414 (September 2013): 436–39. http://dx.doi.org/10.4028/www.scientific.net/amm.411-414.436.

Der volle Inhalt der Quelle

Annotation:

Software requirements validation is one of the hot problems of software engineering field, for the formal verification of software acceptability, this paper presents a formal verification software acceptability method. This method uses the 4-variable model to character the software system requirements and the software behavior, and gives a formal description of the 4-variable model based on the generic model of Tabular expression, and converts the Tabular expression into predicate logic knowledge base to verify the software acceptability. The analysis shows that the proposed method is effective, and the software acceptability can be verified.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Charlton, Nathaniel. „Program verification with interacting analysis plugins“. Formal Aspects of Computing 19, Nr. 3 (05.04.2007): 375–99. http://dx.doi.org/10.1007/s00165-007-0029-4.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Bertrane, Julien, Patrick Cousot, Radhia Cousot, Jérôme Feret, Laurent Mauborgne, Antoine Miné und Xavier Rival. „Static Analysis and Verification of Aerospace Software by Abstract Interpretation“. Foundations and Trends® in Programming Languages 2, Nr. 2-3 (2015): 71–190. http://dx.doi.org/10.1561/2500000002.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Kornecki, Andrew, und Mingye Liu. „Fault Tree Analysis for Safety/Security Verification in Aviation Software“. Electronics 2, Nr. 4 (31.01.2013): 41–56. http://dx.doi.org/10.3390/electronics2010041.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Venet, Arnaud. „A practical approach to formal software verification by static analysis“. ACM SIGAda Ada Letters XXVIII, Nr. 1 (April 2008): 92–95. http://dx.doi.org/10.1145/1387830.1387836.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mehr Quellen

Dissertationen zum Thema "Software analysis and verification"

Jobredeaux, Romain J. „Formal verification of control software“. Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53841.

Der volle Inhalt der Quelle

Annotation:

In a context of heightened requirements for safety-critical embedded systems and ever-increasing costs of verification and validation, this research proposes to advance the state of formal analysis for control software. Formal methods are a field of computer science that uses mathematical techniques and formalisms to rigorously analyze the behavior of programs. This research develops a framework and tools to express and prove high level properties of control law implementations. One goal is to bridge the gap between control theory and computer science. An annotation language is extended with symbols and axioms to describe control-related concepts at the code level. Libraries of theorems, along with their proofs, are developed to enable an interactive proof assistant to verify control-related properties. Through integration in a prototype tool, the process of verification is made automatic, and applied to several example systems.In a context of heightened requirements for safety-critical embedded systems and ever-increasing costs of verification and validation, this research proposes to advance the state of formal analysis for control software. Formal methods are a field of computer science that uses mathematical techniques and formalisms to rigorously analyze the behavior of programs. This research develops a framework and tools to express and prove high level properties of control law implementations. One goal is to bridge the gap between control theory and computer science. An annotation language is extended with symbols and axioms to describe control-related concepts at the code level. Libraries of theorems, along with their proofs, are developed to enable an interactive proof assistant to verify control-related properties. Through integration in a prototype tool, the process of verification is made automatic, and applied to several example systems.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Domagoj, Babić. „Exploiting structure for scalable software verification“. Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/1502.

Der volle Inhalt der Quelle

Annotation:

Software bugs are expensive. Recent estimates by the US National Institute of Standards and Technology claim that the cost of software bugs to the US economy alone is approximately 60 billion USD annually. As society becomes increasingly software-dependent, bugs also reduce our productivity and threaten our safety and security. Decreasing these direct and indirect costs represents a significant research challenge as well as an opportunity for businesses. Automatic software bug-finding and verification tools have a potential to completely revolutionize the software engineering industry by improving reliability and decreasing development costs. Since software analysis is in general undecidable, automatic tools have to use various abstractions to make the analysis computationally tractable. Abstraction is a double-edged sword: coarse abstractions, in general, yield easier verification, but also less precise results. This thesis focuses on exploiting the structure of software for abstracting away irrelevant behavior. Programmers tend to organize code into objects and functions, which effectively represent natural abstraction boundaries. Humans use such structural abstractions to simplify their mental models of software and for constructing informal explanations of why a piece of code should work. A natural question to ask is: How can automatic bug-finding tools exploit the same natural abstractions? This thesis offers possible answers. More specifically, I present three novel ways to exploit structure at three different steps of the software analysis process. First, I show how symbolic execution can preserve the data-flow dependencies of the original code while constructing compact symbolic representations of programs. Second, I propose structural abstraction, which exploits the structure preserved by the symbolic execution. Structural abstraction solves a long-standing open problem --- scalable interprocedural path- and context-sensitive program analysis. Finally, I present an automatic tuning approach that exploits the fine-grained structural properties of software (namely, data- and control-dependency) for faster property checking. This novel approach resulted in a 500-fold speedup over the best previous techniques. Automatic tuning not only redefined the limits of automatic software analysis tools, but also has already found its way into other domains (like model checking), demonstrating the generality and applicability of this idea.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

White, Maurice Walter. „Verification and evaluation of structural analysis and design software“. Thesis, Virginia Tech, 1991. http://hdl.handle.net/10919/41489.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

de, Carvalho Gomes Pedro. „Automatic Extraction of Program Models for Formal Software Verification“. Doctoral thesis, KTH, Teoretisk datalogi, TCS, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-176286.

Der volle Inhalt der Quelle

Annotation:

In this thesis we present a study of the generation of abstract program models from programs in real-world programming languages that are employed in the formal verification of software. The thesis is divided into three parts, which cover distinct types of software systems, programming languages, verification scenarios, program models and properties.The first part presents an algorithm for the extraction of control flow graphs from sequential Java bytecode programs. The graphs are tailored for a compositional technique for the verification of temporal control flow safety properties. We prove that the extracted models soundly over-approximate the program behaviour w.r.t. sequences of method invocations and exceptions. Therefore, the properties that are established with the compositional technique over the control flow graphs also hold for the programs. We implement the algorithm as ConFlEx, and evaluate the tool on a number of test cases.The second part presents a technique to generate program models from incomplete software systems, i.e., programs where the implementation of at least one of the components is not available. We first define a framework to represent incomplete Java bytecode programs, and extend the algorithm presented in the first part to handle missing code. Then, we introduce refinement rules, i.e., conditions for instantiating the missing code, and prove that the rules preserve properties established over control flow graphs extracted from incomplete programs. We have extended ConFlEx to support the new definitions, and re-evaluate the tool, now over test cases of incomplete programs.The third part addresses the verification of multithreaded programs. We present a technique to prove the following property of synchronization with condition variables: "If every thread synchronizing under the same condition variables eventually enters its synchronization block, then every thread will eventually exit the synchronization". To support the verification, we first propose SyncTask, a simple intermediate language for specifying synchronized parallel computations. Then, we propose an annotation language for Java programs to assist the automatic extraction of SyncTask programs, and show that, for correctly annotated programs, the above-mentioned property holds if and only if the corresponding SyncTask program terminates. We reduce the termination problem into a reachability problem on Coloured Petri Nets. We define an algorithm to extract nets from SyncTask programs, and show that a program terminates if and only if its corresponding net always reaches a particular set of dead configurations. The extraction of SyncTask programs and their translation into Petri nets is implemented as the STaVe tool. We evaluate the technique by feeding annotated Java programs to STaVe, then verifying the extracted nets with a standard Coloured Petri Net analysis tool
Den här avhandlingen studerar automatisk konstruktion av abstrakta modeller för formell verifikation av program skrivna i verkliga programmeringsspråk. Avhandlingen består av tre delar som involverar olika typer av program, programmeringsspråk, verifikationsscenarier, programmodeller och egenskaper.Del ett presenterar en algoritm för generation av flödesgrafer från sekventiella program i Java bytekod. Graferna är skräddarsydda för en kompositionell teknik för verifikationen av temporala kontrollflödens säkerhetsegenskaper. Vi visar att de extraherade modellerna sunt överapproximerar programbeteenden med avseende på sekvenser av metodanrop och -undantag. Således gäller egenskaperna som kan fastställas genom kompositionstekniken över kontrollflöden även för programmen. Vi implementerar dessutom algoritmen i form av verktyget ConFlEx och utvärderar verktyget på ett antal testfall.Del två presenterar en teknik för att generera modeller av ofullständiga program. Det vill säga, program där implementationen av åtminstone en komponent inte är tillgänglig. Vi definierar ett ramverk för att representera ofullständiga Java bytekodsprogram och utökar algoritmen från del ett till att hantera ofullständig kod. Därefter presenterar vi raffineringsregler - villkor för att instansiera den saknade koden - och bevisar att reglerna bevarar relevanta egenskaper av kontrollflödesgrafer. Vi har dessutom utökat ConFlEx till att stödja de nya definitionerna och har omvärderat verktyget på testfall av ofullständiga program.Del tre angriper verifikation av multitrådade program. Vi presenterar en teknik för att bevisa följande egenskap för synkronisering med vilkorsvariabler: "Om varje trådsynkronisering under samma villkor så småningom stiger in i sitt synkroniseringsblock så kommer varje tråd också till slut lämna synkroniseringen". För att stödja verifikationen så introducerar vi först SyncTask - ett enkelt mellanliggande språk för att specificera synkronisering av parallella beräkningar. Därefter presenterar vi ett annoteringsspråk för Java som tillåter automatisk extrahering av SyncTask-program och visar att egenskapen gäller om och endast om motsvarande SyncTask-program terminerar. Vi reducerar termineringsproblemet till ett nåbarhetsproblem på färgade Petrinät samt definierar en algoritm som skapar Petrinät från SyncTask-program där programmet terminerar om och endast om nätet alltid når en särskild mängd av döda konfigurationer. Extraktionen av SyncTask-program och deras motsvarande Petrinät är implementerade i form av verktyget STaVe. Slutligen utvärderar vi verktyget genom att mata annoterade.

QC 20151101

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Molin, Oscar. „Design verification through software architecture recovery : Meeting ISO 26262 requirements on software using static analysis“. Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-202149.

Der volle Inhalt der Quelle

Annotation:

Emerging functional safety standards in the automotive industry will create new challenges for companies sitting on large deposits of legacy code. When refactoring existing code for compliance with standards such as ISO 26262, great savings could be made if work products required by the standard could be automatically generated from existing source code. In this thesis, we explore the possibilities to generate graphical software architectures, data-flow graphs and software architectural descriptions directly from existing C source code. By parsing the source code to find structures and the relations between them, we were able to create relational graphs that represents the software of an entire system or that of just one component, using different levels of abstraction where appropriate. We create a proof-of-concept tool chain that can generate two kinds of graphical architecture views and one data-flow view. Although these tools are by no means ready for production, they do show promise and are already useful as development tools for better software understanding. Finally we test the tool chain on current production ECU (Electric Control Unit) software used in heavy trucks and buses and evaluate the results against the requirements of the ISO 26262 standard. This thesis was done at Scania CV AB in Södertälje, Sweden.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Limouee, Maryam. „Verification of NYSlab a software for the analysis of jointed pavements /“. To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mrvaljevic, Pavle. „Tool orchestration for modeling, verification and analysis of collaborating autonomous machines“. Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-48884.

Der volle Inhalt der Quelle

Annotation:

System-of-systems (SoS) is a collective of multiple system units that have a common purpose. In this thesis, the Volvo Electric Site is investigated as an example case study in which safety and performance properties of collaborating autonomous machines are evaluated and analyzed. Formal methods in software engineering aim to prove the correctness of the system by evaluating its mathematical model. We use an actor-based framework, AdaptiveFlow, for modeling system functionalities and timing features. The aim is to link an abstract model evaluation and a simulation of real-world cases that are deployed in the VCE Simulator. In addition, it is necessary to make sure that AdaptiveFlow provides correct-by-design scenarios. The verification is conducted by developing an orchestration method between the AdaptiveFlow framework and the VCE Simulator. A tool named VMap is developed throughout this thesis for automated mapping of the input models of AdaptiveFlow and the VCE Simulator to make the orchestration possible. Furthermore, AdaptiveFlow is perceived in two different ways, as a design tool, and as an analysis tool. The models created in AdaptiveFlow are directly mapped to the VCE Simulator by using the VMap tool where the VCE Simulator is used as a testbed for checking these models. The outcome of this thesis is reflected in the establishment of a mapping pattern between AdaptiveFlow inputs and VCE simulator by developing the VMap tool for automatic mapping. It was shown that there is a natural mapping between the AdaptiveFlow models and VCE simulator inputs. By using VMap, we can quickly get to the desired scenarios. Through the development of three different cases, the results show that it is possible to design safe and optimal scenarios by orchestrating the AdaptiveFlow and the VCE Simulator using the VMap tool as well as the correlation between results from AdaptiveFlow and VCE Simulator.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Motta, Teixeira Leopoldo. „Verification and refactoring of configuration knowledge for software product lines“. Universidade Federal de Pernambuco, 2010. https://repositorio.ufpe.br/handle/123456789/2323.

Der volle Inhalt der Quelle

Annotation:

Made available in DSpace on 2014-06-12T15:56:44Z (GMT). No. of bitstreams: 2 arquivo2985_1.pdf: 5101466 bytes, checksum: 86a375e15b77076e9eb9adffbe664c52 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010
Conselho Nacional de Desenvolvimento Científico e Tecnológico
Uma linha de produtos de software (LPS) é definida como um conjunto de sistemas de software que compartilham características em comum, mas que são suficientemente distintos entre si, desenvolvidos a partir de um conjunto de artefatos reusáveis. Modelos de features e configuração são usados para possibilitar a geração automática de produtos a partir destes artefatos. Um modelo de features representa o conjunto de possíveis configurações de produto de uma LPS, enquanto o modelo de configuração estabelece o mapeamento entre features e implementação. Por exemplo, associando expressões de features, na forma de proposições lógicas, a artefatos. Os benefícios de produtividade que a abordagem de LPS fornece tornam possível que uma LPS seja capaz de gerar milhares de produtos. Neste contexto, erros cometidos ao especificar o modelo de configuração podem resultar em produtos inválidos - o problema da composição segura. Este problema pode ser difícil de ser detectado manualmente, já que os modelos de features e configuração podem tornar-se muito complexos. Gerar todos os produtos de uma LPS pode não ser prático, dado que existem LPS em que é possível gerar milhares de produtos. No entanto, mesmo modelos de configuração que não permitem a geração de produtos inválidos podem ter problemas na sua estrutura interna, como complexidade e duplicação, especialmente no contexto de LPS grandes, onde sua manutenção pode se tornar difícil. Precisamos nos certificar de que não introduzimos erros ao corrigir estes problemas. Neste trabalho, é proposta uma abordagem automática de verificação de composição segura para LPS baseadas em modelos de configuração. Esta abordagem é baseada na tradução de instâncias específicas de modelos de features e configuração em lógica proposicional, usando uma teoria codificada com Alloy. O suporte ferramental fornecido pelo Alloy Analyzer auxilia a verificação. Também é proposto um catálogo de refatoramentos simples para modelos de configuração, como uma maneira de evitar erros ao corrigir problemas na estrutura interna de tais modelos. Este catálogo é formalizado usando uma teoria geral para modelos de configuração especificada com o Prototype Verification System (PVS). Nós avaliamos a abordagem de verificação usando sete versões de uma LPS, com modelos de features que possibilitam a geração de até 272 produtos. Os resultados demonstram a vantagem de usar esta abordagem ao invés de gerar todos os produtos da LPS, já que o tempo médio para compilar um único produto da LPS é maior que o tempo para analisá-la na maior das versões analisadas. Também avaliamos o catálogo de refatoramento provando consistência (soundness) dos refatoramentos propostos no provador de teoremas de PVS

APA, Harvard, Vancouver, ISO und andere Zitierweisen

de, Carvalho Gomes Pedro. „Sound Modular Extraction of Control Flow Graphs from Java Bytecode“. Licentiate thesis, KTH, Teoretisk datalogi, TCS, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-105275.

Der volle Inhalt der Quelle

Annotation:

Control flow graphs (CFGs) are abstract program models that preserve the control flow information. They have been widely utilized for many static analyses in the past decades. Unfortunately, previous studies about the CFG construction from modern languages, such as Java, have either neglected advanced features that influence the control flow, or do not provide a correctness argument. This is a bearable issue for some program analyses, but not for formal methods, where the soundness of CFGs is a mandatory condition for the verification of safety-critical properties. Moreover, when developing open systems, i.e., systems in which at least one component is missing, one may want to extract CFGs to verify the available components. Soundness is even harder to achieve in this scenario, because of the unknown inter-dependencies involving missing components. In this work we present two variants of a CFG extraction algorithm from Java bytecode considering precise exceptional flow, which are sound w.r.t to the JVM behavior. The first algorithm extracts CFGs from fully-provided (closed) programs only. It proceeds in two phases. Initially the Java bytecode is translated into a stack-less intermediate representation named BIR, which provides explicit representation of exceptions, and is more compact than the original bytecode. Next, we define the transformation from BIR to CFGs, which, among other features, considers the propagation of uncaught exceptions within method calls. We then establish its correctness: the behavior of the extracted CFGs is shown to be a sound over-approximation of the behavior of the original programs. Thus, temporal safety properties that hold for the CFGs also hold for the program. We prove this by suitably combining the properties of the two transformations with those of a previous idealized CFG extraction algorithm, whose correctness has been proven directly. The second variant of the algorithm is defined for open systems. We generalize the extraction algorithm for closed systems for a modular set-up, and resolve inter-dependencies involving missing components by using user-provided interfaces. We establish its correctness by defining a refinement relation between open systems, which constrains the instantiation of missing components. We prove that if the relation holds, then the CFGs extracted from the components of the original open system are sound over-approximations of the CFGs for the same components in the refined system. Thus, temporal safety properties that hold for an open system also hold for closed systems that refine it. We have implemented both algorithms as the ConFlEx tool. It uses Sawja, an external library for the static analysis of Java bytecode, to transform bytecode into BIR, and to resolve virtual method calls. We have extended Sawja to support open systems, and improved its exception type analysis. Experimental results have shown that the algorithm for closed systems generates more precise CFGs than the modular algorithm. This was expected, due to the heavy over-approximations the latter has to perform to be sound. Also, both algorithms are linear in the number of bytecode instructions. Therefore, ConFlEx is efficient for the extraction of CFGs from either open, or closed Java bytecode programs.

QC 20121122

APA, Harvard, Vancouver, ISO und andere Zitierweisen

de, Carvalho Gomes Pedro, und Attilio Picoco. „Sound Extraction of Control-Flow Graphs from open Java Bytecode Systems“. KTH, Teoretisk datalogi, TCS, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-104076.

Der volle Inhalt der Quelle

Annotation:

Formal verification techniques have been widely deployed as means to ensure the quality of software products. Unfortunately, they suffer with the combinatorial explosion of the state space. That is, programs have a large number of states, sometimes infinite. A common approach to alleviate the problem is to perform the verification over abstract models from the program. Control-flow graphs (CFG) are one of the most common models, and have been widely studied in the past decades. Unfortunately, previous works over modern programming languages, such as Java, have either neglected features that influence the control-flow, or do not provide a correctness argument about the CFG construction. This is an unbearable issue for formal verification, where soundness of CFGs is a mandatory condition for the verification of safety-critical properties. Moreover, one may want to extract CFGs from the available components of an open system. I.e., a system whose at least one of the components is missing. Soundness is even harder to achieve in this scenario, because of the unknown inter-dependences between software components. In the current work we present a framework to extract control-flow graphs from open Java Bytecode systems in a modular fashion. Our strategy requires the user to provide interfaces for the missing components. First, we present a formal definition of open Java bytecode systems. Next, we generalize a previous algorithm that performs the extraction of CFGs for closed programs to a modular set-up. The algorithm uses the user-provided interfaces to resolve inter-dependences involving missing components. Eventually the missing components will arrive, and the open system will become closed, and can execute. However, the arrival of a component may affect the soundness of CFGs which have been extracted previously. Thus, we define a refinement relation, which is a set of constraints upon the arrival of components, and prove that the relation guarantees the soundness of CFGs extracted with the modular algorithm. Therefore, the control-flow safety properties verified over the original CFGs still hold in the refined model. We implemented the modular extraction framework in the ConFlEx tool. Also, we have implemented the reusage from previous extractions, to enable the incremental extraction of a newly arrived component. Our technique performs substantial over-approximations to achieve soundness. Despite this, our test cases show that ConFlEx is efficient. Also, the extraction of the CFGs gets considerable speed-up by reusing results from previous analyses.

QC 20121029

Verification of Control-Flow Properties of Programs with Procedures(CVPP)

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mehr Quellen

Bücher zum Thema "Software analysis and verification"

Stanley, William, und Janusz Laski. Software Verification and Analysis. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84882-240-5.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Bultan, Tevfik, Fang Yu, Muath Alkhalaf und Abdulbaki Aydin. String Analysis for Software Verification and Security. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-68670-7.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Germany) NATO Advanced Study Institute on Tools for Analysis and Verification of Software Safety and Security (2011 Bayrischzell. Software safety and security: Tools for analysis and verification. Amsterdam: IOS Press published in cooperation with NATO Emerging Security Challenges Division, 2012.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Khedker, Uday. Data flow analysis: Theory and practice. Boca Raton, Fla: Taylor & Francis, 2009.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Symposium on Testing, Analysis, and Verification (1991 Victoria, B.C.). Proceedings of the Symposium on Testing, Analysis, and Verification (TAV4): Victoria, British Columbia, October 8-10, 1991. New York: ACM Press, 1991.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Clarke, Dave. Aliasing in Object-Oriented Programming. Types, Analysis and Verification. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Symposium on Software Testing, Analysis, and Verification (3rd 1989 Key West, Fla.). Proceedings of the ACM SIGSOFT '89: Third Symposium on Software Testing, Analysis, and Verification (TAV3), Key West, Florida, December 13-15, 1989 / edited by Richard A. Kemmerer. New York: ACM Press, 1989.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Zeljko, Zilic, Hrsg. Verification by error modeling: Using testing techniques in hardware verification. Boston: Kluwer Academic Publishers, 2003.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Bouajjani, Ahmed. Automated Technology for Verification and Analysis: 8th International Symposium, ATVA 2010, Singapore, September 21-24, 2010. Proceedings. Berlin, Heidelberg: Springer-Verlag Heidelberg, 2010.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Sungdeok, Cha, Hrsg. Automated technology for verification and analysis: 6th international symposium, ATVA 2008, Seoul, Korea, October 20-23, 2008, proceedings. Berlin: Springer, 2008.

Den vollen Inhalt der Quelle finden

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Mehr Quellen

Buchteile zum Thema "Software analysis and verification"

Carré, Bernard. „Program analysis and verification“. In High-Integrity Software, 176–97. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4684-5775-9_8.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Donaldson, Alastair F., Leopold Haller, Daniel Kroening und Philipp Rümmer. „Software Verification Using k-Induction“. In Static Analysis, 351–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23702-7_26.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Holzmann, Gerard_J. „Software Analysis and Model Checking“. In Computer Aided Verification, 1–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45657-0_1.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Laski, Janusz, und William Stanley. „Dynamic Program Analysis“. In Software Verification and Analysis, 203–19. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84882-240-5_9.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Berz, Martin, und Kyoko Makino. „Rigorous Reachability Analysis and Domain Decomposition of Taylor Models“. In Numerical Software Verification, 90–97. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-63501-9_7.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Sekar, R. „Runtime Analysis and Instrumentation for Securing Software“. In Runtime Verification, 58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-16612-9_6.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Laski, Janusz, und William Stanley. „Why Not Write Correct Software the First Time?“ In Software Verification and Analysis, 1–14. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84882-240-5_1.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Laski, Janusz, und William Stanley. „How to Prove a Program Correct: Programs Without Loops“. In Software Verification and Analysis, 39–61. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84882-240-5_2.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Laski, Janusz, und William Stanley. „How to Prove a Program Correct: Iterative Programs“. In Software Verification and Analysis, 63–79. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84882-240-5_3.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Laski, Janusz, und William Stanley. „Prepare Test for Any Implementation: Black-Box Testing“. In Software Verification and Analysis, 81–99. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84882-240-5_4.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Konferenzberichte zum Thema "Software analysis and verification"

Podymov, Vladislav, und Uliana Popesko. „UPPAAL-based software-defined network verification“. In 2013 Tools & Methods of Program Analysis (TMPA). IEEE, 2013. http://dx.doi.org/10.1109/tmpa.2013.7163715.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Morell, L. J. „Theoretical insights into fault-based testing“. In Workshop on Software Testing, Verification, and Analysis. IEEE, 1988. http://dx.doi.org/10.1109/wst.1988.5353.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

„Proceedings of the Second Workshop on Software Testing, Verification, and Analysis (Cat. No.88TH0225-3)“. In Workshop on Software Testing, Verification, and Analysis. IEEE, 1988. http://dx.doi.org/10.1109/wst.1988.5360.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Weiss, S. N. „A formal framework for the study of concurrent program testing“. In Workshop on Software Testing, Verification, and Analysis. IEEE, 1988. http://dx.doi.org/10.1109/wst.1988.5362.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Kellogg, Martin, Vlastimil Dort, Suzanne Millstein und Michael D. Ernst. „Lightweight verification of array indexing“. In ISSTA '18: International Symposium on Software Testing and Analysis. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3213846.3213849.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Carlson, Jan-Renee. „Verification of Software: The Textbook and Real Problems“. In 11th AIAA/ISSMO Multidisciplinary Analysis and Optimization Conference. Reston, Virigina: American Institute of Aeronautics and Astronautics, 2006. http://dx.doi.org/10.2514/6.2006-7128.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Cortesi, Agostino, Pietro Ferrara und Nabendu Chaki. „Static analysis techniques for robotics software verification“. In 2013 44th International Symposium on Robotics (ISR 2013). IEEE, 2013. http://dx.doi.org/10.1109/isr.2013.6739742.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Beyene, Tewodros A., Marc Brockschmidt und Andrey Rybalchenko. „CTL+FO verification as constraint solving“. In ISSTA '14: International Symposium on Software Testing and Analysis. New York, NY, USA: ACM, 2014. http://dx.doi.org/10.1145/2632362.2632364.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Latorre, Nicolas, Francesco Alberti und Natasha Sharygina. „Verige: verification with invariant generation engine“. In ISSTA '14: International Symposium on Software Testing and Analysis. New York, NY, USA: ACM, 2014. http://dx.doi.org/10.1145/2632362.2632373.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Alqahtani, Sultan S. „Enhancing Trust – Software Vulnerability Analysis Framework“. In 2017 IEEE International Conference on Software Testing, Verification and Validation (ICST). IEEE, 2017. http://dx.doi.org/10.1109/icst.2017.76.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Berichte der Organisationen zum Thema "Software analysis and verification"

Leyva, Nha. Uncertainty Analysis and Software Verification. Office of Scientific and Technical Information (OSTI), Juli 2021. http://dx.doi.org/10.2172/1813900.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Nelson, Adam G., und Micheal A. Smith. Verification of the DIF3D Software to Support Fast Reactor Analysis. Office of Scientific and Technical Information (OSTI), Februar 2020. http://dx.doi.org/10.2172/1599877.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Varma, Amit, und Jungil Seo. Verification of LRFD Bridge Design and Analysis Software for INDOT. West Lafayette, Indiana: Purdue University, 2011. http://dx.doi.org/10.5703/1288284314279.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Butler, Richard S. Air Force Systems Command Software Independent Verification and Validation Implementation Analysis and Guidance. Fort Belvoir, VA: Defense Technical Information Center, April 1988. http://dx.doi.org/10.21236/ada194309.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Lucon, Enrico. New software for the statistical analysis and qualification of NIST charpy verification specimen lots. Gaithersburg, MD: National Institute of Standards and Technology, April 2018. http://dx.doi.org/10.6028/nist.ir.8211.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

BRATZEL, D. R. Flammable Gas Refined Safety Analysis Tool Software Verification and Validation Report for Resolve Version 2.5. Office of Scientific and Technical Information (OSTI), September 2000. http://dx.doi.org/10.2172/804776.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Copps, Kevin D. Verification of the coupled fluid/solid transfer in a CASL grid-to-rod-fretting simulation : a technical brief on the analysis of convergence behavior and demonstration of software tools for verification. Office of Scientific and Technical Information (OSTI), Dezember 2011. http://dx.doi.org/10.2172/1038207.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Strichman, Ofer. Software Regression Verification. Fort Belvoir, VA: Defense Technical Information Center, Dezember 2013. http://dx.doi.org/10.21236/ada594501.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

COMPUSEC INC SAN DIEGO CA. Secure Software Verification Tools. Fort Belvoir, VA: Defense Technical Information Center, Februar 1987. http://dx.doi.org/10.21236/ada189731.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Wallace, Dolores R., und Roger U. Fujii. Software verification and validation. Gaithersburg, MD: National Institute of Standards and Technology, 1989. http://dx.doi.org/10.6028/nist.sp.500-165.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Wir bieten Rabatte auf alle Premium-Pläne für Autoren, deren Werke in thematische Literatursammlungen aufgenommen wurden. Kontaktieren Sie uns, um einen einzigartigen Promo-Code zu erhalten!