Thematische Bibliographien / Simulation – Hardware – Software

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Auswahl der wissenschaftlichen Literatur zum Thema „Simulation – Hardware – Software“

Autor: Grafiati

Veröffentlicht am 29. Juni 2021

Zuletzt aktualisiert am 9. Februar 2022

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Zeitschriftenartikel zum Thema "Simulation – Hardware – Software"

Wang, Shihao. „Software Simulation for Hardware/Software Co-Verification“. Journal of Computer Research and Development 42, Nr. 3 (2005): 514. http://dx.doi.org/10.1360/crad20050322.

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Grierson, W. O. „Perspectives in Simulation Hardware and Software Architecture“. Modeling, Identification and Control: A Norwegian Research Bulletin 6, Nr. 4 (1985): 249–55. http://dx.doi.org/10.4173/mic.1985.4.5.

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Milik, Adam, und Edward Hrynkiewicz. „Accelerated Co-Simulation of Hardware-Software System Based on Configurable Hardware Accelertor and Selective Simulation“. IFAC Proceedings Volumes 36, Nr. 1 (Februar 2003): 31–36. http://dx.doi.org/10.1016/s1474-6670(17)33710-2.

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Grycel, Jacob, und Patrick Schaumont. „SimpliFI: Hardware Simulation of Embedded Software Fault Attacks“. Cryptography 5, Nr. 2 (07.06.2021): 15. http://dx.doi.org/10.3390/cryptography5020015.

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Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities. These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor microarchitecture. We present SimpliFI, a simulation methodology to test fault attacks on embedded software using a hardware simulation of the processor running the software. We explain the purpose and advantage of SimpliFI, describe automation of the simulation framework, and apply SimpliFI on a BRISC-V embedded processor running an AES application.

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Nahvi, M. „Design-oriented DSP courseware-hardware, software, and simulation“. IEEE Signal Processing Magazine 9, Nr. 4 (Oktober 1992): 30–35. http://dx.doi.org/10.1109/79.157328.

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Morris, D. „Simulating the Behaviour of Computer Systems: Co-simulation of Hardware/Software“. Computer Journal 40, Nr. 10 (01.10.1997): 617–29. http://dx.doi.org/10.1093/comjnl/40.10.617.

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AhmedAsifFuad, Kazi, und Shahriyar Masud Rizvi. „Hardware Software Co-Simulation of Canny Edge Detection Algorithm“. International Journal of Computer Applications 122, Nr. 19 (18.07.2015): 7–12. http://dx.doi.org/10.5120/21806-5124.

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Al-Haija, Qasem Abu, Hanan Al-Mubarak und Abdulla Al-Humam. „Hardware Design and Software Simulation for Four Classical Cryptosystems“. Procedia Computer Science 21 (2013): 500–505. http://dx.doi.org/10.1016/j.procs.2013.09.069.

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Vikram, K. N., und V. Vasudevan. „Hardware–software co-simulation of bus-based reconfigurable systems“. Microprocessors and Microsystems 29, Nr. 4 (Mai 2005): 133–44. http://dx.doi.org/10.1016/j.micpro.2004.07.004.

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Olukotun, K. A., R. Helaihel, J. Levitt und R. Ramirez. „A software-hardware cosynthesis approach to digital system simulation“. IEEE Micro 14, Nr. 4 (August 1994): 48–58. http://dx.doi.org/10.1109/40.296157.

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Dissertationen zum Thema "Simulation – Hardware – Software"

Lu, Lipin. „Simulation Software and Hardware for Teaching Ultrasound“. Scholarly Repository, 2008. http://scholarlyrepository.miami.edu/oa_theses/143.

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Over the years, medical imaging modalities have evolved drastically. Accordingly, the need for conveying the basic imaging knowledge to future specialists and other trainees becomes even more crucial for devoted educators. Understanding the concepts behind each imaging modality requires a plethora of advanced physics, mathematics, mechanics and medical background. Absorbing all of this background information is a daunting task for any beginner. This thesis focuses on developing an ultrasound imaging education tutorial with the goal of easing the process of learning the principles of ultrasound. This tutorial will utilize three diverse approaches including software and hardware applications. By performing these methodologies from different perspectives, not only will the efficiency of the training be enhanced, but also the trainee?s understanding of crucial concepts will be reinforced through repetitive demonstration. The first goal of this thesis was developing an online medical imaging simulation system and deploying it on the website of the University of Miami. In order to construct an easy, understandable, and interactive environment without deteriorating the important aspects of the ultrasound principles, interactive flash animations (developed by Macromedia Director MX) were used to present concepts via graphic-oriented simulations. The second goal was developing a stand-alone MATLAB program, intended to manipulate the intensity of the pixels in the image in order to simulate how ultrasound images are derived. Additionally, a GUI (graphic user interface) was employed to maximize the accessibility of the program and provide easily adjustable parameters. The GUI window enables trainees to see the changes in outcomes by altering different parameters of the simulation. The third goal of this thesis was to incorporating an actual ultrasound demonstration into the tutorial. This was achieved by using a real ultrasound transducer with a pulse/receiver so that trainees could observe actual ultrasound phenomena, and view the results using an oscilloscope. By manually adjusting the panels on the pulse/ receiver console, basic A-mode ultrasound experiments can be performed with ease. By combining software and hardware simulations, the ultrasound education package presented in this thesis will help trainees more efficiently absorb the various concepts behind ultrasound.

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Brankovic, Aleksandar. „Performance simulation methodologies for hardware/software co-designed processors“. Doctoral thesis, Universitat Politècnica de Catalunya, 2015. http://hdl.handle.net/10803/287978.

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Recently the community started looking into Hardware/Software (HW/SW) co-designed processors as potential solutions to move towards the less power consuming and the less complex designs. Unlike other solutions, they reduce the power and the complexity doing so called dynamic binary translation and optimization from a guest ISA to an internal host custom ISA. This thesis tries to answer the question on how to simulate this kind of architectures. For any kind of processor's architecture, the simulation is the common practice, because it is impossible to build several versions of hardware in order to try all alternatives. The simulation of HW/SW co-designed processors has a big issue in comparison with the simulation of traditional HW-only architectures. First of all, open source tools do not exist. Therefore researches many times assume that the software layer overhead, which is in charge for dynamic binary translation and optimization, is constant or ignored. In this thesis we show that such an assumption is not valid and that can lead to very inaccurate results. Therefore including the software layer in the simulation is a must. On the other side, the simulation is very slow in comparison to native execution, so the community spent a big effort on delivering accurate results in a reasonable amount of time. Therefore it is the common practice for HW-only processors that only parts of application stream, which are called samples, are simulated. Samples usually correspond to different phases in the application stream and usually they are no longer than a few million of instructions. In order to archive accurate starting state of each sample, microarchitectural structures are warmed-up for a few million instructions prior to samples instructions. Unfortunately, such a methodology cannot be directly applied for HW/SW co-designed processors. The warm-up for HW/SW co-designed processors needs to be 3-4 orders of magnitude longer than the warm-up needed for traditional HW-only processor, because the warm-up of software layer needs to be longer than the warm-up of hardware structures. To overcome such a problem, in this thesis we propose a novel warm-up technique specialized for HW/SW co-designed processors. Our solution reduces the simulation time by at least 65X with an average error of just 0.75\%. Such a trend is visible for different software and hardware configurations. The process used to determine simulation samples cannot be applied to HW/SW co-designed processors as well, because due to the software layer, samples show more dissimilarities than in the case of HW-only processors. Therefore we propose a novel algorithm that needs 3X less number of samples to achieve similar error like the state of the art algorithms. Again, such a trend is visible for different software and hardware configurations.
Els processadors co-dissenyats Hardware/Software (HW/SW co-designed processors) han estat proposats per l'acadèmia i la indústria com a solucions potencials per a fabricar processadors menys complexos i que consumeixen menys energia. A diferència d'altres alternatives, aquest tipus de processadors redueixen la complexitat i el consum d'energia aplicant traducció y optimització dinàmica de binaris des d'un repertori d'instruccions (instruction set architecture) extern cap a un repertori d'instruccions intern adaptat. Aquesta tesi intenta resoldre els reptes relacionats a la simulació d'aquest tipus d'arquitectures. La simulació és un procés comú en el disseny i desenvolupament de processadors ja que permet explorar diverses alternatives sense haver de fabricar el hardware per a cadascuna d'elles. La simulació de processadors co-dissenyats Hardware/Software és un procés més complex que la simulació de processadores tradicionals, purament hardware. Per exemple, no existeixen eines de simulació disponibles per a la comunitat. Per tant, els investigadors acostumen a assumir que la capa de software, que s'encarrega de la traducció i optimització de les aplicacions, no té un pes específic i, per tant, uns costos computacionals baixos o constants en el millor dels casos. En aquesta tesis demostrem que aquestes premisses són incorrectes i que els resultats amb aquestes acostumen a ser molt imprecisos. Una primera conclusió d'aquesta tesi doncs és que la simulació de la capa software és totalment necessària. A més a més, degut a que els processos de simulació són lents, s'han proposat tècniques de simulació que intenten obtenir resultats precisos en el menor temps possible. Una pràctica habitual és la simulació només de parts de les aplicacions, anomenades mostres, en el disseny de processadors convencionals, purament hardware. Aquestes mostres corresponen a diferents fases de les aplicacions i acostumen a ser de pocs milions d'instruccions. Per tal d'aconseguir un estat microarquitectònic acurat per a cadascuna de les mostres, s'acostumen a estressar aquestes estructures microarquitectòniques del simulador abans de començar a extreure resultats, procés anomenat "escalfament" (warm-up). Desafortunadament, aquesta metodologia no pot ser aplicada a processadors co-dissenyats Hardware/Software. L'"escalfament" de les estructures internes del simulador en el disseny de processadores co-dissenyats Hardware/Software són 3-4 ordres de magnitud més gran que el mateix procés d' "escalfament" en simulacions de processadors convencionals, ja que en els primers cal "escalfar" també les estructures i l'estat de la capa software. En aquesta tesi proposem tècniques de simulació basades en l' "escalfament" de les estructures que redueixen el temps de simulació en 65X amb un error mig del 0,75%. Aquests resultats són extrapolables a diferents configuracions del hardware i de la capa software. Finalment, les tècniques convencionals de selecció de mostres d'aplicacions a simular no són aplicables tampoc a la simulació de processadors co-dissenyats Hardware/Software degut a que les mostres es comporten de manera molt diferent quan es té en compte la capa software. En aquesta tesi, proposem un nou algorisme que redueix 3X el nombre de mostres a simular comparat amb els algorismes tradicionals per a processadors convencionals per a obtenir un error similar. Aquests resultats també són extrapolables a diferents configuracions de hardware i de software. En conclusió, en aquesta tesi es respon al repte de com simular processadors co-dissenyats Hardware/Software, que són una alternativa al disseny tradicional de processadors. Hem demostrat que cal simular la capa software i s'han proposat noves tècniques i algorismes eficients d' "escalfament" i selecció de mostres que són tolerants a diferents configuracions

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Blumer, Aric David. „Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration“. Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.

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The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by migration systems to accelerate RTL simulation. In this dissertation, process migration is first formally modeled using Finite State Machines (FSMs). Upon FSMs are built programs, processes, migration realms, and the migration of process state within a realm. From this model, a taxonomy of migration realms is developed. Second, process migration is applied to the RTL simulation of digital circuits. The canonical form of an RTL process is defined, and transformations of HDL code are justified and demonstrated. These transformations allow a simulator to identify basic active units within the simulation and combine them to balance the load across a set of processors. Through the use of input monitors, executive locality of reference is identified and demonstrated on a set of six RTL designs. Finally, the implementation of a migration system is described which utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and algorithmic models are developed from the data collected from the implementation to evaluate the effect of optimizations and migration algorithms.
Ph. D.

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Yildirim, Gokce. „Smoke Simulation On Programmable Graphics Hardware“. Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/12606545/index.pdf.

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Fluids such as smoke, water and fire are simulated for both Computer Graphics applications and engineering fields such as Mechanical Engineering. Generally, Fluid Dynamics is used for the achievement of realistic-looking fluid simulations. However, the complexity of these calculations makes it difficult to achieve high performance. With the advances in graphics hardware, it has been possible to provide programmability both at the vertex and the fragment level, which allows for faster simulations of complex fluids and other events. In this thesis, one gaseous fluid, smoke is simulated in three dimensions by solving Navier-Stokes Equations (NSEs) using a semi-Lagrangian unconditionally stable method. Simulation is performed both on Central Processing Unit (CPU) and Graphics Processing Unit (GPU). For the programmability at the vertex and the fragment level, C for Graphics (Cg), a platform-independent and architecture neutralshading language, is used. Owing to the advantage of programmability and parallelism of GPU, smoke simulation on graphics hardware runs significantly faster than the corresponding CPU implementation. The test results prove the higher performance of GPU over CPU for running three dimensional fluid simulations.

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Freitas, Arthur. „Hardware/Software Co-Verification Using the SystemVerilog DPI“. Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700941.

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During the design and verification of the Hyperstone S5 flash memory controller, we developed a highly effective way to use the SystemVerilog direct programming interface (DPI) to integrate an instruction set simulator (ISS) and a software debugger in logic simulation. The processor simulation was performed by the ISS, while all other hardware components were simulated in the logic simulator. The ISS integration allowed us to filter many of the bus accesses out of the logic simulation, accelerating runtime drastically. The software debugger integration freed both hardware and software engineers to work in their chosen development environments. Other benefits of this approach include testing and integrating code earlier in the design cycle and more easily reproducing, in simulation, problems found in FPGA prototypes.

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Wells, George James. „Hardware emulation and real-time simulation strategies for the concurrent development of microsatellite hardware and software“. Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ62899.pdf.

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Liu, Tsun-Ho. „Future hardware realization of self-organizing learning array and its software simulation“. Ohio : Ohio University, 2002. http://www.ohiolink.edu/etd/view.cgi?ohiou1174680878.

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Herfs, Werner Josef. „Modellbasierte Software in the Loop Simulation von Werkzeugmaschinen /“. Aachen : Apprimus-Verl, 2010. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=018939251&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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Bergström, Christoffer. „Simulation Framework of embedded systems in armored vehicle design“. Thesis, Umeå universitet, Institutionen för fysik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-185123.

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Embedded systems are a mixture of electric and mechanical hardware along with the software that is controlling them. BAE Systems Hägglunds, which designs and builds armored vehicles, is interested in knowing how to simulate these systems for logic validation and testing different design variations. The goal of this thesis was to create a framework for carrying out these simulations. This was done by analyzing hardware and software design at BAE and Identifying the necessary conditions for creating a model which can be simulated. Matlab Simulink is suggested as the tool for these simulations. The framework suggests dividing the model into smaller modules which reflects design principles at BAE. These modules will be made up of sub-modules containing hardware and software in layers. The hardware foundation will be made up of pre-designed components created in Simulink’s physical simulation library. The software will be imported into specialized sub-modules and integrated into the hardware using proposed bridge functions, converting information between the two systems. The framework is designed to provide a comprehensive solution instead of a deep one that can be adapted to changing circumstances. Tests have been made on small-scale systems, but the framework still needs to be tested on a large-scale system, which was not possible during this thesis. In conclusion, this is a stable foundation that needs to be built upon.

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Tang, Yi. „SUNSHINE: Integrate TOSSIM and P-Sim“. Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/40721.

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Simulators are important tools for wireless sensor network (sensornet) design and evaluation. However, existing simulators only support evaluations of protocols and software aspects of sensornet design. Thus they cannot accurately capture the significant impacts of various hardware designs on sensornet performance. To fill in the gap, we proposed SUNSHINE, a scalable hardware-software cross-domain simulator for sensornet applications. SUNSHINE is the first sensornet simulator that effectively supports joint evaluation and design of sensor hardware and software performance in a networked context. SUNSHINE captures the performance of network protocols, software and hardware through the integration of two modules: a network simulator TOSSIM [1] and hardware-software simulator P-Sim composed of an instruction-set simulator SimulAVR [2] and a hardware simulator GEZEL [3]. This thesis focuses on the integration of TOSSIM and P-Sim. It discusses the integration design considerations and explains how to address several integration challenges: time conversion, data conversion, and time synchronization. Some experiments are also given to demonstrate SUNSHINEâ s cross-domain simulation capability, showing SUNSHINE's strength by integrating simulators from different domains.
Master of Science

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Bücher zum Thema "Simulation – Hardware – Software"

Wells, George James. Hardware emulation and real-time simulation strategies for the concurrent development of microsatellite hardware and software. Toronto: Department of Aerospace Engineering, University of Toronto, 2001.

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Aldama, Alvaro A. Filtering Techniques for Turbulent Flow Simulation. Berlin, Heidelberg: Springer Berlin Heidelberg, 1990.

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Zhu, Yucai. Identification of Multivariable Industrial Processes: For Simulation, Diagnosis and Control. London: Springer London, 1993.

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Heller, Moshe R. Automotive Simulation '91: Proceedings of the 3rd European Cars/Trucks, Simulation Symposium Schliersee, Germany, October 1991. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991.

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John, Young, Ingalls V. Wayne, Hawkins Robert und Society for Computer Simulation, Hrsg. Simulation at the frontiers of science with papers on software and hardware systems for the simulationist: Proceedings from the Eastern Simulation Conferences, 10-12 March 1986, Norfolk, Virginia. San Diego, Calif: Society for Computer Simulation, 1986.

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Rao, A. Ravishankar. A Taxonomy for Texture Description and Identification. New York, NY: Springer US, 1990.

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Wunderlich, Hans-Joachim. Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Dordrecht: Springer Science+Business Media B.V., 2010.

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Phillip, Gold, IEEE Industrial Electronics Society, Keisoku Jidō Seigyo Gakkai (Japan) und Society of Photo-optical Instrumentation Engineers., Hrsg. IECON '87: Small computer applications, hardware and software : 1987 International Conference on Industrial Electronics, Control, and Instrumentation, 3 November 1987, Cambridge, Massachusetts. Bellingham, Wash., USA: SPIE--the Society of Photo-optical Instrumentation Engineers, 1987.

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S, Sunderam Vaidy, Hrsg. Computational science -- ICCS 2005: 5th international conference, Atlanta, GA, USA, May 22-25, 2005 : proceedings. Berlin: Springer, 2005.

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Computer Applications: Crashworthiness, Simulation, Hardware and Software. Society of Automotive Engineers Inc, 2001.

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Buchteile zum Thema "Simulation – Hardware – Software"

Dömer, Rainer, Guantao Liu und Tim Schmidt. „Parallel Simulation“. In Handbook of Hardware/Software Codesign, 533–64. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_19.

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Dömer, Rainer, Guantao Liu und Tim Schmidt. „Parallel Simulation“. In Handbook of Hardware/Software Codesign, 1–32. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_19-1.

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Mueller-Gritschneder, Daniel, und Andreas Gerstlauer. „Host-Compiled Simulation“. In Handbook of Hardware/Software Codesign, 593–619. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_18.

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Mueller-Gritschneder, Daniel, und Andreas Gerstlauer. „Host-Compiled Simulation“. In Handbook of Hardware/Software Codesign, 1–27. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_18-1.

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Chang, W.-T., A. Kalavade und E. A. Lee. „Effective Heterogenous Design and Co-Simulation“. In Hardware/Software Co-Design, 187–212. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2_8.

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Bringmann, Oliver, Sebastian Ottlik und Alexander Viehl. „Precise Software Timing Simulation Considering Execution Contexts“. In Handbook of Hardware/Software Codesign, 621–51. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_21.

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Bringmann, Oliver, Sebastian Ottlik und Alexander Viehl. „Precise Software Timing Simulation Considering Execution Contexts“. In Handbook of Hardware/Software Codesign, 1–31. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_21-1.

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Paul, John, Elena Guralnik, Anatoly Koyfman, Amir Nahir und Subrat K. Panda. „Leveraging Accelerated Simulation for Floating-Point Regression“. In Hardware and Software: Verification and Testing, 118–31. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3_15.

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Pierre, Laurence. „VHDL: A Hardware Description Language and its Simulation Semantics“. In Software Specification Methods, 113–30. London: Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0701-9_7.

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Katelman, Michael, und José Meseguer. „vlogsl: A Strategy Language for Simulation-Based Verification of Hardware“. In Hardware and Software: Verification and Testing, 129–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19583-9_14.

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Konferenzberichte zum Thema "Simulation – Hardware – Software"

Keutzer, Kurt. „Hardware/software co-simulation“. In the 31st annual conference. New York, New York, USA: ACM Press, 1994. http://dx.doi.org/10.1145/196244.196458.

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Stroph, R. „Hardware and software fault simulation“. In International Conference on Simulation (1998). IEE, 1998. http://dx.doi.org/10.1049/cp:19980672.

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Dassatti, Alberto, und Roberto Rigamonti. „Heterogeneous Hardware from Homogeneous Software“. In 2017 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2017. http://dx.doi.org/10.1109/hpcs.2017.153.

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Cheung, Ping Hang, Kecheng Hao und Fei Xie. „Component-Based Hardware/Software Co-Simulation“. In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341479.

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Blumer, Aric D., und Cameron D. Patterson. „Hardware/Software Process Migration and RTL Simulation“. In 2007 International Conference on Field Programmable Logic and Applications. IEEE, 2007. http://dx.doi.org/10.1109/fpl.2007.4380722.

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Schnaider, Benny, und Einat Yogev. „Software development in a hardware simulation environment“. In the 33rd annual conference. New York, New York, USA: ACM Press, 1996. http://dx.doi.org/10.1145/240518.240647.

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Adileh, Almutaz, Cecilia Gonzalez-Alvarez, Juan Miguel De Haro Ruiz und Lieven Eeckhout. „Racing to Hardware-Validated Simulation“. In 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 2019. http://dx.doi.org/10.1109/ispass.2019.00014.

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Quraishi, Masudul H., Hessam S. Sarjoughian und Soroosh Gholami. „CO-SIMULATION OF HARDWARE RTL AND SOFTWARE SYSTEM USING FMI“. In 2018 Winter Simulation Conference (WSC). IEEE, 2018. http://dx.doi.org/10.1109/wsc.2018.8632395.

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Tabbara, Bassam, Enrica Filippi und Luciano Lavagno. „Fast hardware-software co-simulation using VHDL models“. In the conference. New York, New York, USA: ACM Press, 1999. http://dx.doi.org/10.1145/307418.307511.

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Chupilko, Mikhail, und Alexander Protsenko. „Simulation-based Hardware Verification Back-end: Diagnostics“. In Spring/Summer Young Researchers' Colloquium on Software Engineering. Institute for System Programming of the Russian Academy of Sciences, 2014. http://dx.doi.org/10.15514/syrcose-2014-8-18.

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Berichte der Organisationen zum Thema "Simulation – Hardware – Software"

Kennedy, R. S., K. S. Berbaum und M. G. Smith. Correlating Visual Scene Elements with Simulator Sickness Incidence: Hardware and Software Development. Fort Belvoir, VA: Defense Technical Information Center, Oktober 1991. http://dx.doi.org/10.21236/ada252235.

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