Dissertationen zum Thema „Sigma-delta continuous-time bandpass modulator“
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1
Yang, Xi S. M. Massachusetts Institute of Technology. „Design of a continuous-time bandpass delta-sigma modulator“. Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87939.
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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 103-105).
An 8th-order continuous-time (CT) bandpass delta-sigma modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signal-to- noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order system, achieving a maximum stable input range of -1.9 dBFS. A 2.5-V/1.2-V dual-supply loop filter with a feed-forward coupling path has been proposed to suppress noise and distortion. On the transistor level, a 5th -order dual-supply feed-forward operational amplifier (op amp) and a 4th-order single-supply feed-forward op amp have been designed to enable high modulator linearity and coefficient accuracy.
by Xi Yang.
S.M.
2
Liu, Xuemei. „Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications“. Texas A&M University, 2004. http://hdl.handle.net/1969.1/3257.
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Bandpass sigma-delta modulators combine oversampling and noise shaping to get
very high resolution in a limited bandwidth. They are widely used in applications that
require narrowband high-resolution conversion at high frequencies. In recent years interests
have been seen in wireless system and software radio using sigma-delta modulators to
digitize signals near the front end of radio receivers. Such applications necessitate clocking
the modulators at a high frequency (MHz or above). Therefore a loop filter is required in
continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime
circuits (e.g., using switched capacitors) where the maximum clocking rate is limited
by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry.
In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking
at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new
calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the
modulator. The continuous-time loop filter is based on Gm-C resonators. A novel
transconductance amplifier has been developed with high linearity at high frequency. Qfactor
of filter is enhanced by tunable negative impedance which cancels the finite output
impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal
standard analog CMOS technology. Postlayout simulation in CADENCE
demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1
MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ±
1.65V.
3
Mariano, André Augusto. „Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications“. Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13644/document.
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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHzWireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz
4
Mahmoud, Doaa. „Convertisseur analogique-numérique de type Sigma-Delta Passe-Bande avec résonateurs à un et deux amplificateurs“. Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS288.
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Le récepteur radio logicielle (SDR) est une technique prometteuse pour les futurs récepteurs adaptés à une variété de protocoles. Il numérise le signal RF directement en basse fréquence. Nous proposons un récepteur SDR basé sur un modulateur sigma-delta à temps continu passe-bande (CT BP ). Nous nous concentrons sur les résonateurs RC actifs pour diminuer la surface du circuit. Nous ciblons les applications au voisinage de 400 MHz, à savoir Advanced Research and Global Observation Satellite (ARGOS), Medical Implant Communication Service (MICS), Automobile Keyless system et Industrial, Scientific and Medical (ISM). Nous présentons une nouvelle comparaison détaillée entre le modulateur CT BP à résonateur à deux amplificateurs et le modulateur CT BP à résonateur à un amplificateur. Les deux modulateurs sont conçus à l'aide de transistors MOS en technologie FDSOI-28nm, où nous utilisons la polarisation du caisson pour compenser les variations de processus, de tension et de températureSoftware defined radio receiver is a promising technique for future receivers which provides a variety of protocols. It digitizes the RF signal directly to low-frequency. We propose an SDR receiver based on a bandpass sigma delta modulator. The most essential element is the loop filter, there are two main configurations, an LC tank resonator and an active RC resonator. We focus on the active RC resonators for a low chip area. We target applications in the vicinity of 400 MHz, namely Advanced Research and Global Observation Satellite, Medical Implant Communication Service. We introduce a new comparison between the two-op-amp resonator CT BP sigma delta modulator and the one-op-amp resonator CT BP sigma delta modulator. We study the sensitivity of the quality factor and the signal to noise ratio to the DC-gain op-amps in two-op-amp resonator sigma delta modulator. It also shows how, in one-op-amp resonator sigma delta modulator, the quality factor and the signal to noise ratio, are very sensitive to any variations in the capacitors values for limited DC-gain op-amps. We establish a mathematical model of the thermal-noise behaviour for two-op-amp resonator CT BP sigma delta modulator. This model matches the circuit simulator results with a good accuracy. Furthermore, we demonstrate that a high quality factor (>100) of the two-op-amp resonators can be achieved by selecting the proper value of the integrator gain at a moderate DC-gain op-amp (35dB). Both sigma delta modulators are designed using flipped-well devices on fully depleted silicon on insulator technology, where we use body biasing to compensate the process, voltage and temperature variations
5
Ding, Chongjun [Verfasser], und Yiannos [Akademischer Betreuer] Manoli. „Design study of high-speed continuous-time delta-sigma modulator“. Freiburg : Universität, 2016. http://d-nb.info/1122647026/34.
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6
Juang, Philip Weimin 1978. „A continuous time sigma-delta modulator for digitizing carrier band measurements“. Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86681.
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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 135-136).
by Philip Weimin Juang.
M.Eng.
7
Chi, Jiazuo. „Micro-Power Inverter-Based Continuous-Time Sigma-Delta Modulator for Biosensor Applications“. Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177367.
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Biosensor applications have made promising progress during the last decade, presenting potentials and challenges at the same time. Meanwhile, digital signal processing (DSP) has become even more powerful than before, due to Moore's Law. Bridging the biosensor applications and the digital circuits, analog-to-digital converters (ADCs) are a critical block that inuences the performance of the entire system, in terms of speed, accuracy and power. Particularly, incremental ΣΔ (IΣΔ) ADCs have recently received increasing research interest because of their high-resolution feature and the ability to time-multiplex different channels of input signals, making them especially suitable for neuro-science studies and brain-computer-interface (BCI). However, IΣΔ ADCs are less power-ecient than traditional ΣΔ ADCs. To improve the power eciency and reduce the chip size, an inverter-based continuous-time (CT) Sigma-Delta (ΣΔ) modulator is proposed, to be integrated in a two-step I(ΣΔ) ADC previously designed. Inverter-based operational transconductance amplifers (OTA) have recently demonstrated their high power efficiency in multiple ΣΔ modulators, most of which are discrete-time (DT) implementation. CT implementation is investigated in this thesis for the possibility to further reduce power consumption, due to its more relaxed requirements on bandwidth and settling compared to the DT counterpart. In the circuit implementation of the modulator, fully-differential topology is used in inverter-based CT ΣΔ ADCs for the rst time. Compared to pseudo-differential topology, fully-differential topology has more precise control on the operating point and the quiescent power. The post-layout simulation result shows that the modulator achieves a peak SNDR of 58.1 dB, and a dynamic range of 65.9 dB. The entire modulator consumes 1.28 μW from a 1.2 V supply voltage, on a chip area of only 0.07 mm2. This corresponds to a FoM of 243 fJ/(conv. step).
8
Chu, Chao [Verfasser]. „A high speed/high linearity continuous-time delta-sigma modulator / Chao Chu“. Ulm : Universität Ulm, 2017. http://d-nb.info/1147848033/34.
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9
McGinnis, Ryan Edward. „Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter“. Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.
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10
Yoon, Do Yeon. „A continuous-time multi-stage noise-shaping delta-sigma modulator with analog delay“. Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75689.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 73-75).
A new continuous-time multi-stage noise-shaping delta-sigma modulator has been designed. This modulator provides high resolution and robust stability characteristics which are the primary advantages of the conventional multi-stage noise-shaping architecture. At the same time, previous critical challenges that degraded the overall performance of multi-stage noise-shaping delta-sigma modulators are eliminated through several unique techniques. Additionally, these techniques relax the requirements of each component of the proposed delta-sigma modulator. As a result, this new delta-sigma modulator architecture can provide several advantages that are not obtainable in other modulator architectures.
by Do Yeon Yoon.
S.M.
11
Thandri, Bharath Kumar. „Design of RF/IF analog to digital converters for software radio communication receivers“. Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.
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Software radio architecture can support multiple standards by performing analogto-
digital (A/D) conversion of the radio frequency (RF) signals and running
reconfigurable software programs on the backend digital signal processor (DSP). A
slight variation of this architecture is the software defined radio architecture in which the
A/D conversion is performed on intermediate frequency (IF) signals after a single down
conversion.
The first part of this research deals with the design and implementation of a
fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters
for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC
architecture is proposed which uses only non-return to zero feedback digital to analog
converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz
and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ±
1.25 V supply.
The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF
digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA
architecture combines both cross coupling and source degeneration in order to obtain
good IM3 performance. A system level digital tuning scheme is proposed to tune the
ADC performance over process, voltage and temperature variations. The output bit
stream of the ADC is captured using an external DSP, where a software tuning algorithm
tunes the ADC parameters for best SNR performance. The IF ADC was designed in
TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V
supply.
12
Yoon, Do Yeon. „A continuous-time multi-stage noise-shaping delta-sigma modulator for next generation wireless applications“. Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99854.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 115-121).
A continuous-time (CT) delta-sigma ([delta][sigma]) modulator for modern wireless communication applications is investigated in this thesis. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function (NTF). In order to increase the effective order of the NTF, a 2-loop sturdy multi-stage noise-shaping (SMASH) architecture is utilized. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of the DT implementation. Furthermore, the proposed CT SMASH architecture provides a better quantization noise suppression capability than the DT SMASH architecture by more completely canceling the quantization noise from the first loop. The CT SMASH architecture is implemented with several circuit techniques suitable for high operation speed. These circuit techniques allow the proposed CT [delta][sigma] modulator to achieve wide bandwidth, high resolution, and low power consumption for modern wireless communication applications. As a result, the prototype fabricated in 28nm CMOS achieves DR of 85dB, peak SNDR of 74.9dB, SFDR of 89.3dBc and Schreier FOM of 172.9dB over a 50MHz bandwidth at a 1.8GHz sampling frequency.
by Do Yeon Yoon.
Ph. D.
13
Melo, João Luís Alvernaz de. „Design of a Continuous-Time (CT) Sigma-Delta modulator for class D audio power amplifiers“. Master's thesis, Faculdade de Ciências e Tecnologia, 2010. http://hdl.handle.net/10362/13154.
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Pěček, Lukáš. „Návrh Sigma Delta AD převodníku pro senzorové aplikace“. Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-317221.
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This diploma thesis deals with the design of a sigma delta AD converter for a sensor application of junction temperature measurement in the automotive environment. A modified continuous time current mode modulator structure was designed. Its advantage lies in shifting and extending an input voltage range to work with signals from 0 V to 1,2 with a high impedance input and a relatively low hardware complexity. The functionality was verified by a behavioral model in the Simulink environment and then by transistor level simulation in CADENCE environment using ONC18/I4T technology.
15
Dobson, Kevin. „A 100 MHz 6th Order Continuous Time Band-Pass Sigma Delta Modulator with Active Inductor Resonators“. Thesis, The George Washington University, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10085732.
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Band-Pass Sigma Delta Modulators allow for the digitization of a carrier signal directly without frequency down conversion to baseband. This results in a simpler and more economical RF receiver front end. The holy grail of signal processing is to develop a Band-Pass Analog to Digital Converter operating at a high enough frequency to digitize high frequency RF signals such as Wi-Fi or cell phone carriers without the need for complicated Filters, Mixers and Amplifiers in the receiver front end.
Continuous Time Band-Pass Sigma Delta Analog to Digital Converters are potentially one technology that can be used to realize this goal because of their ability to operate at higher frequencies than their switched capacitor counterparts. Current Continuous Time Band-Pass Sigma Delta Modulators utilize LC circuits as resonators. This leads to a design that occupies a large die area. In fact, in many designs the area of the spiral inductors occupies more than half the design area. Another drawback of using spiral inductors is the limited quality factor. In order for there to be a high dynamic range at the output of a sigma delta modulator it is necessary to have resonators with high quality factors. We investigate the effects of replacing spiral inductors with high quality factor active inductor resonators with negative impedance circuits.
CMOS is a fairly cheap technology when compared to other ASIC design technologies. It also offers lower power consumption but its operating frequencies are somewhat lower. We have chosen to use CMOS technology for our design because of its economy and low power consumption. We have been able to design and simulate a 6th order, continuous time Band-Pass Sigma Delta modulator in IBM 0.18u cmrf7sf CMOS technology. Cadence schematic simulations show a modulator with a high dynamic range and decreased area usage.
Pad to pad simulation of the extracted layout in Cadence yields an enhanced peak SNDR of 73 dB with a noise bandwidth of 36 kHz and a power consumption of 12 mW. This modulator occupies 2.05 mm2 of active die area.
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Pereira, Nuno Ruben Ferreira. „Implementation of a sigma delta modulator for a class D audio power amplifier“. Master's thesis, Faculdade de Ciências e Tecnologia, 2013. http://hdl.handle.net/10362/10046.
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ALGHAMDI, ALI SAAD. „DESIGN AND PERFORMANCE ANALYSIS OF AN OPTICAL PROTERETIC DELTA-SIGMA MODULATOR“. OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1331.
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This dissertation is a contribution toward developing all-optical binary delta sigma modulator (BDSM) [27] by changing its bistability to proteretic bistability in order to increase the modulator bandwidth frequency. An innovative delta sigma modulator called proteretic binary delta sigma modulator (PBDSM), which is optically compatible, is investigated theoretically and by modeling and simulation and its bandwidth superiority is proven. The time interval of PBDSM Δt calculation is driven and dynamic performance measure of PBDSM comparing to previous related work is computed, modeled and simulated. Modeling and simulations are based on Matlab-Simulink for ideal environment testing. The basic components of BDSM are the leaky integrator and the bi-stable device. Thus, the focus was on improving the bi-stable device to overcome the bandwidth limitation toward THz modulation frequency in optical domain. Consequently, proteresis bistability was investigated in semi-practical domain, using Matlab-Simulink function, for clear realization of its input-output characteristics and compared with the corresponding hysteresis bistability. The contribution in this research, regarding proteresis bi-stable device design, can be implemented in current technologies, both optical and electrical, of continuous-time delta sigma modulation. Furthermore, the new design showed capability and more flexibility in manipulating its output form and it showed more control on the way of conducting delta sigma modulator error correction.
18
Talebzadeh, Jafar. „A continuous-time time-interleaved delta-sigma modulator with a novel solution to the delayless feedback path problem for high bandwidth applications“. Thesis, University of Westminster, 2017. https://westminsterresearch.westminster.ac.uk/item/q3z21/a-continuous-time-time-interleaved-delta-sigma-modulator-with-a-novel-solution-to-the-delayless-feedback-path-problem-for-high-bandwidth-applications.
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Öberg, Eric, und Gustav Kindeskog. „16 GS/s Continuous-Time ΣΔ Modulator in a 22 nm SOI Process : a Simulation and Feasibility Study“. Thesis, Linköpings universitet, Tekniska fakulteten, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-155781.
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With a reference specification model in terms of 8 GS/s Sigma Delta Modulator in a 28 nm CMOS process consuming 890 mW, the purpose with this thesis is to construct a similar and simpler model but with higher specification demands. In a 22 nm SOI process with an input signal bandwidth of 500 MHz sampled at 16 GS/s with a power consumption below 2 W, the objective is to design a Continuous-Time Sigma Delta Modulator with verified simulated functionality on a transistor level basis. This specification is accomplished - with a power consumption in total of 75 mW. The design methodology is divided into an integrator part along with a quantizer and feedback DAC part. A top-down strategy is carried out starting with an ideal high level Verilog-A model for the complete system, followed by a hardware implementation on transistor level.
20
Atac, Aytac [Verfasser], Stefan [Akademischer Betreuer] Heinen und Jürgen [Akademischer Betreuer] Oehm. „Design of Low Power Reconfigurable Continuous Time Quadrature Bandpass $\Delta$ $\Sigma$ ADCs for Multi-Standard SoC / Aytac Atac ; Stefan Heinen, Jürgen Oehm“. Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1157016251/34.
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PATEL, VIPUL J. „BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS“. University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.
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Aguirre, Paulo Cesar Comassetto de. „Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD“. reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/105065.
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Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e empregados para a conversão de sinais de baixa frequência e com operação em tempo discreto (DT), esta classe de conversores têm evoluído e nos últimos anos está sendo desenvolvida para operar em tempo contínuo e ser empregada na conversão de sinais com frequências de centenas de kHz a dezenas de MHz. Neste trabalho, os moduladores sigma-delta em tempo contínuo (SDMs-CT) são estudados, visando sua aplicação à conversão analógico-digital (AD). Os SDMs-CT oferecem vantagens significativas sobre seus homólogos em tempo discreto, como menor consumo de energia, maior largura de banda do sinal de entrada e filtro anti-alias, do inglês anti-alias filter (AAF), implícito. Entretanto, os SDMs-CT apresentam limitações adicionais, responsáveis pela degradação de seu desempenho, como os efeitos do jitter do sinal de relógio, o atraso excessivo do laço de realimentação, do inglês Excess Loop Delay (ELD), e as limitações impostas aos integradores analógicos. Após o estudo e análise de SDMs-CT e de suas limitações, foi desenvolvido um modelo comportamental no ambiente Matlab/Simulink R , que permite a simulação do impacto destas limitações no modulador, possibilitando a obtenção de uma estimativa mais aproximada do seu desempenho. Com base nestas simulações foi possível a determinação das especificações mínimas de cada bloco analógico que compõe o modulador (como o slew rate, a frequência de ganho unitário (fu) e o ganho DC dos amplificadores operacionais utilizados nos integradores) e os valores toleráveis de ELD e jitter do sinal de relógio. Adicionalmente, neste trabalho foi desenvolvida uma metodologia para simulação de SDMs-CT compostos por DACs a capacitor chaveado e resistor, do inglês Switched-Capacitor-Resistor (SCR). Com base neste modelo e no estudo das diferentes topologias de SDMs, um circuito foi desenvolvido para aplicação em receptores de RF, sendo do tipo passa-baixas de laço único, do inglês single-loop, single-bit, de terceira ordem, voltado ao baixo consumo de energia. Este circuito foi desenvolvido em tecnologia CMOS IBM de 130 nanômetros, tendo sido enviado para fabricação. Através das simulações pós-leiaute realizadas espera-se que seu desempenho fique próximo ao que tem sido publicado recentemente sobre SDMs-CT passa-baixas de laço único e single-bit.Analog-to-Digital Converters (ADCs) play a fundamental role in the implementation of current systems-on-chip (SoC). Due to the requirements of these systems and the tradeoffs between the main ADCs characteristics, such as signal bandwidth, power consumption and accuracy, many topologies and strategies for their implementation in integrated circuits (ICs) have been developed through the ages. Among these topologies, the sigmadelta converters (SDC) have highlighted the versatility combined with low power consumption and excellent accuracy. Initially developed and used for the conversion of low frequency signals and operation in the discrete time (DT) domain, this class of converters have been evolved and developed over the past to operate in continuous time domain for the conversion of signals with frequencies of hundreds of kHz up to tens of MHz. In this work, continuous time sigma-delta modulators (CT-SDMs) are studied focusing its application to the analog-to-digital (AD) conversion. CT-SDMs offer significant advantages over their discrete-time counterparts, such as lower power consumption, higher input signal bandwidth and implicit anti-alias filter (AAF). However, CT-SDMs present additional limitations that are responsible for their performance degradation, such as the clock jitter, Excess Loop Delay (ELD) and the limitations imposed on the analog integrators. After the study and analysis of CT-SDMs and their performance limitations, a behavioral model approach was developed in the Matlab/Simulink R environment, which allows the simulation of the limitations impact on the modulator, allowing the obteinment of a more accurate estimate of its performance. Based on these simulations it was possible to determine the minimum specifications for each block that composes the analog modulator (such as slew rate, the unity gain frequency (fu) and the DC gain of the operational amplifiers used in integrators) and tolerable values of ELD and clock jitter. Additionally, it was developed in this work a methodology for simulate CT-SDMs with Switched-Capacitor- Resistor (SCR) DACs that provide exponential waveforms. Based on this model and the study of different SDMs topologies, it was developed a low-pass, single-loop, single-bit, third order circuit focused on low-power intended for application in RF receivers. This circuit was developed in an IBM 130 nanometers CMOS technology, and was send to manufacturing. Based on the post-layout simulations it is expected to have performance close to what has been recently published of low-pass, single-loop, single-bit CT-SDMs.
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Hardy, Emmanuel. „Etude et développement d'un amplificateur audio de classe D intégré haute performance et basse consommation“. Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4722/document.
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De nombreux dispositifs embarqués récents comme les téléphones portables, les GPS ou encore les consoles de jeu, possèdent un ou des haut-parleurs, chacun étant piloté par un amplificateur audio sur circuit intégré. De tels amplificateurs audio doivent répondre le mieux possible à quatre contraintes : une qualité audio satisfaisante, une immunité aux perturbations induites par le système, une faible consommation et une surface de silicium minimale. Ce travail de thèse sous contrat CIFRE a pour origine la création de l’entreprise Primachip en mai 2009 par Christian Dufaza et Hassan Ihs. Cette startup a été bâtie sur une architecture innovante d’amplificateur audio de classe D intégré. Son originalité repose sur le principe de rétroaction partielle qui s’applique à une boucle contenant un modulateur numérique Delta Sigma (ΔΣ) qui pilote l’étage de puissance et un convertisseur analogique-numérique (ADC) effectuant la rétroaction. Cela permet d’obtenir la stabilité de cette boucle tout en offrant une excellente réjection des bruits de l’étage de puissance. Un prototype sur silicium de l’architecture d’amplificateur de classe D numérique a été conçu et fabriqué. Un nouvel ADC ΔΣ temps continu a été développé pour ce prototype, afin d’obtenir des performances supérieures ou égales à l’état de l’art. Les résultats obtenus sur le circuit se sont révélés encourageants, bien que toutes les spécifications n’aient pas été atteintes. L’analyse des erreurs de ce premier circuit doit permettre la réalisation d’un amplificateur intégré exploitant au mieux cette architecture de classe D numériqueMost current embedded devices, such as smartphones, GPS or portable consoles, feature one speaker or more, those speakers being driven by an integrated audio amplifier. This type of amplifier must meet four specifications: an adequate audio quality, to be immune to system disturbances, low power consumption and the smallest silicon area. This work takes its origin from the creation of Primachip in May 2009 by Christian Dufaza and Hassan Ihs. The aim of this startup was to develop and sell an innovative audio class-D amplifier for mobile market: the digital class-D concept. A partnership with the IM2NP laboratory was decided to propose a PhD topic under CIFRE contract (PhD in an industrial environment), in order to study and improve the amplifier architecture. Its originality is in the partial feedback concept which applies to a loop made of a digital ΔΣ modulator driving the power stage, with an analogue-to-digital converter (ADC) in the feedback path. It makes it possible to achieve stability while offering an outstanding power supply rejection. An integrated prototype of the class-D amplifier was designed, fabricated and evaluated. A new continuous-time ΔΣ ADC has been added to enable the digital class-D loop to achieve performances superior or equal to state of the art. The circuit measurement results were encouraging, although not ideal. The analysis of the prototype errors was performed. The conclusions should allow the design of an integrated audio amplifier making the best of the digital class-D architecture
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Baltolu, Anthony. „Etude et conception analogique d’architectures d’acquisition acoustique très faible consommation pour applications mobiles“. Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0339/document.
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Les récentes avancées technologiques des microphones de type microsystème électromécanique (MEMS) leurs permettent une utilisation sur une large gamme d’amplitudes sonores. Leur niveau de bruit ayant baissé, il devient possible de capter des sons provenant d’une distance plus lointaine, tandis que l’augmentation de leur pression acoustique maximale leur permet de ne pas saturer dans un environnement très bruyant de type concert ou évènement sportif. Ainsi le système électronique de conversion analogique-numérique connecté au microphone devient l’élément limitant les performances du système d’acquisition acoustique. Un besoin de nouvelles architectures de conversion analogique-numérique ayant une plage dynamique augmentée se fait donc ressentir. Par ailleurs, ces microphones étant de plus en plus utilisés dans des systèmes fonctionnant sur batterie, la contrainte de limitation de la consommation devient importante.Dans la bande de fréquences audio, les convertisseurs analogiques-numériques de type sigma-delta sont les plus aptes à obtenir une grande résolution combinée à une faible consommation. Ils sont divisés en deux grandes familles: ceux à temps discret utilisant principalement des circuits à capacités commutées, et ceux à temps continu utilisant des circuits classiques. Cette thèse se concentre sur l’étude et la conception de chacun des deux types de convertisseurs sigma delta, en insistant sur la faible consommation, le faible coût de production (surface occupée) et la robustesse du circuit, cela en vue d’une production de masse pour équipements portables.La conception d’un convertisseur analogique numérique de type sigma-delta à temps discret a été réalisé, ce dernier atteignant un rapport signal sur bruit de 100 décibels sur une bande de 24kHz, pour une puissance consommée de seulement 480μW. Pour limiter la consommation, de nouveaux amplificateurs à base d’inverseurs sont utilisés, et dont la robustesse contre les variations du procédé de fabrication ou de la température a été améliorée. Les spécifications ont été définies grâce au développement d’un modèle de haut-niveau précis, ce qui permet d’éviter le surdimensionnement tout en atteignant les performances voulues. Enfin, un grand ratio de suréchantillonnage a été choisi afin de réduire l’espace utilisé par les capacités commutées, minimisant le coût de fabrication.Après une étude théorique de l’équivalence entre les modulateurs sigma-delta à temps discret et à temps continu, ainsi que des spécificités propres aux modulateurs à temps continu, une réalisation de ces derniers a été effectuée. Celui-ci atteint un rapport signal sur bruit de 95 décibels sur une bande de fréquence de 24kHz, tout en consommant 142μW. Pour réduire la consommation ainsi que l’espace utilisé, un filtre de boucle du second-ordre a été réalisé avec un seul amplificateur, et le quantificateur fait aussi office d’intégrateur grâce à l’utilisation d’une structure d’oscillateurs contrôlés en tension. Ce quantificateur à base d’oscillateurs est réalisé par des cellules numériques, réduisant la consommation et l’espace utilisé, mais est hautement non-linéaire. Cette non-linéarité a été prise en compte par des choix architecturaux afin de ne pas réduire les performances finales du modulateurThe recent technological advances in microelectromechanical system (MEMS) microphones allow them to be used on a large sound amplitude range. Due to their lower noise level, it becomes possible to capture sound from a faraway distance, while their increased acoustic overload point gives them the ability to capture sound without saturation in a loud environment like a concert or a sport event. Thus, the electronic analog / digital conversion system connected to the microphone becomes the limiting element of the acoustic acquisition system performance. There is then a need for a new analog / digital conversion architecture which has an increased dynamic range. Furthermore, since more and more of these microphones are used in battery-powered devices, the power consumption limitation constraint becomes of high importance.In the audio frequency band, the sigma-delta analog / digital converters are the ones most able to provide a high dynamic range combined to a limited power consumption. They are split in two families: the discrete-time ones using switched-capacitors circuits and the continuous-time ones using more classical structures. This thesis concentrates on the study and the design of both of these two types of sigma-delta converters, with an emphasis on the low-power consumption, the low production cost (area occupied) and the circuit robustness, in sight of a mass production for portable devices.A discrete-time sigma-delta modulator design has been made, the latter reaching a signal to noise ratio of 100dB on a 24kHz frequency bandwidth, for a power consumption of only 480μW. To limit the power consumption, new inverter-based amplifiers are used, with an improved robustness against the variations of the fabrication process or the temperature. Amplifier specifications are obtained thanks to an accurate high-level model developed, which allows to avoid over-design while ensuring that the wanted performances are reached. Finally, a large oversampling ratio has been used to reduce the switched-capacitors area, lowering the modulator cost.After a theoretical study of the equivalence between discrete-time and continuous-time modulators, and of continuous-time modulators specificities, a design of the latter has been made too. It reaches a signal to noise ratio of 95dB on a 24kHz bandwidth, while consuming 142μW. To reduce the power consumption and the occupied area, a second-order loop filter is implemented using a single amplifier, and the quantizer uses a VCO-based structure that provides inherently an integrating stage. The VCO-based quantizer is made using digital cells, lowering the consumption and area, but is highly non-linear. This non-linearity has been handled by architectural choices to not influence the final modulator performances
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Marefat, Fatemeh. „Toward Cuffless Blood Pressure Monitoring: Integrated Microsystems for Implantable Recording of Photoplethysmogram“. Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1595441087168539.
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Lu, Cho-Ying. „Calibrated Continuous-Time Sigma-Delta Modulators“. 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7914.
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To provide more information mobility, many wireless communication systems such
as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication
networks have been recently developed. Recent efforts have been made to build the allin-
one next generation device which integrates a large number of wireless services into a
single receiving path in order to raise the competitiveness of the device. Among all the
receiver architectures, the high-IF receiver presents several unique properties for the
next generation receiver by digitalizing the signal at the intermediate frequency around a
few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols,
equalization, etc., are all determined in a software platform that runs in the digital signal
processor (DSP) or FPGA. The specifications for most of front-end building blocks are
relaxed, except the analog-to-digital converter (ADC). The requirements of large
bandwidth, high operational frequency and high resolution make the design of the ADC
very challenging.
Solving the bottleneck associated with the high-IF receiver architecture is a major
focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to
accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture
employs an 800 MHz clock frequency. By making use of a unique software-based
calibration scheme together with the tuning properties of the bandpass filters developed
under the umbrella of this project, the ADC performance is optimized automatically to
fulfill all requirements for the high-IF architecture.
In a separate project, other critical design issues for continuous-time sigma-delta
ADCs are addressed, especially the issues related to unit current source mismatches in
multi-level DACs as well as excess loop delays that may cause loop instability. The
reported solutions are revisited to find more efficient architectures. The aforementioned
techniques are used for the design of a 25MHz bandwidth lowpass continuous-time
sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX
applications. The prototype is designed by employing a level-to-pulse-width modulation
(PWM) converter followed by a single-level DAC in the feedback path to translate the
typical digital codes into PWM signals with the proposed pulse arrangement. Therefore,
the non-linearity issue from current source mismatch in multi-level DACs is prevented.
The jitter behavior and timing mismatch issue of the proposed time-based methods are
fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak
SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts
and effectiveness of time-based quantization and feedback.
Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS
0.18um technologies, which are the most popular in today?s consumer electronics
industry.
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Tu, Ming-Hung, und 杜明鴻. „A 138.24MHz Continuous Time BandPass Sigma-Delta Modulator For Digital IF Application“. Thesis, 2004. http://ndltd.ncl.edu.tw/handle/94155799931582976824.
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碩士淡江大學
電機工程學系
92
Analog to digital converters have been widely used in digital signal processing, and over-sampling and sigma-delta modulation techniques are used in analog to digital conversion interface of modern very large scaled integrated circuits. Due to over-sampling characteristics, the sigma-delta modulators usually are limited on the application of voice band signals. As the integrated circuit process improvement, it makes many researches transfer to applications of wide-bandwidth gradually, such as xDSL, Bluetooth, GSM ,and WCDMA. Since cellular telephony made the transition from the first-generation analog systems to the second—generation (2G) digital systems less than a decade ago, mobile telecommunications have experienced tremendous growth. Today, several different 2G standards are used worldwide, of which the global system for mobile communication (GSM) has highest penetration. Driven by market forces, the number of second-generation subscribers is expected to increase further in the next few years. On the other hand, the demand for higher system capacity and data rates has led to the development of third-generation (3G) systems, which are in their final stage of standardization now and will be deployed in many parts of the world in the next couple of years. Dictated by the continuing popularity of exisited 2G services and the time needed to build up equivalent coverage, quality, and variety of service, a 3G cellular network requires multi-standard mobile terminals, to take advantage of both 2G and 3G services during the transition period. In this thesis, we want to design a band-pass sigma-delta modulator suitable for WCDMA application. The center frequency is 100MHz, and the bandwidth is 3.84MHz.Because of the limitation on sampling frequency of the traditional switched-capacitor circuit (usually below 100MHz), even though double sampling or pseudo two-path techniques are used, the band-pass sigma-delta modulator’s center frequency is still below 50MHz.Therefore we use another approach continuous time circuit, to design the sigma-delta modulator. The impulse time invariant transformation is used to transfer the discrete time filter transfer function to the continuous-time filter transfer function. The continuous-time filter uses transconductance-capacitance circuits to fulfill the implementation. Its advantage is that it can work at a higher frequency band. In this manner, it can compensate the switched-capacitor circuit which cannot work at high the frequency band. Our circuit architecture is with multiple-feedback, its structure has two different one-bit digital-to-analog converters to control the feedback current. Our proposed band-pass sigma-delta modulators for wireless receiver application whose operating voltage is 1.8V；the center frequency is 138.24MHz；the sampling frequency is 553MHz, and the oversampling ratio is 72. The simulation result show that the bandwidth is 3.84MHz；the sampling frequency is 553MHz；the dynamic input range is 60dB and the maximum signal to noise ratio is 56 dB. Its input signal is 0.2V；the effective resolution is 9.5bits, and the total power dissipation is 75mW.
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Chu, Hung-Yuan, und 瞿鴻遠. „Design Methodology and Verification of a Continuous-Time Bandpass Delta-Sigma Modulator“. Thesis, 2007. http://ndltd.ncl.edu.tw/handle/21214096656339513926.
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碩士國立成功大學
電機工程學系碩博士班
95
In the design flow of circuits, building the behavior models is very important. The behavior of the system can be simulated and the result can be verified in a short time by using a higher level platform and the simpler user interface. Designing the circuit after confirming the simulation results of a behavior model helps the designers avoid making too many mistakes. From the searched literatures for the design of CT BP delta-sigma modulator, we found that some of them only focused on building a behavior model and others focused only on the circuit implementation. Almost none was found to consider both the behavior model and the physical implementation at the same time. Hence, we develop a top-down design flow using Simulink and Verilog-A for it to facilitate the design work. This paper presents a design methodology of a continuous-time(CT) Band-pass(BP) delta-sigma modulator which can simplify the design procedure. The models were built in SIMULINK and Cadence’ s Spectre environment. Finally, the flow is used in the design of a CT BP delta-sigma modulator which is applied to a WCDMA communication system. The center frequency of this modulator is at 100MHz and the internal quantizer operated at 400MHz clock frequency. The modulator is simulated in TSMC 0.35μm CMOS technology, at a supply voltage of 3.3V. The maximum SNR is 38.6dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.
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Wang, Chi-Yun, und 王麒雲. „A Fourth-Order Continuous-Time Bandpass RF Delta-Sigma Modulator for GPS L1 Band Application“. Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19253569830398418196.
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碩士臺灣大學
電子工程學研究所
98
This thesis describes the procedures from the system-level synthesis and design to circuit-level simulation and implementation of a fourth-order single-bit continuous-time bandpass RF delta-sigma ADC for GPS L1 band application. At least a 1.5-clock-cycle time slot is preserved in the modulator feedback path in the system-level design to relieve the speed requirements of quantizer comparison and DAC feedback. Thus, the excess loop delay and quantizer metastability issues usually occurred in GS/s-sampling delta sigma ADCs are both alleviated. Furthermore, only non-return-to-zero (NRZ) DACs are used in the modulator, the effect of clock jitter is mitigated. This ADC applies for direct digitization of the 1.57542-GHz GPS L1 band RF signal with a 6.297-GS/s sampling clock. A prototype ADC is fabricated in 65-nm SP CMOS technology. The circuit-level simulation results of the proposed ADC show a 61-dB signal-to-noise ratio (SNR) and a 62-dB input dynamic range (DR) over a 2-MHz signal bandwidth centered at 1.57542 GHz. The whole ADC consumes 29.85 mW under a 1-V supply voltage.
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Kim, Song-Bok [Verfasser]. „A contribution to continuous time quadrature bandpass sigma-delta modulators for low-IF receivers / vorgelegt von Song-Bok Kim“. 2009. http://d-nb.info/994623410/34.
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Pulincherry, Anurag. „A continuous time frequency translating delta Sigma Modulator“. Thesis, 2002. http://hdl.handle.net/1957/30250.
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This thesis presents a continuous time bandpass delta sigma modulator with
frequency translation inside the delta sigma loop. The input IF signal is down
converted to baseband after amplification by a low Q, wideband bandpass
resonator. The down converted IF signal is digitized by a continuous time, second
order lowpass delta sigma modulator. The output of the lowpass delta sigma
modulator is upconverted and fedback in to the low Q wideband bandpass
resonator. Unlike the conventional delta sigma modulators, sinusoidal pulses are
used for feedback. The system level design of the frequency translating delta sigma
modulator is discussed. A prototype frequency translating delta sigma modulator to
digitize IF signals at 100 MHz was designed in CMOS 0.35 μm process. Transistor
level simulation shows that 80 dB SNR is achievable at a power dissipation of 100
mW. The frequency translating delta sigma modulator is less sensitive to time delay
jitter in the DAC feedback pulse. If we use edge triggered sinusoid pulses for
feedback, the DAC jitter performance of frequency translating delta sigma
modulator will be better than that of conventional bandpass delta sigma modulator.Graduation date: 2003
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Chen, Po-Sheng, und 陳柏升. „Continuous-Time Delta-Sigma Modulator for Wireless Communication Application“. Thesis, 2010. http://ndltd.ncl.edu.tw/handle/11510817581099030852.
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碩士淡江大學
電機工程學系碩士班
98
With wireless networks and portable electronic products popularized in recent years, the goals of analog-to-digital converter (ADC) are gradually moving into the trend of high bandwidth, high resolution, and low power consumption. To contrast continuous-time (CT) architecture with discrete-time (DT) architecture, the CT architecture consumes less power than that of the DT architecture. Due to the complex derivation of mathematics, it is difficult to design a proper CT architecture. With the evolution of VLSI process technology, both the lower supply voltage and leakage current increase the difficulties of analog circuit design. This thesis tries to simplify the structure of CT ADC and analog part complexity of the design. We present a new architecture of CT analog-to-digital delta sigma modulator (DSM) in this thesis. Differing from the traditional method to design a CT DSM from the DT DSM needs to increase analog compensation paths or re-design the digital filters, the new approach uses digital filters to replace the analog compensation paths without re-designing digital filters. The new method simplifies the design procedural and induces the analog circuit complexity. This research tries to design a CT DSM for GSM / WCDMA / WiMAX applications. When operating at low speed mode, it will shut down the part of the circuit to save power. The circuit is designed by the TSMC 90nm 1p9m standard process; the supply voltage is 1.2V; bandwidths are 100k/2M/10M Hz; sampling frequencies are 40M/160M/320M Hz; oversampling rates(OSR) are 200/40/16. The greatest signal to noise distortion ratio are 85/70/61 dB, and the power consumptions are 4/6.4/15 mW(pre-simulations). In the implementation and post-simulations, because of the problems of RC-variation must be additional adjustments capacitors, the chip size and cost will increase, we only present WiMAX specifications.
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Liu, Jun-hong, und 劉俊宏. „Low-Power Continuous-Time Sigma-Delta Modulator for GSM“. Thesis, 2012. http://ndltd.ncl.edu.tw/handle/34006394311059440138.
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碩士國立中山大學
電機工程學系研究所
100
Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator. The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design. The proposed sigma-delta modulator used TSMC 0.18μm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW. Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.
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Yu-Chen, Sung. „Design of Continuous-Time Delta-Sigma Modulator for WCDMA Application“. 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0002-1407200501290000.
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Sung, Yu-Chen, und 宋育誠. „Design of Continuous-Time Delta-Sigma Modulator for WCDMA Application“. Thesis, 2005. http://ndltd.ncl.edu.tw/handle/25786057334637711160.
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碩士淡江大學
電機工程學系碩士班
93
The 3rd generation mobile communications standard (WCDMA), based on a wideband code division multiple access (W-CDMA) modulation scheme, will be available in the commercial market. The use of spread spectrum techniques requires high-speed baseband circuits (few MHz) with a moderate dynamic range (10~12 bit). A basic building block of such a WCDMA receiver is an analog-to-digital converter. Over-sampling and sigma-delta modulation techniques are used in the analog to digital conversion interface of modern very large scaled integrated circuits. Unlike Nyquist rate A/D converters, which need high-precision building blocks, A/D converters show low sensitivity to circuit imperfections. This technique is then well-suited for standard low-cost CMOS technologies dedicated to digital VLSI circuits. The recent high demand for wideband, high resolution A/D converters for telecommunication applications requires very high sampling frequencies. The continuously decreasing supply voltage of recent CMOS technologies is causing important limitations to the performances of SC circuits. High switch resistance limits the signal dynamic range and limits the sampling frequency. Some circuit techniques, like bootstrapping switch and switched-opamp, have been developed to overcome this problem. These techniques are rather complex and still limit the sampling frequency. Continuous-time (CT) circuits do not suffer from these limitations and are therefore capable of achieving higher performances in recent low-voltage CMOS processes. Input-signal sampling errors, like settling-time errors and charge injection, are other discrete-time (DT) problems that do not exist in CT circuits. In this thesis, we try to design a continuous-time low-pass sigma-delta modulator suitable for WCDMA application. The impulse time invariant transformation is used to transfer the discrete time filter transfer function to the continuous-time filter transfer function. The continuous-time modulator uses Active-RC Integrators circuits to fulfill the implementation. Our circuit architecture is with single-loop, and the multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivities. The operating voltage of our proposed low-pass sigma-delta modulators for WCDMA receiver application is 1.8V；the sampling frequency is 52MHz, and the oversampling ratio is 13. The simulation results show that the bandwidth is 2MHz；the sampling frequency is 52MHz；the dynamic input range is 75dB, and the maximum signal to noise ratio is 72 dB. Its input signal is 0.45V；the effective resolution is 12bits, and the total power dissipation is 6mW.
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wu, kuo-hsi, und 吳國璽. „Implementation of the continuous-time transconductor-capacitor Delta-Sigma modulator“. Thesis, 2007. http://ndltd.ncl.edu.tw/handle/6rkp74.
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碩士國立交通大學
電信工程系所
96
Because of the rapid growth of wireless communication, there has been more focus on analog-to-discrete converter (ADC) for wireless communication. Since the frequency is usually narrow-band in general wireless communication, in order to reduce the complexity of the architecture, we usually require the ADC has the ability of in-band anti-noise. Besides, it is important the ADC operates in low voltage, low-power, and small area. The delta-sigma (ΔΣ) ADC is very suitable for the application because they can achieve high accuracy for narrow band signals with few analog components and insensitivity to process and component variation. Typically, there are two kinds of ΔΣ ADCs. The first one is the discrete-time (DT) ΔΣ ADC and the other is the continuous-time (CT) ΔΣ ADC. The DT ΔΣ ADC also called the switched-capacitor (SC) ΔΣ ADC because of using switched capacitors. The CT ΔΣ ADC obtains lots of attentions lately. Because the requirement of integrator is relaxed, it does not need to process signals within a clock time. This results in further power reduction. In order to combine the advantages of the CT ΔΣ ADC system into low-power communication system, this research focuses on low power 20MS/s sample frequency 3-rd order zero optimization CT GM-C ΔΣ ADC for GSM communication system. The chip has been fabricated by TSMC 0.18-um CMOS process. The measured peak SNDR is 45dB, SNR is 47.8dB and the DR is 49dB. The resolution is 7.2 bits that is 4 bits lower than prediction in 200k HZ signal band.
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Kang, Ruei-Gen, und 康瑞根. „Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer“. Thesis, 2011. http://ndltd.ncl.edu.tw/handle/75534283238990354555.
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碩士國立中山大學
電機工程學系研究所
100
The thesis proposes a third order continuous-time sigma delta modulator used in GSM. We used a special 1.5bit quantizer, and to use its three different states to reach a differential feedback path. That can improve the resolution of our circuit. Oversampling and noise shaping are two keys of sigma delta modulator. In structure, the continuous-time features can reduce power consumption. The proposed sigma delta modulator uses TSMC 0.35 m CMOS process and its sampling frequency is 10.8MHz, bandwidth is200KHz and oversampling ratio is 32.
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Periasamy, Vijayaramalingam. „System Design of a Wide Bandwidth Continuous-Time Sigma-Delta Modulator“. Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7989.
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Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.
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Sun, Jin Tin, und 孫京庭. „A SECOND-ORDER THREE-BIT CONTINUOUS-TIME WIDEBAND DELTA-SIGMA MODULATOR“. Thesis, 2013. http://ndltd.ncl.edu.tw/handle/35499828160484656950.
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碩士大同大學
電機工程學系(所)
101
We present a three-bit continuous-time delta sigma modulator. The clock frequency is 320 MHz and the signal bandwidth is 10MHz, producing an oversampling rate of 16. In This work achieves second-order noise shaping by using Gm-C integrator. Eight comparators are used in the quantizer to achieve 3-bits resolution and two groups of DAC-current outputs feedback the signal form quantizater to Gm-C transconductor. This work requires a single 1.8-V supply, oversampling ratio 16, and bandwidth 10MHz. The Hspice simulation at -6.9dBFS intput shows a peak, signal-to-noise ratio of 49.21dB and the power consumption is 5mW.
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Chien, Cheng-Ming. „Design of a Wide Bandwidth Continuous-time Low-pass Sigma-delta Modulator“. Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10690.
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The emergence of bandwidth-intensive services has created a need for high speed and high resolution data converters. Towards this end, system level design of a continuous-time sigma-delta modulator achieving 11 bits resolution over 100 MHz signal bandwidth by using a feed-forward topology is presented. The system is first built in the Simulink environment in MATLAB. The building blocks in the loop filter are modeled with non-idealities, and specifications for these blocks are obtained by simulations. An operational transconductor amplifier (OTA) with 100 mS transconductance, 70 dB linearity, and 34.2 mW power dissipation is designed to be used in the loop filter. Simulation results indicate that the 5th order loop filter implemented in the feed-forward architecture in transistor level shows lower power consumption, 105 mW, compared to the loop filter implemented by feedback architecture, 152 mW.
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Lin, Yu-Xian, und 林育賢. „1.2V 0.18μm Continuous-Time Sigma-Delta Modulator Chip Design for WiMAX Application“. Thesis, 2008. http://ndltd.ncl.edu.tw/handle/91139847172044970696.
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碩士國立臺灣科技大學
電子工程系
96
With the flourishing of personal wireless communications development, to achieve high resolution with high bandwidth and reduce power consumption, complexity of handheld wireless devices is very important. The analog-to-digital (A/D) conversion plays an important role in the system signal quality. WiMAX wireless communication uses Orthogonal Frequency Division Multiplexing (OFDM) to transfer high data rates. The standard offers flexible for long distance and high bandwidth between 1.25MHz to 20MHz. With the progress of personal wireless communications based on the considerations of extending battery life achieving high resolution with several MHz bandwidth applications and reducing system complexity, which are especially important for portable wireless devices. The analog-to-digital (A/D) converters play an important role in the system. Over-sampling sigma-delta analogue-to-digital converters (ADCs), which provide a robust and economical solution for high-resolution and wideband analog-to-digital conversion. There are several wideband sigma-delta modulators using the structure of the discrete-time (DT) switched-capacitor (SC) but with high unity-gain bandwidth (UGB) requirements on the amplifiers in SC integrators, it has been difficult to extend the signal bandwidth implementations of sigma-delta modulators beyond a few MHz while maintaining high resolution. In low voltage design, the SC circuits need clock bootstrap and high switch resistance limits the signal dynamic range and limits the sampling frequency. Continuous-time (CT) sigma-delta modulator can be used to solve these problems. In this thesis, we design and implementation a low voltage, wideband, continuous-time sigma delta modulator for WiMAX application. The modulator mainly contains active-RC integrator, feedback DAC, and excess loop delay and 4-bits quantizer operation at 160MHz. The modulator dissipates 10.1 mW at 1.2 V supply voltage and is fabricated in the TSMC 0.18 um 1P6M CMOS technology. Measurement results show the modulator achieves 66.9 dB SNR, a peak 62.9 dB SNDR and 75dB dynamic range over a 10 MHz band at an over-sampling ratio of 8.
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Kuo, Ya-Wen, und 郭雅雯. „Chopper-Stabilized Continuous-time Sigma-Delta Modulator Design for Biomedical Sensing Applications“. Thesis, 2012. http://ndltd.ncl.edu.tw/handle/46177746956327848300.
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碩士國立中山大學
電機工程學系研究所
100
Continuous-time sigma-delta modulators play an important role in the development of biomedical sensors. It is suitable for monitoring of basic human vital functions (i.e., heartbeat and respiration). However, the physiological signal is very weak and it belongs to low-frequency range, the observed signals are strongly inter¬fered by the intrinsic flicker noise form CMOS transistors, which will cause a certain degree of difficulty in the identification. This thesis describes the implementation of loop filter using a differential chopper-stabilized configuration to reduce the influence of flicker noise on sigma-delta modulator within the signal bandwidth. The noise analysis of this sigma-delta modulator is calculated by the time-domain noise simulation. This method can take the noise factors into account when analyzing the overall performance. The proposed sigma-delta modulator is fabricated using TSMC 0.35μm 2P4M CMOS technology. The chip area is 1.403 x 1.4 mm2. With a sampling rate of 20.8 kHz, the modulator achieves 84.4 dB of the peak SNDR and ENOB is 13.7-bit within signal band¬width of 10Hz. It dissipates 3.46 mW under 3V supply voltage.
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Chang, Yu-Cheng, und 張育誠. „Design of Continuous-Time Delta-Sigma Modulator with Reduced Sensitivity to Clock Jitter“. Thesis, 2010. http://ndltd.ncl.edu.tw/handle/31268932230040042400.
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碩士國立臺灣大學
電子工程學研究所
99
For medium data rate applications, the continuous-time (CT) delta-sigma modulator is an appropriate candidate for implementing the ADC. However, the CT delta-sigma modulator is known to be sensitive to the excess loop delay (ELD) in the modulator and the clock jitter. Finite circuit response time causes latency in the modulator loop, which corrupts the modulator stability and degrades the system signal-to-noise ratio (SNR). On the issue of the clock jitter, the main culprit arises from the feedback DAC. The clock jitter modulates the DAC feedback waveforms and in effect adds noise to the input signal. Such noise content, just as the input signal, is not subject to the high-pass noise-shaping of the loop; thus, it directly results in SNR reduction. This work proposes a simple technique to reduce clock jitter effects that shapes the DAC feedback waveform as multi-step fixed-ON RZ. The sampling clock is processed by delay chain and digital logic to control the feedback DAC. By this way, this technique can reduce the clock jitter effect effectively but also archive low penalty of power consumption and delay element non-linearity. On the ELD issue, we use a digital circuit technique to improve the conventional ELD compensation technique that is necessary to a summing amplifier. To validate the proposed technique, a 3rd –order single-bit CT delta-sigma modulator is implemented in the TSMC 0.18-mm 1P6M COMS process. The proposed modulator achieves a 69-dB peak SNR with a 4-MHz bandwidth at a 400-MHz sampling rate and has an 71-dB dynamic range. The implemented modulator consumes 19mW from a 1.8-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless wideband systems.
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Lai, Yan-cheng, und 賴彥誠. „A Low-Voltage Continuous-Time Sigma-Delta Modulator Chip Design with DWA Technology“. Thesis, 2010. http://ndltd.ncl.edu.tw/handle/53597492085247881807.
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碩士國立臺灣科技大學
電子工程系
98
Recently, continuous-time (CT) ΣΔ modulators gain growing interest in wireless applications for their lower consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. Sigma-delta modulation techniques have been widely used in broadband and high accuracy analog/mixed-signal IC applications, such as analog-to-digital data converters (ADCs), digital-to-analog data converters (DACs), frequency synthesis, and power amplification. In the situation of low-voltage design, the signal dynamic range and sampling frequency are restricted by the high switch resistance in the switched-capacitor (SC) circuits. Due to the bandwidth limitation of the integrators, it is difficult to achieve wideband with high resolution. Hence, continuous-time ΣΔ modulator can be used to solve these problems. For a multibit ΣΔ modulator, the performance is directly related to the linearity of the internal multibit DAC in the feedback path. Various dynamic element matching (DEM) techniques have been proposed to improve the nonlinearity of the internal DAC. In the modulator, the data weighted averaging (DWA) algorithm is employed and provide first-order noise shaping of the DAC element mismatches. On the other hand, Capacitor tuning circuit is utilized to overcome loop coefficient shifts due to process variations. In digital signal processing, the design and analysis of the decimation filter is discussed including the comb filter and the finite impulse response (FIR) filter. In this thesis, we design and implement a low voltage, continuous-time sigma delta modulator for broadband application. The modulator mainly contains active-RC integrator, DWA circuit, feedback DAC circuit, and 4-bits quantizer operation at 160MHz. The modulator dissipates 19.8 mW at 1.2 V supply voltage and is fabricated in the TSMC 0.18 um 1P6M CMOS technology. Measurement results show the modulator achieves 51 dB SNR, a peak 48 dB SNDR and 54dB dynamic range over a 10 MHz band at an over-sampling ratio of 8.
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Yang, Ren-Chien, und 楊仁傑. „A Design of Low Power Continuous Time Delta-Sigma Modulator for Biosignal Applications“. Thesis, 2016. http://ndltd.ncl.edu.tw/handle/73507449787105287930.
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碩士國立中央大學
電機工程學系
104
With the coming of aging societies and the emergence of civilized illness, modern people increasingly focus on their body monitoring, so that various wearable devices of blood pressure, blood glucose and heart rate sensors have been launched. However, it usually be worn for long periods of time, so the lightweight and higher power efficiency are the key factors in considering. In general, biosignal detection system can be classified as sensor and the back-end processing circuit. The back-end processing circuit may be implemented by the integrated circuit (IC) to minimize the area. This thesis designs an analog to digital converter (ADC) for biosignal applications and implemented by continuous time delta-sigma modulator (CTDSM). The structure of the modulator is a third-order integrator and single bit quantizer. This ADC could process common biosignals and has enough resolutions to convert the analog signals to digital signals completely. In addition, the CTDSM also has the important property of implicit anti-aliasing filter (AAF), and it can relax the AAF front end and reduce power consumption in full system. Comparing to discrete time, the continuous time integrator can have lower power consumption to achieve the specification if both of them have the same type of integrator capacitor. In the end, the single bit quantizer can provide the best linearity and reduce the complexity of the circuit. The chip was implemented in 0.18 um CMOS technology and the core size is 0.8483 mm2. This work achieves 86 dB dynamic range and 12.6 bits ENOB in 10 kHz signal bandwidth with an oversampling ratio of 64. The power consumption is 140 uW under 1.8 V supply voltage.
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Chen, Zong-Yi, und 陳宗益. „A Continuous-Time Delta-Sigma Modulator Using Time-Domain Flash Quantizer and Modified DWA Implementation“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/97cv86.
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博士國立交通大學
電信工程研究所
104
Recently, the demands for analog-to-digital converters (ADCs) in wireless standards, such as LTE-A, have increased, which has pushed ADC bandwidth up to a few tens of megahertz (MHz) and resolution to more than 10 bits. In this dissertation, a power-efficient realization of a third-order continuous-time delta-sigma (CT-ΔΣ) modulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input is presented. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The CT-ΔΣ modulator uses the proposed TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in the TSMC CMOS 90 nm process. The proposed CT-ΔΣ modulator consumes 5.8 mW from 1.0 V supply voltage and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in FOM_W = 96.3 fJ/level and FOM_S = 161 dB.
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Hsueh, Chih-Pei, und 薛志培. „A Low-Power Gm-C Continuous Time Sigma Delta Modulator for Electrocardiogram Signal Sensor“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/242qcm.
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碩士國立中正大學
電機工程研究所
102
The top of the 10 leading causes of death in the world are Ischemic heart disease as well as Stroke and other cerebrovascular disease in recent years. In order to effectively treat related diseased, a portable wireless sensing system is required to monitor human biomedical signals, such as EEG or ECG. The sensing system should be low power and has the corresponding specifications to allow users for long-term use and carry conveniently. According to the required specifications of a wireless bio-signal acquisition system, this thesis proposes a novel sigma delta modulator structure, including a chopper, a low-pass sigma delta modulator and a digital filter with a chopper. The chopper can not only avoid the injection of low-frequency noise caused by devices but also increase the linearity of integrator by increasing input signal frequency in LPSDM. Moreover, the LPSDM is implemented in continuous time Gm-C architecture and the systematic design flow is introduced. The digital filter with a chopper is adopted to filter the quantization noise and to demodulate the input signal. The circuit is implemented in TSMC 0.18μm 1P6M CMOS process. The desired signal bandwidth is 200 Hz. The measured results with sampling frequency of 256 kHz reveal the SNR and SNDR are 52.03 dB and 47.49 dB, respectively. The dynamic range is 53.97 dB. The total power consumption is 5.223 uW under supply voltage of 1V.
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Ranjbar, Mohammad. „Power efficient continuous-time delta-sigma modulator architectures for wideband analog to digital conversion“. 2012. https://scholarworks.umass.edu/dissertations/AAI3518412.
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This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.
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Ming-Chi, Tsai. „The Design of A Second-Order Continuous-Time Delta-Sigma Modulator with A Single Amplifier“. 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0002-1007200613395800.
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50
Ming-Chung, Tsai. „A Third-Order Multi-Bit Continuous-Time Delta-Sigma Modulator with Incremental Data Weighted Averaging“. 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1401200714491500.
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