Auswahl der wissenschaftlichen Literatur zum Thema „Side-channel based disassembly“

Nucleocytoplasmic exchange in the cell occurs through the nuclear pore complexes (NPCs). NPCs are large multiprotein complexes with octagonal symmetry about their axis and imperfect mirror symmetry about a plane parallel with the nuclear envelop (NE). NPC fuses the inner and outer nuclear membranes and opens up а channel between nucleus and cytoplasm. NPC is built of nucleoporins. Each nucleoporin occurs in at least eight copies per NPC. Inside the NPC forms a permeability barrier by which NPC can ensure fast and selectable transport of molecules from one side of nuclear membrane to another. NPC architecture is based on hierarchical principle of organization. Nucleoporins are integrated into complexes that oligomerizes into bigger octomeric high-order structures. These structures are the main components of NPC. In the first part of this work the main attention is paid to NPC structure and nucleoporins’ properties. The second part is dedicated to mechanisms of NPC assembly and disassembly at different stages of cell cycle.

With the development of 5G and network technology, the usage of IoT devices has become popular. Because most of these IoT devices can be controlled by an adversary away from the administrator, several security issues such as firmware dumping can arise. Firmware dumping is the cornerstone or goal of many types of hardware hacking. Therefore, many IoT device manufacturers adopt some protection mechanisms such as the restriction of hardware debuggers. However, several recent studies have shown that the operating instructions of an IoT device can be recovered through the profiling-based side-channel analysis. The Side-Channel-Based Disassembler (SCBD) refers to software that recovers instructions of the device only from the side-channel signal. The SCBD is powerful enough to defeat many firmware protection mechanisms. In this paper, we show how an adversary can build an instruction (opcode)-level disassembler using the power consumption signal of commercial microcontrollers (MCUs) such as the 8-bit ATxmega128 and 32-bit STM32F0. To implement the SCBD, we elaborately constructed the instruction template considering the pipeline of the target MCUs through instruction sequence analysis. Furthermore, we preprocessed the side-channel signals using the Continuous Wavelet Transform (CWT) for noise reduction and Kullback-Leibler Divergence (KLD) for instruction feature extraction. Our experimental results show that the machine-learning-based instruction disassembling models can recover the operating instructions with an accuracy of about 91.9% and 98.6% for the ATxmega128 and STM32F0, respectively. Furthermore, we achieved an accuracy of 77% and 96.5% in a cross-board validation.

AbstractSide-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring instruments. In this work, however, we analyze the CPU instruction-level power side-channel leakage in an environment that lacks physical access or expensive measuring equipment. We show that instruction leakage is present even in a multitenant FPGA scenario, where the victim uses a soft-core CPU, and the adversary deploys on-chip voltage-fluctuation sensors. Unlike previous remote power side-channel attacks, which either require a considerable number of victim traces or attack large victim circuits such as machine learning accelerators, we take an evaluator’s point of view and provide an analysis of the instruction-level power side-channel leakage of a small open-source RISC-V soft processor core. To investigate whether the power side-channel traces leak secrets, we profile the victim device and implement various instruction opcode classifiers based on both classical machine learning algorithms used in disassembly attacks, and novel, deep learning approaches. We explore how parameters such as placement, trace averaging, profiling templates, and different FPGA families (including a cloud-scale FPGA) impact the classification accuracy. Despite the limited leakage of the soft-core CPU victim and a reduced accuracy and sampling rate of on-chip sensors, we show that in a worst-case scenario for the evaluator, i.e., an attacker breaching physical separation, we can identify the opcode of executed instructions with an average accuracy as high as 86.46%. Our analysis shows that determining the executed instruction type is not a classification bottleneck, while leakages between instructions of the same type can be challenging for deep learning models to distinguish. We also show that the instruction-level leakage is significantly reduced in a cloud-scale FPGA scenario with higher soft-core CPU frequencies. Nevertheless, our results show that even small circuits, such as soft-core CPUs, leak potentially exploitable information through on-chip power side channels, and users should deploy mitigation techniques against disassembly attacks to protect their proprietary code and data.

Le désassemblage par canaux auxiliaires (SCBD) est une famille d’attaques par canaux auxiliaires (SCA) dont le but est de retrouver de l’information à propos du code exécuté par un processeur via l’observation de canaux physiques comme la consommation électrique ou le rayonnement électromagnétique. Alors que les SCA classiques ciblent majoritairement des clés cryptographiques, le SCBD vise à récupérer du code assembleur difficile à extraire par d’autres moyens. Un exemple typique est le bootloader, qui est le premier programme exécuté au démarrage d’un dispositif électronique. La découverte d’une vulnérabilité dans un bootloader peut mener à la compromission totale du dispositif qui l’exécute. Le SCBD a été montré faisable sur de petits microcontrôleurs possédant une microarchitecture simple et un jeu d’instructions réduit. Cependant, l’essor des System-on-Chips (SoCs) complexes dans les smartphones, l’automobile ou l’avionique, rend nécessaire l’évaluation du risque posé par le SCBD sur ces plateformes. Par conséquent, dans cette thèse, nous nous intéressons à la faisabilité du SCBD sur les SoCs. Dans un premier temps, nous investiguons l’impact de la complexité microarchitecturale des SoCs sur les techniques de SCBD existantes. Nous montrons que ces dernières ont des difficultés à fournir des prédictions fiables sur des phénomènes de petite échelle, laissant une grande quantité d’incertitude à l’attaquant. Néanmoins, les phénomènes manipulant plus de ressources, comme les accès à la mémoire DRAM, peuvent être plus facilement distingués. Cette observation nous conduit à proposer trois nouvelles attaques hybrides, à l’intersection entre les attaques physiques et les attaques de microarchitecture. Dans un second temps, nous traitons l’incertitude inhérente au SCBD sur SoC en développant un outil générique et flexible. Cet outil permet de réaliser des attaques à base de modèles probabilistes (SASCA). Il se base sur un algorithme de propagation de croyances (BP) qui opère sur un modèle de graphe appelé factor graph. Cet outil nous permet d’opérer à des attaques sur les fonctions de hachage SHA-2 et SHA-3, ce qui, dans certains cas d’usage, mène à un moyen détourné de réaliser du SCBD. Enfin, nous introduisons un modèle probabiliste de désassemblage par canaux auxiliaires (SASCBD), qui permet d’agréger les prédictions imparfaites issues d’un SCBD classique. En plus d’exploiter efficacement la structure du jeu d’instruction, ce modèle permet d’incorporer de la connaissance bien plus riche, comme par exemple les propriétés du code assembleur à l’échelle d’un programme entier
Side-Channel Based Disassembly (SCBD) is a category of Side-Channel Analysis (SCA) that aims at recovering information on the code executed by a processor through the observation of physical side-channels such as power consumption or electromagnetic radiations. While traditional SCA often targets cryptographic keys, SCBD focuses on retrieving assembly code that can hardly be extracted via other means. A typical example is bootloader code, which is the first program executed by a processor at a device startup. Finding vulnerabilities in bootloader code could allow an attacker to compromise the entire device. SCBD has been shown feasible on microcontrollers with simple microachitectural complexity and small Instruction Sets Architecture (ISA). However, as System-on-Chips (SoCs) become ubiquitous in various systems such as smartphones, automotive or avionics, the threat posed by SCBD on these devices needs to be evaluated. In this thesis, we investigate the feasibility of SCBD on SoCs. We first study the impact of the microachitectural complexity of SoC’s processors on existing SCBD techniques. This brings us to the observation that the latter struggle to provide accurate predictions on small-scale phenomena, leaving a high amount of uncertainty from an attacker’s perspective. However, coarse-grained events, such as accesses to the main memory, can be accurately distinguished. We exploit this property to mount three new hybrid attacks, at the intersection of physical and microarchitectural attack. In the second part of this thesis, we deal with the uncertainty inherent to SCBD on SoCs by developing a generic and flexible Soft-Analytical Side-Channel Attack (SASCA) framework. This tool leverages factor graphs and the Belief Propagation (BP) algorithm to efficiently handle probabilistic information. This framework allows us to derive an attack on hash functions from the SHA-2 and SHA-3 families, which could lead to a twisted way to perform SCBD. Finally, we introduce the concept of Soft-Analytical Side-Channel Based Disassembly (SASCBD), which leverages the aforementioned framework to efficiently aggregate imperfect predictions from SCBD. This new approach efficiently exploits the structure of ISA and supports the addition of rich knowledge, such as behaviors at the scale of full programs