Thematische Bibliographien / Sequential digital circuits

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Auswahl der wissenschaftlichen Literatur zum Thema „Sequential digital circuits“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 1. Februar 2022

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Zeitschriftenartikel zum Thema "Sequential digital circuits"

Jagadeesan, Neeraja, B. Saman, M. Lingalugari, P. Gogna und F. Jain. „Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs“. International Journal of High Speed Electronics and Systems 24, Nr. 03n04 (September 2015): 1550011. http://dx.doi.org/10.1142/s0129156415500111.

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The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

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Hudli, Anand V., und Raghu V. Hudli. „Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits“. VLSI Design 2, Nr. 1 (01.01.1994): 69–80. http://dx.doi.org/10.1155/1994/94514.

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Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

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Nagar, Ayushi, und Rahul Shrivastava. „Review of Clocked Storage Elements in Digital Circuit Design“. International Journal on Recent and Innovation Trends in Computing and Communication 7, Nr. 5 (04.06.2019): 30–34. http://dx.doi.org/10.17762/ijritcc.v7i5.5308.

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Storage of digital circuit is "state" or memory. These are called sequential circuits. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. It is ponder four distinct assortments of these gadgets and their utilization in registers and register documents, which can be considered as one type of on– CPU memory. The traditional memory, called RAM, is ordinarily not on the CPU chip. Regular Slam and its assortments, including RAM, ROM, SRAM, Measure, and SDRAM. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. At first as a quick topology, the TSPC structure in like manner eats up less power and includes less areas than various systems. In flip-flop plan only a single transistor is being clocked by short heartbeat get ready which is known as True Single Phase Clocking (TSPC) flip-flop.

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Madec, Morgan, Elise Rosati und Christophe Lallement. „Feasibility and reliability of sequential logic with gene regulatory networks“. PLOS ONE 16, Nr. 3 (30.03.2021): e0249234. http://dx.doi.org/10.1371/journal.pone.0249234.

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Gene regulatory networks exhibiting Boolean behaviour, e.g. AND, OR or XOR, have been routinely designed for years. However, achieving more sophisticated functions, such as control or computation, usually requires sequential circuits or so-called state machines. For such a circuit, outputs depend both on inputs and the current state of the system. Although it is still possible to design such circuits by analogy with digital electronics, some particularities of biology make the task trickier. The impact of two of them, namely the stochasticity of biological processes and the inhomogeneity in the response of regulation mechanisms, are assessed in this paper. Numerical simulations performed in two use cases point out high risks of malfunctions even for designed GRNs functional from a theoretical point of view. Several solutions to improve reliability of such systems are also discussed.

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Dobai, Roland, und Elena Gramatová. „A novel automatic test pattern generator for asynchronous sequential digital circuits“. Microelectronics Journal 42, Nr. 3 (März 2011): 501–8. http://dx.doi.org/10.1016/j.mejo.2010.10.013.

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Tayal, Shubham, und Sunil Jadav. „Power-Delay Trade-Offs in Complementary Metal-Oxide Semiconductor Circuits Using Self and Optimum Bulk Control“. Sensor Letters 18, Nr. 3 (01.03.2020): 210–15. http://dx.doi.org/10.1166/sl.2020.4211.

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Power dissipation and delay are the challenging issues in the design of VLSI circuits. This manuscript explores joint effect of Self-Bias transistors (SBTs) and Optimum Bulk Bias Technique (OBBT) on CMOS circuits. Earlier investigations on SBTs shows decrease in power dissipation of combinational as well as sequential circuits. We extend the analysis by studying the effect of OBBT on the static and dynamic power of CMOS circuits with SBTs coupled amid the pull-up/down network and the supply bars. Extensive SPICE simulations have been carried out in 0.18 μm technology. Results demonstrate that, a 73% drop in power in case of combinational circuits and 43% in case of sequential circuits can be accomplished by engaging OBBT in digital circuits. Trade-off between power and delay is also been presented.

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Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas und Scott Morton. „Low-level logic fault testing ASIC simulation environment“. World Journal of Engineering 11, Nr. 3 (01.06.2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.

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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

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Barkalov, Oleksandr O., Larisa O. Titarenko, Oleksandr M. Golovin und Oleksandr V. Matvienko. „Optimization of a Composition Microprogram Control Unit with Elementary Circuits“. Control Systems and Computers, Nr. 2-3 (292-293) (Juli 2021): 40–51. http://dx.doi.org/10.15407/csc.2021.02.040.

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Introduction. The control unit coordinating interaction of all other blocks of a digital system is one of the central blocks and is a sequential circuit. As a rule, when synthesizing control unit circuits, the problem arises of reducing hardware costs. Methods for solving this problem depend on features of both the architecture of the control unit and the elemental basis. Purpose. The main goal of this work is to reduce hardware costs and power consumption of control units of digital systems by taking into account features of the element base of the control unit and rational organization of addressing microinstructions. FPGA (field-programmable logic array) microcircuits, widely used for the implementation of modern digital systems, were chosen as an elementary basis. Methods. Methods of set theory, synthesis of automata, and software modeling as well as the library of standard automata and FPGA Virtex-7 from Xilinx were used for assessment the effectiveness of solving the problem. Results. The paper proposes a method for optimizing the circuit of the microinstruction addressing unit based on splitting the set of outputs of elementary linear operator circuits, which is based on the idea of double coding of states. The proposed method, under certain conditions, makes it possible to reduce the number of levels in the microinstruction addressing circuit to two. Conclusion. Studies have shown that double coding of states can increase performance, reduce hardware costs (the number of LUTs and their interconnections) and power consumption in Mealy’s circuitry. Based on these results, it can be expected that, with the number of conditions exceeding the number of LUT inputs, the proposed approach will improve the characteristics of the composition microprogram control unit in comparison with the equivalent control unit U1.

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OBATA, K., K. TAKAGI und N. TAKAGI. „A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits“. IEICE Transactions on Electronics E90-C, Nr. 12 (01.12.2007): 2278–84. http://dx.doi.org/10.1093/ietele/e90-c.12.2278.

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Guimarães, Janaina Gonçalves, und Beatriz De Oliveira Câmara. „Digital Circuits and Systems based on Single-Electron Tunneling Technology“. Journal of Integrated Circuits and Systems 16, Nr. 1 (05.04.2021): 1–9. http://dx.doi.org/10.29292/jics.v16i1.475.

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In this work, digital circuits and systems based on single-electron tunneling technology will be presented and analyzed. A simple design methodology will be proposed using a programmable single-electron NAND/NOR gate as a building block. Aspects such as operating temperature, noise, and charge fluctuations will be discussed. SET devices can reach ultra-low power consumption and high frequencies during operation. Although there are already many digital SET circuits and systems previously proposed and studied, there are few works about design methodology for SETs. This study shows a proposal for designing combinational and sequential singleelectron circuits aiming at systems design. In the end, this work reinforces the use of single-electron technology as a possible large scale device in the future.

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Dissertationen zum Thema "Sequential digital circuits"

Hacker, Charles Hilton, und n/a. „WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design“. Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.

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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.

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Mudlapur, Anandshankar S. Agrawal Vishwani D. „Practically realizing random access scan“. Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/master's/MUDLAPUR_ANAND_14.pdf.

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Mohamed, Mohamed Hassan Wahba Ayman. „Diagnostic des erreurs de conception dans les circuits digitaux : le cas des erreurs simples“. Grenoble 1, 1997. http://www.theses.fr/1997GRE10086.

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Le diagnostic automatique des erreurs de conception est un probleme important dans le domaine de la cao. Bien que des outils automatises de synthese soient employes pour generer des structures de circuits correctes-par-construction, celles-ci sont souvent modifiees manuellement pour refleter des petites modifications faites sur la specification, ou pour ameliorer certaines caracteristiques critiques de la conception. Les outils de verification peuvent reveler l'existence d'erreurs, mais ils ne donnent aucune information sur leurs emplacements ou la facon de les corriger. Ces outils generent seulement quelques contres-exemples qui mettent en evidence l'erreur. Les concepteurs utilisent ces contre-exemples pour diagnostiquer manuellement leur conception. Le diagnostic manuel est un processus tres lent et tres couteux. Le temps de diagnostic peut etre egal, voire superieur, au temps de conception. Nous presentons dans cette these de nouveaux algorithmes pour la localisation et la correction automatique des erreurs simples de conception dans les circuits logiques sous l'hypothese d'une seule erreur. Les erreurs traitees ici sont : le remplacement d'un composant dans les circuits combinatoires et sequentiels, et une erreur de connexion dans les circuits combinatoires. Le modele d'une seule erreur exige une strategie de verification frequente, dans laquelle la conception est verifiee apres chaque modification, pour que la probabilite d'insertion de plus d'une erreur ne soit pas trop elevee. Notre approche consiste a simuler et analyser automatiquement le circuit sous l'application de vecteurs de test que nous produisons specialement pour accelerer le diagnostic. Nous avons realise deux logiciels prototypes bases sur ces algorithmes. Ccds est l'outil de diagnostic pour les circuits combinatoires, et scds est l'outil de diagnostic pour les circuits sequentiels. Ces outils sont actuellement integres dans l'environnement de preuves prevail#t#m.

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Lee, Chris Y. „Full Custom VLSI Design of On-Line Stability Checkers“. DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.

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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.

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Houška, David. „Poloautomatizovaný návrh vysoce výkonných číslicových obvodů s Xilinx FPGA“. Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2021. http://www.nusl.cz/ntk/nusl-442592.

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Tato diplomová práce se zabývá návrhem sekvenčních digitálních obvodů s ohledem na optimalizaci zpoždění. V práci je popsána problematika dvou technik, které jsou běžně používané při optimalizaci – stručně je popsána technika tzv. synchronizace registrů (angl. retiming), větší pozornost je však věnována technice tzv. zřetězení (angl. pipelining). V rámci praktické části byla vypracována forma abstrakce sekvenčních digitálních obvodů pomocí acyklických orientovaných grafů. Obvod je tak přenesen do roviny, ve které je jednodušší jej transformovat. Zároveň je představen nástroj pro polo-automatickou optimalizaci digitálních obvodů vyvíjených v prostředí Xilinx ISE Design Suite využitím techniky zřetězení.

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BUENO, REGIS C. „Detecção de contornos em imagens de padrões de escoamento bifásico com alta fração de vazio em experimentos de circulação natural com o uso de processamento inteligente“. reponame:Repositório Institucional do IPEN, 2016. http://repositorio.ipen.br:8080/xmlui/handle/123456789/26817.

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Submitted by Claudinei Pracidelli (cpracide@ipen.br) on 2016-11-11T13:03:47Z No. of bitstreams: 0
Made available in DSpace on 2016-11-11T13:03:47Z (GMT). No. of bitstreams: 0
Este trabalho desenvolveu um novo método para a detecção de contornos em imagens digitais que apresentam objetos de interesse muito próximos e que contêm complexidades associadas ao fundo da imagem como variação abrupta de intensidade e oscilação de iluminação. O método desenvolvido utiliza lógicafuzzy e desvio padrão da declividade (Desvio padrão da declividade fuzzy - FuzDec) para o processamento de imagens e detecção de contorno. A detecção de contornos é uma tarefa importante para estimar características de escoamento bifásico através da segmentação da imagem das bolhas para obtenção de parâmetros como a fração de vazio e diâmetro de bolhas. FuzDec foi aplicado em imagens de instabilidades de circulação natural adquiridas experimentalmente. A aquisição das imagens foi feita utilizando o Circuito de Circulação Natural (CCN) do Instituto de Pesquisas Energéticas e Nucleares (IPEN). Este circuito é completamente constituído de tubos de vidro, o que permite a visualização e imageamento do escoamento monofásico e bifásico nos ciclos de circulação natural sob baixa pressão.Os resultados mostraram que o detector proposto conseguiu melhorar a identificação do contorno eficientemente em comparação aos detectores de contorno clássicos, sem a necessidade de fazer uso de algoritmos de suavização e sem intervenção humana.
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IPEN/T
Instituto de Pesquisas Energeticas e Nucleares - IPEN-CNEN/SP

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Van, den Berg Allan Edward. „Hardware evolution of a digital circuit using a custom VLSI architecture“. Thesis, Nelson Mandela Metropolitan University, 2013. http://hdl.handle.net/10948/d1020984.

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This research investigates three solutions to overcoming portability and scalability concerns in the Evolutionary Hardware (EHW) field. Firstly, the study explores if the V-FPGA—a new, portable Virtual-Reconfigurable-Circuit architecture—is a practical and viable evolution platform. Secondly, the research looks into two possible ways of making EHW systems more scalable: by optimising the system’s genetic algorithm; and by decomposing the solution circuit into smaller, evolvable sub-circuits or modules. GA optimisation is done is by: omitting a canonical GA’s crossover operator (i.e. by using an algorithm); applying evolution constraints; and optimising the fitness function. The circuit decomposition is done in order to demonstrate modular evolution. Three two-bit multiplier circuits and two sub-circuits of a simple, but real-world control circuit are evolved. The results show that the evolved multiplier circuits, when compared to a conventional multiplier, are either equal or more efficient. All the evolved circuits improve two of the four critical paths, and all are unique. Thus, it is experimentally shown that the V-FPGA is a viable hardware-platform on which hardware evolution can be implemented; and how hardware evolution is able to synthesise novel, optimised versions of conventional circuits. By comparing the and canonical GAs, the results verify that optimised GAs can find solutions quicker, and with fewer attempts. Part of the optimisation also includes a comprehensive critical-path analysis, where the findings show that the identification of dependent critical paths is vital in enhancing a GA’s efficiency. Finally, by demonstrating the modular evolution of a finite-state machine’s control circuit, it is found that although the control circuit as a whole makes use of more than double the available hardware resources on the V-FPGA and is therefore not evolvable, the evolution of each state’s sub-circuit is possible. Thus, modular evolution is shown to be a successful tool when dealing with scalability.

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Araujo, Marcos Paulo Mello. „Síntese evolucionária de circuitos sequenciais inspirada nos princípios da computação quântica“. Universidade do Estado do Rio de Janeiro, 2008. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=7448.

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Esta dissertação investiga a aplicação dos algoritmos evolucionários inspirados na computação quântica na síntese de circuitos sequenciais. Os sistemas digitais sequenciais representam uma classe de circuitos que é capaz de executar operações em uma determinada sequência. Nos circuitos sequenciais, os valores dos sinais de saída dependem não só dos valores dos sinais de entrada como também do estado atual do sistema. Os requisitos cada vez mais exigentes quanto à funcionalidade e ao desempenho dos sistemas digitais exigem projetos cada vez mais eficientes. O projeto destes circuitos, quando executado de forma manual, se tornou demorado e, com isso, a importância das ferramentas para a síntese automática de circuitos cresceu rapidamente. Estas ferramentas conhecidas como ECAD (Electronic Computer-Aided Design) são programas de computador normalmente baseados em heurísticas. Recentemente, os algoritmos evolucionários também começaram a ser utilizados como base para as ferramentas ECAD. Estas aplicações são referenciadas na literatura como eletrônica evolucionária. Os algoritmos mais comumente utilizados na eletrônica evolucionária são os algoritmos genéticos e a programação genética. Este trabalho apresenta um estudo da aplicação dos algoritmos evolucionários inspirados na computação quântica como uma ferramenta para a síntese automática de circuitos sequenciais. Esta classe de algoritmos utiliza os princípios da computação quântica para melhorar o desempenho dos algoritmos evolucionários. Tradicionalmente, o projeto dos circuitos sequenciais é dividido em cinco etapas principais: (i) Especificação da máquina de estados; (ii) Redução de estados; (iii) Atribuição de estados; (iv) Síntese da lógica de controle e (v) Implementação da máquina de estados. O Algoritmo Evolucionário Inspirado na Computação Quântica (AEICQ) proposto neste trabalho é utilizado na etapa de atribuição de estados. A escolha de uma atribuição de estados ótima é tratada na literatura como um problema ainda sem solução. A atribuição de estados escolhida para uma determinada máquina de estados tem um impacto direto na complexidade da sua lógica de controle. Os resultados mostram que as atribuições de estados obtidas pelo AEICQ de fato conduzem à implementação de circuitos de menor complexidade quando comparados com os circuitos gerados a partir de atribuições obtidas por outros métodos. O AEICQ e utilizado também na etapa de síntese da lógica de controle das máquinas de estados. Os circuitos evoluídos pelo AEICQ são otimizados segundo a área ocupada e o atraso de propagação. Estes circuitos são compatíveis com os circuitos obtidos por outros métodos e em alguns casos até mesmo superior em termos de área e de desempenho, sugerindo que existe um potencial de aplicação desta classe de algoritmos no projeto de circuitos eletrônicos.
This thesis investigates the application of quantum inspired evolutionary algorithms in the synthesis of sequential circuits. Sequential digital systems represent a class of circuit that is able to execute operations in a particular sequence. In sequential circuits, the values of output signals not only depend on the values of input signals but also on the current state of the system. The increasingly high requirements regarding the functionality and performance of digital systems demand more efficient designs. The design of these circuits, when implemented manually, became slow and thus the importance of tools for automatic synthesis of circuits grew rapidly. These tools known as ECAD (Electronic Computer-Aided Design) are computer programs usually based on heuristics. Recently, evolutionary algorithms also began to be used as a basis in ECAD tools developing. These applications are referenced in literature as evolutionary electronics. The algorithms most commonly used in evolutionary electronics are genetic algorithms and genetic programming. This work presents a study of the application of quantum inspired evolutionary algorithms as a tool for automatic synthesis of sequential circuits. This class of algorithms uses the principles of quantum computing to improve the performance of evolutionary algorithms. Traditionally, the design of sequential circuits is divided into five main steps: (i) State machine specification; (ii) Reduction of states; (iii) State assignment; (iv) Control logic synthesis and (v) Implementation of the state machine. The proposed algorithm AEICQ is used in the state assignment design step. The choice of an optimal state assignment is treated in the literature as an issue still unresolved. The state assignment chosen for a particular state machine has a direct impact on the complexity of its control logic. The results show that the state assignment obtained by AEICQ in fact leads to the implementation of circuits of less complexity when compared with the ones generated from assignments obtained by other methods. The AEICQ is also used in the control logic synthesis of the state machine. The circuits evolved by AEICQ are optimized according to the area occupied and the propagation delay. These circuits are compatible with the circuits obtained by other methods and in some cases even higher in terms of area and performance, suggesting that there is a potential for application of this class of algorithms in the design of electronic circuits.

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Jiang, Yiau-Shiuan, und 江耀玄. „Oscillation Ring Test for Digital Sequential Circuits“. Thesis, 2001. http://ndltd.ncl.edu.tw/handle/81276650099454760745.

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碩士
國立交通大學
電子工程系
89
In this thesis, we propose a novel method for testing using theory of oscillation ring testing. The oscillation ring detects stuck-at fault of the sequential circuit, in addition, it detects the delay fault. We propose two methods for generating the test patterns. The first one method is to create oscillation ring test in the circuit for generating test patterns. The second method is using the state transition table to observe the output of the oscillation ring. For the second method an algorithm has been designed to generate efficient test patterns. Beside, we also alleviate the difficult of test patterns generation by proposing an oscillation ring driven sequential circuit synthesize method which reassigns the state variables to provide an efficient approach for oscillation ring based test pattern generations. Consequently, the testability is great enhanced after the transform of state table. These two methods have been simulated, and got excellent results.

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Chen, Ti-Wen, und 陳文. „Randomization on Testing in Digital Sequential Logic Circuits“. Thesis, 1999. http://ndltd.ncl.edu.tw/handle/54400850713916137407.

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碩士
中華大學
電機工程學系碩士班
87
Randomization on testing in sequential logic circuits is more complicated and difficult than that on combinational logic circuits. In this thesis, it aims to adopt the method of Markov chain to analyze the random testability for detecting a fault in circuit. By the analysis results, the random testability of a circuit under test may be seen are a figure of merit and it can be used for generating a set of random test patterns to reduce the time of pattern generation.

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Bücher zum Thema "Sequential digital circuits"

Vasyukevich, Vadim. Asynchronous Operators of Sequential Logic: Venjunction & Sequention: Digital Circuit Analysis and Design. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.

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Digital logic and state machine design. 3. Aufl. Ft. Worth: Saunders College Pub., 1995.

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Digital logic and state machine design. 2. Aufl. Philadelphia: Saunders College Pub., 1990.

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Comer, David J. Digital logic and state machine design. 3. Aufl. New York: Oxford University Press, 1995.

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Comer, David J. Digital logic and state machine design. 2. Aufl. Philadelphia, Pa: Saunders College Pub, 1990.

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Bronstein, Alexandre. String-functional semantics for formal verification of synchronous circuits. Stanford, Calif: Dept. of Computer Science, Stanford University, 1988.

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Steven, Nowick, Hrsg. Sequential optimization of asynchronous and synchronous finite-state machines: Algorithms and tools. Boston: Kluwer Academic Publishers, 2001.

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Fuhrer, Robert M. Sequential optimization of asynchronous and synchronous finite-state machines: Algorithms and tools. Boston: Kluwer Academic Publishers, 2001.

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Lee, Sunggu. Advanced digital logic design: Using Verilog, state machines, and synthesis for FPGAs. Toronto, Ont: Thomson, 2006.

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Ndjountche, Tertulien. Digital Electronics 2: Sequential and Arithmetic Logic Circuits. Wiley & Sons, Incorporated, John, 2016.

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Buchteile zum Thema "Sequential digital circuits"

Deschamps, Jean-Pierre, Elena Valderrama und Lluis Terés. „Sequential Circuits“. In Digital Systems, 79–133. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-41198-9_4.

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Anis, Mohab, und Mohamed Elmasry. „MTCMOS Sequential Circuits“. In Multi-Threshold CMOS Digital Circuits, 135–61. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_5.

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Wirth, Niklaus. „Synchronous, Sequential Circuits“. In Digital Circuit Design for Computer Science Students, 49–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/978-3-642-57780-2_4.

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Stonham, T. J. „Design of Sequential Logic Circuits“. In Digital Logic Techniques, 82–114. Boston, MA: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4615-6856-8_5.

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Sachdev, Manoj. „Testing Defects in Sequential Circuits“. In Defect Oriented Testing for CMOS Analog and Digital Circuits, 95–132. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4926-7_4.

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El-Zawawy, Mohamed A. „Novel Designs for Memory Checkers Using Semantics and Digital Sequential Circuits“. In Computational Science and Its Applications -- ICCSA 2015, 597–611. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-21410-8_46.

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Crowe, John, und Barrie Hayes-Gill. „Synchronous sequential circuits“. In Introduction to Digital Electronics, 179–90. Elsevier, 1998. http://dx.doi.org/10.1016/b978-034064570-3/50010-1.

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„Asynchronous sequential circuits“. In Digital Design Using VHDL, 551–65. Cambridge University Press, 2015. http://dx.doi.org/10.1017/cbo9781316162651.027.

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„Asynchronous Sequential Circuits“. In Foundations of Digital Logic Design, 329–431. WORLD SCIENTIFIC, 1998. http://dx.doi.org/10.1142/9789812817044_0006.

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„Synchronous Sequential Circuits“. In Foundations of Digital Logic Design, 433–538. WORLD SCIENTIFIC, 1998. http://dx.doi.org/10.1142/9789812817044_0007.

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Konferenzberichte zum Thema "Sequential digital circuits"

Dobai, Roland, und Elena Gramatova. „Deductive Fault Simulation for Asynchronous Sequential Circuits“. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD). IEEE, 2009. http://dx.doi.org/10.1109/dsd.2009.129.

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Subbaraman, Shaila, und P. S. Nandgawe. „Intellectual Property Protection of Sequential Circuits Using Digital Watermarking“. In First International Conference on Industrial and Information Systems. IEEE, 2006. http://dx.doi.org/10.1109/iciis.2006.365790.

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Raik, Jaan, Raimund Ubar, Anna Krivenko und Margus Kruus. „Hierarchical Identification of Untestable Faults in Sequential Circuits“. In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341539.

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Kaur, Navneet, Varun Nehru und Deep Sehgal. „Dynamic Logic Circuits: Combinational and Sequential Design for Digital ICs“. In 2018 International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET). IEEE, 2018. http://dx.doi.org/10.1109/iccsdet.2018.8821078.

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He, Yajuan, Ziji Zhang, Xiong Zhou und Qiang Li. „Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits“. In ICETT 2021: 2021 7th International Conference on Education and Training Technologies. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3463531.3463541.

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Subash, T. D., T. Gnanasekaran, A. Karpagaselvi und R. Kavitha. „Low power consumption of sequential circuit of digital ICS“. In 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2014. http://dx.doi.org/10.1109/icdcsyst.2014.6926184.

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Skobtsov, Yu A., und V. Yu Skobtsov. „Evolutionary approach to test generation of sequential digital circuits with multiple observation time strategy“. In Test Symposium (EWDTS). IEEE, 2010. http://dx.doi.org/10.1109/ewdts.2010.5742104.

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Fazeli, Mahdi, Seyed Ghassem Miremadi, Hossein Asadi und Mehdi Baradaran Tahoori. „A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits“. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD). IEEE, 2010. http://dx.doi.org/10.1109/dsd.2010.74.

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Yu Ben, Laurent El Ghaoui, Kameshwar Poolla und Costas J. Spanos. „Yield-constrained digital circuit sizing via sequential geometric programming“. In 2010 11th International Symposium on Quality of Electronic Design (ISQED). IEEE, 2010. http://dx.doi.org/10.1109/isqed.2010.5450391.

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Parashar, K. N., und N. Chandrachoodan. „A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation“. In 2007 International Conference on Field Programmable Logic and Applications. IEEE, 2007. http://dx.doi.org/10.1109/fpl.2007.4380770.

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