Dissertationen zum Thema „Semiconductor failure analysis“

Les travaux de recherche présentés dans ce manuscrit de thèse ont pour principal objectif d’aider à comprendre les différents mécanismes et phénomènes qui interviennent lors de l’interaction d’un laser avec un semiconducteur dans une analyse de circuits intégrés submicroniques. Le but étant de maitriser et améliorer les techniques d’analyse par laser en mode sonde. La miniaturisation et la densification des composants électroniques fait que les techniques d’analyse par laser atteignent leurs limites. Connaitre l’impact des différents paramètres physiques, optiques et électriques sur une analyse sonde est un facteur clé pour pouvoir améliorer la compréhension des signaux sonde mesuré. Ces travaux montrent également l’effet non négligeable de la température sur les techniques d’analyse par laser en mode sonde
The main objective of the presented research work in this PhD thesis is to help to understand the different mechanisms and phenomena involved in the interaction of a laser with a semiconductor in the analysis of a submicron integrated circuit. The aim is to master and improve the Electro Optical Probing techniques. Miniaturization and densification of electronic components lead the failure analysis techniques using Laser to their limits. Knowing the impact of different physical, optical and electrical parameters on a probing analysis is a key to improve the understanding the measured EOP signals. These studies also show the significant effect of temperature on the EOP techniques

Hmotnostná spektrometria sekundárnych iónov s analýzou doby letu (TOF-SIMS) patrí vďaka vysokej citlivosti na prvkové zloženie medzi významné metódy analýzy pevných povrchov. Táto práca demonštruje možnosti TOF-SIMS v troch odlišných oblastiach výskumu. Prvá časť práce sa zaoberá lokalizáciou defektov vysokonapäťových polovodičových súčiastok, ktorá je nevyhnutná k ich ďalšiemu skúmaniu metódou TOF-SIMS. Bola navrhnutá experimentálna zostava s riadiacim softvérom umožňujúca automatizované meranie záverného prúdu v rôznych miestach polovodičový súčiastok. Druhá časť práce sa zaoberá kvantifikáciou koncentrácie Mg dopantov v rôznych hĺbkach vzoriek AlGaN. Kvantifikácia je založená na metóde RSF a umožňuje charakterizáciu AlGaN heteroštruktúr určených na výrobu tranzistorov s vysokou elektrónovou mobilitou (HEMT) alebo na výrobu rôznych optoelektronických zariadení. Sada 12 AlGaN kalibračných vzoriek dopovaných Mg, určených na kvantifikáciu hĺbkových profilov, bola pripravená metódou iónovej implantácie. Posledná časť práce demonštruje možnosti metódy TOF-SIMS vo výskume heterogénnej katalýzy. Hlavným objektom nášho výskumu je dynamika oxidácie CO na oxid uhličitý na polykryštalickom povrchu platiny za tlakov vysokého vákua. V tejto práci prezentujem prvé TOF-SIMS pozorovanie časopriestorových vzorov v reálnom čase, ktoré vznikajú v dôsledku rôzneho pokrytia povrchu Pt reaktantmi. Výsledky TOF-SIMS experimentu boli porovnané s výsledkami podobného experiment v rastrovacom elektrónovom mikroskope (SEM).

Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.
Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.

QC 20170524

A bord des véhicules électriques (VE) et Hybrides (VEH), les fonctions de tractions sont assurées par des convertisseurs électroniques de puissances. Ces derniers sont constitués de module de puissance (IGBTs ou MOSFETs). Au cours de leur fonctionnement, ces modules sont parfois soumis à de fortes contraintes électriques et thermiques qui amènent à une défaillance ou même à une destruction. Le premier objectif sera de réaliser un banc expérimentale permettant d'étudier le vieillissement des modules IGBTs en régîmes extrêmes de fonctionnement (mode de court-circuit). Ainsi, nous évaluerons les différents indicateurs de vieillissements permettant de prédire la défaillance du composant. Il sera question aussi de suivre le vieillissement ou une dégradation initié sur les composants IGBTs par thermographie infrarouge. Le second objectif sera de modéliser et simuler par éléments finis différentes structures d'IGBTs, afin de valider les modèles en fonctionnement statique et dynamique. L'avantage de l'approche multicellulaire par rapport à l'approche unicellulaire sera mis en avant.

碩士
國立清華大學
工業工程研究所
86
For semiconductor manufacturing industries, high manufacturing costs are coupled with numerous, complex manufacturing processes and strict manufacturing environment. Since any yield loss will induce huge increase of manufacturing costs, the semiconductor manufacturing companies are always searching for methods to enhance the yield of their products. Besides in-line process control, off-line failure analysis is another important approach to improve the yield of semiconductor products. 　In this research, an engineering-data based semiconductor failure analysis system is presented. The goal of this system is to clarify the relationship between circuit probe yield and defects, via the comparison between Bin map and various defect maps gathered from in-line inspection, such that the contribution of various manufacturing processes to the failure of chips can be traced. 　Through the experiments conducted in a semiconductor company, it can be proven that the failrue analysis system developed in this research possesses the capability of finding our the root cause of yidle loss. By the assistance of this system, engineers can more effectively find out process problems to achieve the goal of yield improvement and enhancement.

碩士
國立成功大學
電機工程學系專班
98
The study of failure analysis (FA) is rare internal. Thus the purpose of this thesis is to setup a complete FA flow and to study the challenges of couple metal oxide semiconductor (CMOS) FA in nano process. First to study each technique of failure site localization, advantages, disadvantages and limitations and illustrated by real cases. The techniques of failure site localization are liquid crystal microscopy, photon emission microscopy, optical beam induced resistance change and static random access memory of bitmap programming. Because of the physical limitation of nano process integrated circuit (IC), failure site localization becomes more and more difficult. To study a new technique which is FA of CMOS logic IC by testing pattern, called diagnosis. Next, simply introduces several methods of FA of sample preparation as top lapping, focused Ion beam (FIB) circuit repair, wet etching and dry etching and discusses the challenges of FA in nano process. Then simply introduces several methods of sample inspection analysis in physically as optical microscope, scanning electron microscope, FIB X-section, transmission electron microscope, scanning transmission electron microscope and energy dispersive spectroscopy and in electrically as scanning capacitor microscopy and passive voltage contrast. Finally, two new techniques and applications of sample inspection analysis in electrically in order to analysis more accurate in nano process, one is conductive atom force microscopy, to study CMOS gate oxide defect localization and inter connection high resistance detection. Another is nano-probing technique, to study two real cases of applications of source to drain dislocation detection and discusses their mechanisms.

碩士
大葉大學
工業工程與科技管理學系
98
The process of semiconductor is considered complex as a large of manpower and cost are required. In this case, how to effectively control and advance the yield of wafers that most important issue at present. Previous studies were rather insufficient on the yield of wafer process as they focused on the issues of equipment maintenance and human dispatch. This study aims to find the key factors of wafer yield failure by failure mode and effects analysis (FMEA). Traditional calculations in FMEA are existed in many problems depended on the experiences of engineers as well as specific quantizing values were insufficient that resulted in significant difference between research results and actual processes. Many experts proposed revisions for the calculations in failure mode; however, the probabilities of occurrence were not evaluated with practical values. This concept of Fuzzy Theory with quantizing values in actual processes with process modifications and improvements. Research findings on traditional calculation sequencing of risk priority number (RPN), proposed in the fourth revision of FMEA, failed to definitely identify improvement-priority sequence after the case studies. This study re-calculates and further sorts by replacing severity and in-detection in failure mode with Fuzzy linguistic variables and obtaining occurrence from the yield transformation in wafer process, In this case, the research results are more complete and are able to accurately distinguish the priority sequencing of key failures.

碩士
國立交通大學
工學院半導體材料與製程設備學程
102
This study was focused on failure analysis for custom product with end terminal production return. Because there is only one or two sample from board level return, the priority of this case event is emergent for tracing all the effecting reason. We propose an efficient way to short the analysis time and develop a failure analysis scheme to fit custom requirement. In this thesis, we report the combination of electrical probing and photo emission microscope techniques. As to the surface mount technology (SMT) response, this system was demonstrated the abnormal characteristics. We preliminarily judge as the possible failure site. If the failed effect is resulted from IC, this sample should be further failure analysis. By change different test pattern and operating voltage, this condition could be determined as the the failure mode. From the different waveform and co-observed phenomenon, we can approach the suspected area in the chip. This sample is further inspected with emission microscope to find abnormal hot spot. If there is abnormal hot spot, it should be further physical failure analysis. According to the hot spot, this sample should be delayer and check the suspected area by SEM. The final deteriorated reason of this failure chip is determined from our proposed scheme for failure analysis.

碩士
國立成功大學
電機工程學系碩博士班
94
The industry of integrated circuit (IC) semiconductor started at the middle of twenty century and grows fast at the second half century. The capacity of the IC industry exceeds the consumption of the market at the end of twenty century. The cycle time of a product getting shorter compresses the profile. Especially the vertical division of semiconductor industry decreases the barrier of entry. The time-to-market becomes critical to the profit. The design and manufacturing period with computer-aided automation are well controlled and very precisely, but yield rate of the first cut always get low yield. This violently extends the time-to-market, reduces profit or even losses money. The low yield may comes from design, manufacturing or interaction of both and almost induced by high resistance or leakage circuit. Failure analysis to identify the cause of high resistance and leakage plays a significant role to improve the yield. 　　The failure analysis technologies, liquid crystal microscopy, fluorescent micro-thermal microscopy, emission microscopy, thermal beam induced current variation, and passive voltage contrast are used to locate the failure site. Several real cases are demonstrated in this thesis to discuss the possible failure mechanism and find out the defect, in order to compare these failure analysis technologies.

abstract: Integrated oxide/semiconductor heterostructures have attracted intense interest for device applications which require sharp interfaces and controlled defects. The research of this dissertation has focused on the characterization of perovskite oxide/oxide and oxide/semiconductor heterostructures, and the analysis of interfaces and defect structures, using scanning transmission electrom microscopy (STEM) and related techniques. The SrTiO3/Si system was initially studied to develop a basic understanding of the integration of perovskite oxides with semiconductors, and successful integration with abrupt interfaces was demonstrated. Defect analysis showed no misfit dislocations but only anti-phase boundaries (APBs) in the SrTiO3 (STO) films. Similar defects were later observed in other perovskite oxide heterostructures. Ferroelectric BaTiO3 (BTO) thin films deposited directly onto STO substrates, or STO buffer layers with Ge substrates, were grown by molecular beam epitaxy (MBE) in order to control the polarization orientation for field-effect transistors (FETs). STEM imaging and elemental mapping by electron energy-loss spectroscopy (EELS) showed structurally and chemically abrupt interfaces, and the BTO films retained the c-axis-oriented tetragonal structure for both BTO/STO and BTO/STO/Ge heterostructures. The polarization displacement in the BTO films of TiN/BTO/STO heterostructures was investigated. The Ti4+ atomic column displacements and lattice parameters were measured directly using HAADF images. A polarization gradient, which switched from upwards to downwards, was observed in the BTO thin film, and evidence was found for positively-charged oxygen vacancies. Heterostructures grown on Ge substrates by atomic layer deposition (ALD) were characterized and compared with MBE-grown samples. A two-step process was needed to overcome interlayer reaction at the beginning of ALD growth. A-site-rich oxide films with thicknesses of at least 2-nm had to be deposited and then crystallized before initiating deposition of the following perovskite oxide layer in order to suppress the formation of amorphous oxide layers on the Ge surface. BTO/STO/Ge, BTO/Ge, SrHfTiO3/Ge and SrZrO3/Ge thin films with excellent crystallinity were grown using this process. Metal-insulator-metal (MIM) heterostructures were fabricated as ferroelectric capacitors and then electrically stressed to the point of breakdown to correlate structural changes with electrical and physical properties. BaTiO3 on Nb:STO was patterned with different top metal electrodes by focused-ion-beam milling, Au/Ni liftoff, and an isolation-defined approach.
Dissertation/Thesis
Doctoral Dissertation Materials Science and Engineering 2018

碩士
中華大學
工業工程與管理研究所
88
Abstract A Process Failure Mode and Effects Analysis (PFMEA) is a kind of defense process to assure product quality. Using PFMEA effectively can identify potential or known failure modes and provide Risk Priority Number (RPN) or relative information, which gives decision-maker and operator to make appropriate decision or operation. In this study, fuzzy logic FMEA is introduced to semiconductor assembly and testing industry. By analyzing the machine module and the manufacture procedure and making all departments cooperate with each other, all failure modes can be found. Therefore, automated FMEA for whole process has its convenience and importance. In addition, each department will be connected to the database of FMEA via the computer network to provide relativity and importance information. In a traditional analysis, the assessment of Risk Priority Number is based on the severity, occurrence, and detection of an item failure. The ranking of these parameters is ranging from 1 to 10. RPN is a product of the severity, occurrence, and detection. Owing to these parameters representing uncertain fuzzy set, fuzzy logic is used to deal with qualitative and quantitative data via membership functions and relative rules.

碩士
國立交通大學
工學院產業安全與防災學程
107
In the semiconductor industry, the use of nitrogen is indispensable. Whether using cylinders or tank trucks or underground pipelines, they provide users with high cleanliness and safety considerations, especially using for production that pays particular attention to the purity of nitrogen. To achieve high purity and cleanliness, the nitrogen must be purified to meet the process requirements in factory. Purification equipment is expensive, and if a high concentration of impurities enters the purification equipment during the purification process, the purification equipment will be burnt due to high temperature reaction. In addition to the safety of the entire plant, the post-disaster recovery will be a long-term work. In this paper, using the FMEA (Failure Mode and Effects Analysis) method to list all the risk nodes, and found that there are high-risk nodes for the continuous supply of nitrogen, such as adsorption material saturation, excessive temperature during adsorption, and nitrogen content excessive impurity, Identify the prevention methods for these high-risk nodes, so that the design concept of the purification equipment is more in line with safety, and the risk of the purification equipment in the factory can be minimized to avoid disasters.

碩士
國立交通大學
工學院半導體材料與製程設備學程
101
The rapid increase in the demand of 3C consumer products requires a fast supply of a large quantity of flat panel displays of different dimensions. Nowadays, the liquid crystal display (LCD) is the standard display panel for various kinds of television sets, mobile phones and tablet computers. These LCD displays are controlled by integrated circuit (IC) drivers that are fabricated using the high-voltage (HV) metal-oxide-semiconductor (MOS) field-effect transistor (FET) process. The stability of the threshold voltage (VT) of HV-MOSFET drivers greatly affect the performance of the LCD panel displays. From the wafer acceptance test (WAT), two types of VT instability (or drift) are found to occur to the HV-MOSFET drivers. One type is a high VT in the P-type MOS (PMOS) but a low VT in the N-type MOS (NMOS); the other is a high VT in NMOS but a low VT in PMOS. In the thesis, we study the failure cause of the VT drift of the HV-MOSFET drivers. We used WAT analysis, in conjunction with various material analysis techniques, to study the dependence of the VT drift on the parameters of the fabrication processes of the HV-MOSFET drivers. From the study, we found that a thin initial oxide layer before the ion implantation (IMP) will result in a serious VT drift. The formation of the thin oxide layer may occur due to following improper process conditions: the time of IMP drive-in, the time for the pre-IMP wet clean, and the waiting time between the pre-IMP wet-clean and the IMP process.This study found that the main factor causing the VT drift of the HV-MOSFET driver was the wafer location in the furnace for the deposition of the sacrificial oxide and the pad oxide for the shallow trench isolation process. The placement of wafers on the top section of the furnace may result in an opposite VT drift to that on the bottom section. This is due to the non-uniform distribution of the oxygen flow in the furnace. The problem of the VT drift of the HV-MOSFET drivers was eliminated by the modification of the furnace deposition conditions of the pad oxide in the shallow trench isolation process.

碩士
臺灣大學
電子工程學研究所
96
Atomic Force Microscopy (AFM) based method of this thesis was indicated and established for its possible applications in semiconductor investigation. Based on three successful published papers (ISTFA: International Symposium for Testing and Failure Analysis), the AFM system is clear and accurate to identify the semiconductor failure root cause and summarize these results. Multiple scanning probing microscopy methods were maturely developed and accomplished for advanced nanometer process investigation. E.g. Magnetic Force Microscopy, Scanning Capacitance Microscopy, Current-Mapping Conductive-AFM applications would be introduced and applied in this thesis. Six published semiconductor failure analysis cases were detailed described for each experiment in this thesis. Case-1: Thin LOCOS did not block implant induced P+ bridge caused DC standby high current failure. Case-2: N type dopant was found at P+ area caused single device fail. Case-3: Possible solution for well inspection in advanced nanometer process. Case-4: Bipolar Vertical PNP Beta Loss by silicide margin short fail issue. Case-5: CMOS Chip Power Leakage by photo-resistor bubble fail issue. Case-6: Nano-scale extra-shallow junctions suffered silicide roughness induced vertical junction leakage failure issue. Based on these real applications and evidences, AFM has been becoming a powerful and new generation technique for physical failure analysis investigation. This thesis would like to introduce each detail and research in the AFM based method application.

碩士
國立中央大學
環境工程研究所在職專班
106
In the semiconductor packaging and testing industry, many raw materials (such as flammable chemicals, strong acids, strong alkalis, strong oxidizing substances and flammable gases) are used in various processes equipment operated at high temperatures according to the process requirements. While the products are regulated by the relevant laws and regulations, these laws and regulations are not as clear and specific as the standards that can be followed in foreign countries, resulting in that enterprises can only rely on the experience to set up their equipment procurement specifications. In this case, it is easy to derive the fire caused by poor equipment safety design and improper on-site management. In addition, the design of the plant is mostly in a closed environment, which leads to the difficulty of people evacuation and disaster relief when the fire occurs. In this study, the Failure Mode and Effect Analysis (FMEA) and EMI S10 risk assessment method are used to analyze the hazards that can be caused in the process of equipment with high-temperature operation (i.e., High Temperature Equipment) by the functional failure of apparatus components, exhaust system and the safety interlock devices, and study the improvement countermeasures according to the risk assessment results. Using a semiconductor packaging and testing industry as a case, the failure analysis of the fire project caused by the process of High Temperature Equipment reveals that (i) among the Equipment Components, the highest risk priority number is when the element material is carbonated (RPN was 320); (ii) in the Exhaust System, when the pipeline full of internal condensation, the highest risk priority number is scored 392; (iii) among the Safety interlock System, the highest risk priority number of the safety interlock devices and the temperature detection devices are scored 336. According to the analysis of various failure items, it was found that the reason of the high risk priority, apart from causality, the general problems are lack of existing prevention and detection deficiencies, which leads to the failure to prevent the occurrence. This study also takes how to early prevention of failures as an improvement strategy to compare the differences between before and after improvement that is made. It is found that the abnormity of the equipment components is carbonated by the element material, the RPN scored is reduced to 128; the RPN scored of the safety interlock system is reduced to 96, and the RPN scored of the temperature detection system is reduced to 144; in exhaust pipe, the abnormal internal condensation in the pipeline which RPN scored fell from 392 to 112. From the outcome of the improvement, it is known that the Standards should be set up early in the stage of equipment planning and evaluation to reduce the failure rate of process equipment during operation. According to the above results, the risk value of internal condensation of exhaust pipeline is the highest, resulting in condensation phenomenon caused when a high temperature gas contacting with cold surfaces. The second high risk value is the safety interlock system, because the equipment machine is not connected with the safety interlock devices. The element material carbonation ranks the third place, because the component temperature exceeds the circuit insulation temperature. Hence. the above projects in the management control should be strengthened via personnel routine testing, cleaning frequency and regular infrared thermal imaging instrument to measure temperature; further, in engineering control, a condensation collecting plate and the exhaust flow detector can be set up inside the exhaust pipe and safety interlock system should controlled by double and double loop protection devices; lastly, the material carbonation of the circuit material should be replaced with a heat-resistant material.