Dissertationen zum Thema „Sécurité intégrée“
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Schellekens-Gaiffe, Marie-Ange. „La sécurité environnementale dans les relations extérieures de l’Union européenne : vers une approche intégrée de la prévention des conflits et crises externes“. Thesis, La Rochelle, 2017. http://www.theses.fr/2017LAROD004/document.
Der volle Inhalt der QuelleThe link between environmental problems and risks to security is progressively gaining ground, even though diverging opinions still prevail as to the exact nature and challenges of this interaction. The increasingly visible impacts of climate change have indirectly strengthened the prominence of this issue on the international agenda. Can the European Union, born itself from a successful approach to conflict prevention and international leader for environmental protection contribute to this aim ? Beyond the immediate urgency of environmental problems, environmental security carries several elements which could turn it into a driving force for the European Union's foreign policy by an improved understanding of the actual roots and multifaceted nature of numerous conflicts. This would allow the EU to support global stability and to strengthen its role on the international scene
Métivier, Virginie. „Méthode d'application d'un système de management de l'environnement, de la sécurité et de la santé : cas du site industriel de production pharmaceutique Abbott“. Orléans, 2002. http://www.theses.fr/2002ORLE1045.
Der volle Inhalt der QuelleThe purpose of this report is to promote the implementation of a general method in respect of the environmental, safety and management systems for the pharmaceutical industry and more specifically for the industrial site for the Abbott laboratory. After giving an outline of the already existing environment, safety and hygiene management systems, we would develop the method and tools chosen to implement the management system for the Abbott site. Based on numerous examples we would also evaluate the results achieved by the new system. Eventually, we would analyse all sociological constraints and limits that held back the implementation of this environment, safety and hygiene management system that was chosen for the industrial site
Hirschhorn, Damien. „Haïti : une intervention exemplaire ? La Réforme du Secteur de Sécurité en Haïti“. Thesis, Lyon 3, 2014. http://www.theses.fr/2014LYO30053/document.
Der volle Inhalt der QuelleFirst of all, this thesis aims at understanding, while using the example of Haiti, if Security Sector Reforms carried out within international interventions in crisis or post-conflict countries are effective at accomplishing their objectives and providing the best support for sustainable changes to host States. Finally this document's objective is also to serve as a support in finding new solutions and new practices to successfully achieve Security Sector Reforms
Farre-Malaval, Margerie. „Les rapports juridiques entre sécurité maritime et protection du milieu marin : essai sur l'émergence d'une sécurité maritime environnementale en droit international et de l'union européenne“. Thesis, Lyon 3, 2011. http://www.theses.fr/2011LYO30070.
Der volle Inhalt der QuelleBegun with the study of the European Union rules engendered by the wreck of Erika, the present research was refined around the relation between marine safety and marine environment protection while growing rich of the observation of the international rules. From then on, the idea was to study the collision between two elements neither equivalents, nor completely different and to see what this legal "big-bang" had provoke.The first part will envisage the renewal of the function of marine safety around the purpose of marine environment protection. Indeed, by the middle of the XXth century, the appearance of the environmental concerns comes to destabilize the classic distribution of the skills between the flag State and the coastal State. The freedom, founding principle of the order of seas, has been transformed to adapt itself to the realities of the marine environment protection. It becomes then the principle of sustainable use of the sea, the new key of the distribution of sovereignties on the sea. A shape of environmental governance of the maritime safety appears to establish around the International Maritime Organization and the European Union.The second part will allow to bring to light the redefining of the normative space of maritime safety in the prism of the objective of prevention of the pollutions. Originally, the regulations of marine safety aimed at protecting the sailormen against the dangers of the sea. Henceforth, it is today a question of protecting the biosphere, the humanity and its future generations. That is why the classic marine safety, become insufficient, evolves towards a more modern, " environmental " notion
Abdalla, Iskandar Boctor Christine. „Le développement durable et le droit de l'environnement : La sécurité nationale hydraulique au Moyen-Orient“. Thesis, Artois, 2012. http://www.theses.fr/2012ARTO0301/document.
Der volle Inhalt der QuelleThe concept of National Hydraulic Security (NHS) is the result of changing the concept ofsecurity from military security to multi-faceted security. The traditional method of managing thisnational hydraulic security is a way hydraulic unsustainable. The National Hydraulic Securityneeds to know a new hydraulic evolution that takes into account not only the qualitatif andquantitatif challenges but also the environmental challenges. A version of this sustainablenational hydraulic security interest to the hydraulic common interests of all riparian countries ofthe three rivers: Nile, Jordan, Tigris and Euphrates. In addition, the concept of SustainableDevelopment must grow significantly to obtain a hydraulic sustainable management of theNational Hydraulic Security
Germain, Fabien. „Sécurité cryptographique par la conception spécifique de circuits intégrés“. Phd thesis, Ecole Polytechnique X, 2006. http://pastel.archives-ouvertes.fr/pastel-00001858.
Der volle Inhalt der QuelleJoaquim, da Rolt Jean. „Testabilité versus Sécurité : Nouvelles attaques par chaîne de scan & contremesures“. Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20168.
Der volle Inhalt der QuelleIn this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks
Porquet, Joël. „Architecture de sécurité dynamique pour systèmes multiprocesseurs intégrés sur puce“. Phd thesis, Université Pierre et Marie Curie - Paris VI, 2010. http://tel.archives-ouvertes.fr/tel-00574088.
Der volle Inhalt der QuelleBeringuier-Boher, Noémie. „Evaluation et amélioration de la sécurité des circuits intégrés analogiques“. Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT007.
Der volle Inhalt der QuelleWith the development of the Internet of things, the number of connected devices is in constant increase. These objects use a large amount of data including personal credentials. Therefore, security has become a major constraint for System on Chips (SoCs) designers. Moreover, in a context more and more aggressive in terms of performances and time to market, it is important to find low cost security solutions. Although the hardware security is often treated from a digital point of view, almost every SoCs is also using analog and mixed IP. Thus, this work presents different steps to improve the security of analog IPs, from vulnerability analysis to countermeasures design validation, and behavioral modeling in the context of mixed signals and low cost applications. To protect any system, the first requirement is to know its vulnerabilities. To do so, a vulnerability analysis methodology dedicated to analog circuit has been developed. Using the results of this analysis, countermeasures can be designed during the development of the circuit and not at the end. The circuit security is thus improved without dramatically increasing its cost in terms of design time. The analysis of a clock system generator, an analog IP widely used in current SoCs and composed with various sub-circuits, has shown fault attacks using Laser Photoelectric Stimulation (LPS) or supply voltage glitches as important threats. After having identified the 2 previous attacks types as major threats, their effects on analog circuits are analyzed. Existing countermeasures are then compared and evaluated for the protection of analog IPs. To complete these solutions, two analog detectors have been designed to detect laser and supply voltage glitch attacks considering SoCs level constraints. Electrical test of these detectors processed on CMOS 28nm FD-SOI technology proved their efficiency. Theoretical vulnerability analysis has shown some difficulties. Indeed, analog circuits are sensitive to numerous parametrical faults. Also, the high interconnection of various sub-circuits makes the faults propagation analysis quite difficult. To help this analysis, electrical simulations at transistor level are necessary. These simulations are quite long and, so the behavioral modeling of analog circuits to help the analysis of supply voltage glitch attack effects has been studied. To do so, the developed models must be developed according different constraints presented in this report and applied to the behavioral modeling of a real analog circuit. This illustration proved that behavioral models can be used to help to identify which attack shapes are the most likely to induce faults in the circuit
Porquet, Joël. „Architecture de sécurité dynamique pour systèmes multiprocesseurs intégrés sur puces“. Paris 6, 2010. http://www.theses.fr/2010PA066511.
Der volle Inhalt der QuelleBaranowski, Sylvie. „Utilisation d'un microcontrôleur dans une application de sécurité : test et évaluation du taux de couverture de pannes et de la sécurité“. Lille 1, 1988. http://www.theses.fr/1988LIL10095.
Der volle Inhalt der QuelleBondoux-Wisniewski, Caroline. „Automatisation de prototypes industriels et d'unités pilotes dédiées à l'extrapolation des procédés : méthodologie et rôle du cahier des charges de la phase d'étude à la conception pour des procédés chimiques et biochimiques“. Paris 6, 2002. http://www.theses.fr/2002PA066044.
Der volle Inhalt der QuelleSokpor, Adjo Sefofo. „Conception de balises de détresse intégrées aux équipements de sécurité maritime“. Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S068/document.
Der volle Inhalt der QuelleOver the last few years, wireless communications have grown dramatically, with the development of more and more communication standards, which open the way to multiple applications such as: mobile telephony, biomedical, maritime, the civilian and the military. Today, wireless communications have diversified and multiplied. This leads to the design of antennas that are always more innovative, more efficient and smaller in size (miniaturization). The FLEXBEA project (FLEXible BEAcon) aims to develop a new concept of low cost miniature distress beacons (AIS and COSPAS-SARSAT) integrated into marine safety equipment such as a life raft and a lifejacket safety. This equipment is intended for professionals of the sea and boaters. The main advantage of this new concept is the integration in maritime safety equipment of a distress function in case of major problem: man overboard (MOB, Man OverBoard) for example during a shipwreck. Different antennas have been studied. We present planar antennas (dipole type or printed monopoly) developed in the UHF band: a dipole solution with folded strands is proposed to reduce the bulk, and two modes of supply (symmetrical / asymmetrical) are compared. Examples of monopole antennas are then presented with a modification of their geometry (Bow-tie or meander type structures) to ensure optimal miniaturization. Then the wired antennas selected for the project, with a modeling of these antennas by an equivalent circuit (RLC). Analytical formulas are proposed to determine the RLC component values involved in the circuit model. Then we went to the design of the beacon antenna. Two antennas were designed and measured. A ribbon monopoly with introduction of localized components for the AIS and COSPAS-SARSAT beacon, and a helix antenna operating in the AIS band, integrated into the "SIMY" beacon. Many achievements and measurements have been made to characterize its antennas
Damien, Aliénor. „Sécurité par analyse comportementale de fonctions embarquées sur plateformes avioniques modulaires intégrées“. Thesis, Toulouse, INSA, 2020. http://www.theses.fr/2020ISAT0001.
Der volle Inhalt der QuelleToday, air transportation is one of the safest transportation modes, with a continuous reduction in the risk of accidents since the early days of aviation. In recent decades, several advances have been achieved in avionics systems (such as connectivity, resource sharing, COTS) to improve the passenger experience and reduce costs. While these evolutions have been well managed from safety point of view, nevertheless, from the security point of view, they have led to new attack vectors. Considering recent attacks on embedded or critical systems, it is becoming essential to anticipate the potential malicious modification of an aircraft application in future systems. Recently, several studies have been carried out to improve aircraft security. Most of them focus on the aircraft interfaces (communication means or software updates) or on the development phase (risk analysis, vulnerability tests). A few works proposed in-depth defense measures (OS hardening, intrusion detection), in particular to protect against internal attackers.In this thesis, we assume that a malicious application was introduced inside an avionics computer. More specifically, we study the development of an intrusion detection system within an avionics computer. Taking into account the specific constraints related to avionics applications, we have formalized six specific objectives to develop such solution, related to detection efficiency, aircraft lifetime, performance, real-time impact, safety impact, and certification. To fulfill these objectives, this thesis presents a comprehensive approach to integrate an anomaly-based intrusion detection system into an avionics computer, based on the IMA (Integrated Modular Avionics) development process. The normal behavior of an avionics application is modeled during the integration phase, based on the static and deterministic characteristics of avionics applications, and on the existing means that have been developed for safety. This model of normal behavior is then embedded onboard the aircraft and allows to detect any deviation of behavior during the operation phase. In addition, an on-board anomaly analysis function offers a first level of on-board diagnosis and some flexibility once the aircraft is in operation.This approach has been implemented on two case studies to validate its feasibility and assess its detection capabilities and resource consumption. Firstly, an attack injection tool was developed in order to compensate for the lack of existing means to test our approach. Then, several behavioral detection solutions were proposed and evaluated, based on two types of models: OCSVM and Timed Automata. Two of them were implemented in an embedded prototype, and provided very good results in terms of detection efficiency and resource consumption. Finally, the anomaly analysis function has also been implemented, and the associated experiments showed encouraging results regarding the possibility to embed such a system onboard an aircraft
Vaquié, Bruno. „Contributions à la sécurité des circuits intégrés face aux attaques par canaux auxiliaires“. Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20133/document.
Der volle Inhalt der QuelleSide channel attacks such as power analysis attacks are a threat to the security of integrated circuits.They exploit the physical leakage of circuits during the cryptographic computations to retrieve the secret informations they contain. Many countermeasures, including hardware, have been proposed by the community in order to protect cryptosystems against such attacks. Despite their effectiveness, their major drawback is their significant additional cost in area, speed and consumption. This thesis aims at proposing low cost countermeasures able to reduce the leaks and offering a good compromise between security and costs. First we identify the main sources of leakage of a cryptographic system that integrates an iterative hardware architecture of a symetric algorithm. Then we propose several low cost countermeasures, which aim at reducing this leakage. Finally, we evaluate the robustness of our solutions against side channel attacks
Bouesse, Ghislain Fraidy. „Contribution à la conception de circuits intégrés sécurisés : l'alternative asynchrone“. Grenoble INPG, 2005. http://www.theses.fr/2005INPG0155.
Der volle Inhalt der QuelleThis work is focused on the development of new design techniques for protecting integrated circuits against power analysis attacks by exploiting the properties of asynchronous logic. In fact, among non intrusive attacks which exploit the hardware weaknesses of cryptographic devices for retrieving confidential information, the power analysis attacks are the most efficient and the easiest to implement. In this work the countermeasures developed are based on Quasi Delay Insensitive asynchronous logic (QDI) and focused on the protection of integrated circuits against power analysis attacks. The properties of the QDI asynchronous logic are particularly interesting for securing an implementation because it enables the designer to precisely control the current activity. The work was first concentrated on the evaluation of the resistance of asynchronous logic to DPA. The results obtained demonstrate the potentiality of the QDI properties to improving chips' security compared to synchronous logic, and enable us to identify some limits of this approach. We propose a formal analysis to evaluate the sensitivity of QDI asynchronous logic to power analysis and then present new countermeasures that exploit the QDI logic topology. These studies lead to the specification of a new design methodology for implementing secure asynchronous chips which will be integrated in the TAST framework, TIMA Asynchronous Synthesis Tools
Harrari, Mounia. „Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l'Internet des Objets“. Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0621.
Der volle Inhalt der QuelleIn the last decade, the Internet of Things deployment highlighted new needs and constraints in terms of consumption and area for integrated circuits. However, the recent craze for connected objects and due to the extremely pressing time-to-market demand, the manufacturers commercialize their products, sometimes at the expense of their security. The main focus of the work undertook during this thesis consists in the hybridization of the CMOS technology with the emerging non-volatile memory technology STT-MRAM. This study aims to determine the assets and drawbacks of this hybridization. These innovating architectures must allow the development of low power applications and support the growth of secured connected objects. Thus, the design of a hybrid CMOS/STT-MRAM lightweight cryptographic algorithm based on the PRESENT cipher is realised.This is how the first study carried out consisted in investigating the robustness of STT-MRAM junctions facing physical attacks, before their integration in the cryptographic algorithm. To do this, laser fault injections were performed in order to evaluate the integrity of the sensitive data stored in the cells.Following the observations carried out on these experiments on perpendicular STT-MRAM memories, a new physical attack detector based on this memory technology is proposed, designated by DDHP. This sensor allows simultaneous detection of photoelectrical and thermal attacks that can target integrated circuits
Clavier, Christophe. „De la sécurité physique des crypto-systèmes embarqués“. Versailles-St Quentin en Yvelines, 2007. http://www.theses.fr/2007VERS0028.
Der volle Inhalt der QuelleIn a world full of threats, the development of widespread digital applications has led to the need for a practical device containing cryptographic functions that provide the everyday needs for secure transactions, confidentiality of communications, identification of the subject or authentication for access to a particular service. Among the cryptographic embedded devices ensuring these functionalities, smart cards are certainly the most widely used. Their portability (a wallet may easily contain a dozen) and their ability to protect its data and programs against intruders, make it as the ideal ``bunker'' for key storage and the execution of cryptographic functions during mobile usage requiring a high level of security. Whilst the design of mathematically robust (or even proven secure in some models) cryptographic schemes is an obvious requirement, it is apparently insufficient in the light of the first physical attacks that were published in 1996. Taking advantage of weaknesses related to the basic implementation of security routines, these threats include side-channel analysis which obtains information about the internal state of the process, and the exploitation of induced faults allowing certain cryptanalysis to be performed which otherwise would not have been possible. This thesis presents a series of research works covering the physical security of embedded cryptosystems. Two parts of this document are dedicated to the description of some attacks and to a study of the efficiency of conceivable countermeasures. A third part deals with that particular and still mainly unexplored area which considers the applicability of physical attacks when the cryptographic function is, partly or totally, unknown by the adversary
Cioranesco, Jean-Michel. „Nouvelles Contre-Mesures pour la Protection de Circuits Intégrés“. Thesis, Paris 1, 2014. http://www.theses.fr/2014PA010022/document.
Der volle Inhalt der QuelleEmbedded security applications are diverse and at the center of all personal embedded applications. They introduced an obvious need for data confidentiality and security in general. Invasive attacks on hardware have always been part of the industrial scene. The aim of this thesis is to propose new solutions in order to protect embedded circuits against some physical attacks described above. ln a first part of the manuscript, we detail the techniques used to achieve side-channel, invasive attacks and reverse engineering. I could implement several of these attacks during my thesis research, they will be detailed extensively. ln the second part we propose different hardware countermeasures against side-channel attacks. The third part is dedicated to protection strategies against invasive attacks using active shielding and we conclude this work by proposing an innovative cryptographic shield which is faulty and dpa resistant
Ruillé, Jonathan. „Management des risques intégré des navires et de leurs armements : un ferry peut-il être une organisation à haute fiabilité ?“ Nantes, 2015. http://www.theses.fr/2015NANT4027.
Der volle Inhalt der QuelleDespite the technological developments making the ships more "safe", the recent accidents - Costa Concordia (2012), Sewol (2014), Norman Atlantic (2014) - remind us that the maritime transport remains a risk activity. For as much, the maritime traffic has never been as important, either in number of vessels or in tons of freight transported, and these accidents have a relatively low frequency. The multiplication of regulations and conventions (SOLAS, MARPOL, STCW, ISM, ISPS; MLC 2006, etc. ) is intended to reduce them because their consequences can be quickly dramatic: hundreds, or even thousands, of people may lose their lives due to a shipwreck. Thus, ferries have an imperative of reliability counteracting the dangers that threaten them. The responsibilities which weigh on the crew are important, and each day they have to lead the ship of a point A to a point B safely while respecting the deadlines. This thesis is concerned with the organizational reliability by examining the organization allowing the crew, in link with the stakeholders (shipping company, approved inspection body, etc. ), to seize all of requirements for risk management and performance expected, in a context of globalization and increased competition. During our five-week boarding of two ferries, we combined a qualitative approach (observations, interviews) to a quantitative approach (questionnaires) to answer the question: a ferry can be a high reliability organization ?
Dumont, Mathieu. „Modélisation de l’injection de faute électromagnétique sur circuits intégrés sécurisés et contre-mesures“. Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS031.
Der volle Inhalt der QuelleThis thesis is devoted to the study of electromagnetic fault injection attack on se-cure integrated circuits. Electrical modeling permits to simulate the coupling between an EM probe injection and the circuit supply and ground grids in order to understand the effect of the EM pulse. This modeling is then applied on a logic circuit simulation with a D flip-flop and its components. The simulation results were used to determine the various faults that could be induced by this attack and to explain their formation. Measurements on a test circuit revealed the appearance of timing and sampling faults and validated ex-perimentally the proposed model. Finally, some countermeasures based on the model are proposed in order to increase the robustness of a circuit against electromagnetic fault in-jection
Stadler, Yves. „Tatouage d'image semi-fragile pour appareil mobile intégré dans une chaîne de certification“. Thesis, Université de Lorraine, 2012. http://www.theses.fr/2012LORR0395/document.
Der volle Inhalt der QuelleSmartphones are nowadays ubiquitous, they can be found in anybody's hands with no consideration of one's age or work. They are used to create, manipulate and broadcast security constrained pieces of information (in term of confidentiality, integrity or authenticity). Different protection types can be found, with regard to the security constraints (copyrights, document tracking, etc.). This thesis presents a watermarking scheme tailored for smartphone-captured images, which scheme allows the use of the image as an evidence. The goal is linking the evidence to the image and forbidding any content modification. Confidentiality not being a constraint, the scheme keeps the image visible and allow its broadcast. Contextual pieces of data are part of the evidence: author name, date of shot and geographic location (geolocation). Few means are available to assess this geolocation. The second part of the thesis aims to fill this gap by proposing software based countermeasures to enhanced geolocation authenticity. Finally, the last chapter presents a critic of security works on the other authentication methods required to forge a strong proof
Kussener-Combier, Edith. „Conception de circuits intégrés de régulation intelligente pour les microprocesseurs sécurisés (carte à puce)“. Lille 1, 2002. https://pepite-depot.univ-lille.fr/RESTREINT/Th_Num/2002/50376-2002-117.pdf.
Der volle Inhalt der QuelleCe circuit additionnel permet en particulier de réaliser une conversion et une régulation de tension de gain unitaire. La phase de conception de ces convertisseurs nécessite une interprétation correcte des résultats de simulation. Dans ce sens, vue de l'alimentation, une macro modélisation de l'activité du microprocesseur est nécessaire. Une macro modélisation basée sur la simulation et la programmation de plusieurs inverseurs logiques est proposée. Les mesures effectuées sur plusieurs prototypes confirment bien l'interprétation théorique proposée ainsi que les résultats attendus à partir des simulations. Différentes solutions permettent de crypter les informations confidentielles qui circulent aux travers des plots d'alimentations des cartes à puces. Les solutions proposées consistent à ajouter des blocs sécuritaires élémentaires pouvant être pilotés par le microprocesseur via des algorithmes de cryptage
Dehbaoui, Amine. „Analyse Sécuritaire des Émanations Électromagnétiques des Circuits Intégrés“. Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20020.
Der volle Inhalt der QuelleThe integration of cryptographic primitives in different electronic devices is widely used today incommunications, financial services, government services or PayTV.Foremost among these devices include the smart card. According to a report published in August 2010, IMS Research forecasts that the smart card market will reach 5.8 billion units sold in this year. The vast majority is used in telecommunications (SIM) and banking.The smart card incorporates an integrated circuit which can be a dedicated processor for cryptographic calculations. Therefore, these integrated circuits contain secrets such as secret or private keys used by the symmetric or asymmetric cryptographic algorithms. These keys must remain absolutely confidential to ensure the safety chain.Therefore the robustness of smart cards against attacks is crucial. These attacks can be classifiedinto three main categories: invasive, semi-invasive and non-invasive.Non-invasive attacks can be considered the most dangerous, since this kind of attack can be achieved without any contact with the circuit.Indeed, while using electronic circuits that compose them are subjected to variations in current and voltage. These variations generate an electromagnetic radiation propagating in the vicinity of the circuit.These radiations are correlated with secret information (eg a secret key used for authentication). Several attacks based on these leakages were published by the scientific community.This thesis aims to: (a) understand the different sources of electromagnetic emanations of integrated circuits, and propose a localized near field attack to test the robustness of a cryptographic circuit and (b) propose counter-measures to these attacks
Razafindraibe, Hanitriniaina Mamitiana Alin. „Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés“. Montpellier 2, 2006. http://www.theses.fr/2006MON20117.
Der volle Inhalt der QuelleHély, David. „Conception en vue du test de circuits sécurisés“. Montpellier 2, 2005. http://www.theses.fr/2005MON20123.
Der volle Inhalt der QuelleLaabidi, Selma. „Méthodologie de conception de composants intégrés protégés contre les attaques par corrélation“. Phd thesis, Ecole Nationale Supérieure des Mines de Saint-Etienne, 2010. http://tel.archives-ouvertes.fr/tel-00488013.
Der volle Inhalt der QuelleAcunha, guimarães Leonel. „Techniques de Test Pour la Détection de Chevaux de Troie Matériels en Circuits Intégrés de Systèmes Sécurisés“. Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT080/document.
Der volle Inhalt der QuelleThe world globalization has led the semiconductor industry to outsource design and fabrication phases, making integrated circuits (ICs) potentially more vulnerable to malicious modifications at design or fabrication time: the hardware Trojans (HTs). New efficient testing techniques are thus required to disclose potential slight and stealth HTs, and to ensure trusted devices. This thesis studies possible threats and proposes two new post-silicon testing techniques able to detect HTs implanted after the generation of the IC netlist. The first proposed technique exploits bulk built-in current sensors (BBICS) -- which are originally designed to identify transient faults in ICs -- by using them as testing mechanisms that provide statistically-comparable digital signatures of the devices under test. With only 16 IC samples, the testing technique can detect dopant-level Trojans of zero-area overhead. The second proposition is a non-intrusive technique for detection of gate-level HTs in asynchronous circuits. With this technique, neither additional hardware nor alterations on the original test set-up are required to detect Trojans smaller than 1% of the original circuit. The studies and techniques devised in this thesis contribute to reduce the IC vulnerability to HT, reusing testing mechanisms and keeping security features of original devices
Pamula, Danuta. „Opérateurs arithmétiques sur GF (2m) : étude de compromis performances-consommation-sécurité“. Rennes 1, 2012. http://www.theses.fr/2012REN1E011.
Der volle Inhalt der QuelleThe efficiency of devices performing arithmetic operations in finite field is crucial for the efficiency of ECC systems. Regarding the dependency of the system on those devices we conclude that the robustness of the system also depends on the robustness of the operators. The aim of conducted researches described in the dissertation was to propose efficient and robust against power analysis side-channel attacks hardware arithmetic operators on GF(2m) dedicated to elliptic curve cryptography (ECC) applications. We propose speed and area efficient hardware solutions for arithmetic operators on GF(2m). Designed units are flexible and operate, due to assumed applications, on large numbers (160-600 bits). Next we propose algorithmic and architectural modifications improving robustness against side-channel power analysis attacks of designed solutions. The final goal described was to find a tradeoff between security of arithmetic operators and their efficiency. We were able to perform such modifications increasing robustness of designed hardware arithmetic operators, which do not impact negatively overall performance of the operator. The attempt to protect the lowest level operations of ECC systems, the finite field operations, is a first known attempt of that type. Till now researches described in literature on the subject did not concern the finite field level operations protections. They considered only protections of curve or ECC protocol level operations. Proposed protections contribute and we may say complete already developed means of protections for ECC systems. By combining protections of all levels of operation of the ECC system it is assumed that it is possible to make the system very robust against side-channel power analysis attacks
Papadimitriou, Athanasios. „Modélisation au niveau RTL des attaques laser pour l'évaluation des circuits intégrés sécurisés et la conception de contremesures“. Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT041/document.
Der volle Inhalt der QuelleMany aspects of our current life rely on the exchange of data through electronic media. Powerful encryption algorithms guarantee the security, privacy and authentication of these exchanges. Nevertheless, those algorithms are implemented in electronic devices that may be the target of attacks despite their proven robustness. Several means of attacking integrated circuits are reported in the literature (for instance analysis of the correlation between the processed data and power consumption). Among them, laser illumination of the device has been reported to be one important and effective mean to perform attacks. The principle is to illuminate the circuit by mean of a laser and then to induce an erroneous behavior.For instance, in so-called Differential Fault Analysis (DFA), an attacker can deduce the secret key used in the crypto-algorithms by comparing the faulty result and the correct one. Other types of attacks exist, also based on fault injection but not requiring a differential analysis; the safe error attacks or clocks attacks are such examples.The main goal of the PhD thesis was to provide efficient CAD tools to secure circuit designers in order to evaluate counter-measures against such laser attacks early in the design process. This thesis has been driven by two Grenoble INP laboratories: LCIS and TIMA. The work has been carried out in the frame of the collaborative ANR project LIESSE involving several other partners, including STMicroelectronics.A RT level model of laser effects has been developed, capable of emulating laser attacks. The fault model was used in order to evaluate several different secure cryptographic implementations through FPGA emulated fault injection campaigns. The injection campaigns were performed in collaboration with TIMA laboratory and they allowed to compare the results with other state of the art fault models. Furthermore, the approach was validated versus the layout of several circuits. The layout based validation allowed to quantify the effectiveness of the fault model to predict localized faults. Additionally, in collaboration with CMP (Centre Microélectronique de Provence) experimental laser fault injections has been performed on a state of the art STMicroelectronics IC and the results have been used for further validation of the fault model. Finally the validated fault model led to the development of an RTL (Register Transfer Level) countermeasure against laser attacks. The countermeasure was implemented and evaluated by fault injection campaigns according to the developed fault model, other state of the art fault models and versus layout information
De, Castro Stephan. „Modélisation et simulation d'attaque laser sur des circuits sécuritaires“. Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT317/document.
Der volle Inhalt der QuelleNowadays, more and more microelectronic circuits are used for critical purposes, such as payment or identification. Then those circuit sparked interest form attackers. Among the different ways to retrieve the cipher key, laser illumination is a very efficient one. Thereby, the protection of the circuit against these attacks becomes an important point for designers. However, to determine the resistance of a circuit against laser injection, laser illumination has to be performed. If the circuit do not match the security requirement, it has to be changed, which represent a large cost in terms of design time and fabrication cost. In order to predict the effect of a laser injection, electrical model and simulator have been developed.First, a description of the physical phenomenon (photoelectric effect), which leads to the fault injection in the circuit, is given. Then a description of the first electrical model developed using current sources to model the illumination effect.Then, a practical attack is performed on a crypto processor implanting the AES algorithm. This experimentation allows us to compare the two ways of laser injections, injection from the front side or the back side of the circuit. It comes out that the best way of injection depends on the circuit aimed and the laser bench at disposal of the attacker. Indeed, on the studied circuit, better exploitable fault can be injected, from the front side injection with a large laser spot than from the back side with the same laser spot size. This result can be explained by the effect of the metal lines above the circuit, which reduce the area of illuminated silicon.We discuss then about the validity of the electrical model for more recent technology nodes. Thus a new electrical model is developed for more recent CMOS bulk and Fully Depleted Silicon On Insulator (FDSOI) technologies. From its transistor structure, the CMOS FDSOI technology seems to be more resistant to laser injection than the CMOS bulk technology. This observation is confirmed by experimentation.Finally, we perform laser injection on a memory element (here a flip-flop chain). These experimentations show that even if the CMOS FDSOI technology seems to be more resistant, fault can be injected. With a one micro meter laser spot, the attacker can inject the wanted fault type in the flip-flop (bit set or bit reset) on 28nm CMOS bulk and FDSOI technologies. Even if, the fault injection is still possible, from the attacker point of view, fault injection is more difficult in a circuit using the CMOS 28nm FDSOI technology than the CMOS 28nm bulk one. Indeed, the gap between the fault injection threshold and the breaking threshold is narrower for the FDSOI than the bulk. Moreover, a breaking phenomenon has been observed in the FDSOI technology when multiple laser shot are performed in the same place.To conclude, the previous work allows updating and developed a new electrical model for the recent CMOS bulk and FDSOI technology under illumination, to compare those technologies against laser illumination. It comes out, that even if fault injection is possible for both technologies, the practical attack is more difficult to achieve on a CMOS FDSOI circuit
Montoya, Maxime. „Sécurité adaptative et énergétiquement efficace dans l’Internet des Objets“. Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEM032.
Der volle Inhalt der QuelleThe goal of this work is to propose new methods that provide both a high security and a high energy efficiency for integrated circuits for the IoT.On the one side, we study the security of a mechanism dedicated to energy management. Wake-up radios trigger the wake-up of integrated circuits upon receipt of specific wake-up tokens, but they are vulnerable to denial-of-sleep attacks, during which an attacker replays such a token indefinitely to wake-up a circuit and deplete its battery. We propose a new method to generate unpredictable wake-up tokens at each wake-up, which efficiently prevents these attacks at the cost of a negligible energy overhead.On the other side, we improve on the energy efficiency of hardware countermeasures against fault and side-channel attacks, with two different approaches. First, we present a new combined countermeasure, which increases by four times the power consumption compared to an unprotected implementation, introduces no performance overhead, and requires less than 8 bits of randomness. Therefore, it has a lower energy overhead than existing combined protections. It consists in an algorithm-level power balancing that inherently detects faults. Then, we propose an adaptive implementation of hardware countermeasures, which consists in applying or removing these countermeasures on demand, during the execution of the protected algorithm, in order to tune the security level and the energy consumption. A security evaluation of all the proposed countermeasures indicates that they provide an efficient protection against existing hardware attacks
Marchand, Cédric. „Conception de matériel salutaire pour lutter contre la contrefaçon et le vol de circuits intégrés“. Thesis, Lyon, 2016. http://www.theses.fr/2016LYSES058/document.
Der volle Inhalt der QuelleCounterfeiting and theft affects all industrial activities in our society. Electronic products are the second category of products most concerned by these issues. Among the most affected electronic products, we find mobile phones, tablets, computers as well as more basic elements such as analog and digital circuits or integrated circuits. These are the heart of almost all electronic products and we can say that a mobile phone is counterfeited if it has at least one counterfeit integrated circuit inside. The market of counterfeit integrated circuit is estimated between 7 and 10% of the global semi-conductors market, which represents a loss of at least 24 billion euros for the lawful industry in 2015. These losses could reach 36 billion euros in 2016. Therefore, there is an absolute necessity to find practical and efficient methods to fight against counterfeiting and theft of integrated circuits. The SALWARE project, granted by the French "Agence Nationale de la Recherche" and by the "Fondation de Recherche pour l’Aéronautique et l’Espace", aims to fight against the problem of counterfeiting and theft of integrated circuitsFor that, we propose to design salutary hardwares (salwares). More specifically,we propose to cleverly combine different protection mechanisms to build a completeactivation system. Activate an integrated circuit after its manufacturing helpsto restore the control of integrated circuits to the true owner of the intellectualproperty.In this thesis, we propose the study of three different protection mechanismsfighting against counterfeiting and theft of integrated circuits. First, the insertionand the detection of watermark in the finite state machine of digital and synchronoussystems will be studied. This mechanism helps to detect counterfeit or theftparts. Then, a physical unclonable function based on transcient effect ring oscillatoris implemented and characterized on FPGA. This protection mechanism is used toidentify integrated circuit with a unique identifier created thanks to the extractionof entropy from manufacturing process variations. Finally, we discuss the hardwareimplementations of lightweight block ciphers, which establish a secure communicationduring the activation of an integrated circuit
Haddad, Patrick. „Caractérisation et modélisation de générateurs de nombres aléatoires dans les circuits intégrés logiques“. Thesis, Saint-Etienne, 2015. http://www.theses.fr/2015STET4008/document.
Der volle Inhalt der QuelleRandom number generators (RNG) are primitives that produce independent and uniformly distributed digital values, RNG are used in secure environments where the use of random numbers is required (generation of cryptographic keys, nonces in cryptographic protocols, padding values, countermeasures against side-channel attacks) and where the quality of the randomness is essential. All electronic components with a security function, such as smart cards, include one or more random generators (based on physical principles). Consequently, the RNG is an essential primitive for security applications. A flaw in security of the random number generation process directly impacts the security of the cryptographic system. This thesis focuses on the study of physical RNG (PTRNG), the modeling of its randomness and an electronic characterizations of the circuit. This study is in the context of the AIS-31 standard which is published by the BSI* and followed by many European countries. This standard is one of the few that require a characterizations of the PTRNG and a stochastic model. In this context, it is crucial to validate the evaluation methodology proposed by these standards and l focused on them during my thesis.*Bundesamt fiir Sicherheit in der Informationstechnik, federal agency German responsible for the security of information technology
Ibambe, Gatsinzi Martine. „Etudes des performances radiofréquences d'antennes 5,8 GHz intégrées sur des véhicules automobilesApplications sécuritaires et communications à courte portée“. Paris 11, 2008. http://www.theses.fr/2008PA112179.
Der volle Inhalt der QuelleEvolution in technology allows automotive manufacturers and suppliers to propose more and more embedded electronic systems to make driving safer and easier. However, the number of road victims is still high. In this context, a study of the integration of a pre-crash radar operating at 5. 8GHz has been launched by Renault. This system is based on low cost components and allows the activation of either automatic braking to avoid any crash or restraint systems in case of an impending collision. Besides, to reduce the number of integrated antennas on vehicles, other applications, such as smart keyless and vehicle to vehicle communication systems can use the same radar antenna. The main objective of the proposed research work is to study the integration of 5. 8 GHz antennas on vehicles. In particular, simulations are performed to investigate the integration on numerical prototypes to make up for problems posed by the late availability of car prototypes and the reduction of cost in industry. For this purpose, we focused on the 4 following topics: 1) Simulation at higher frequencies and measurement to evaluate integration effects on antenna radiation. 2) Analysis of wave propagation in vehicular environments to quantify and qualify propagation channel in the 5. 8 GHz frequency band. 3) Study of radar signal propagation. The goal is to develop a method for echo signal analysis of the radar prototype by modeling and simulating the antenna and different targets in road environments. 4) Evaluation of antenna integration and wave propagation at 24 GHz. We have presented a study of a second type of pre-crash radar currently under investigation
Nejat, Arash. „Tirer parti du masquage logique pour faciliter les méthodes de détection des chevaux de Troie hardware“. Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT004.
Der volle Inhalt der QuelleThe ever-increasing complexity of integrated circuits (ICs) design and manufacturing has necessitated the employment of third parties such as design-houses, intellectual property (IP) providers and fabrication foundries to accelerate and economize the development process. The separation of these parties results in some security threats. Untrustworthy fabrication foundries are suspected of three security threats: hardware Trojans, IP piracy, and IC overproduction. Hardware Trojans are malicious circuitry alterations in IC layouts intended for sabotage objectives.Some IC design modifications, known as Design-for-Trust (DfTr) have been proposed to facilitate Trojan detection methods or prevent Trojan insertion. In addition, key-based modifications, known as design masking or obfuscation, have been proposed to protect IPs/ICs from IP piracy and IC overproduction. They obscure circuits’ functionality by modifying circuits such that they do not correctly work without being fed with a correct key.In this thesis, we propose three DfTr methods based on leveraging the masking approach to hinder Trojan insertion. The first proposed DfTr method aims to maximize obscurity and simultaneously minimize the rare signal counts in circuits under masking. Rare signals barely have transitions during circuit operations and so the use of them causes hardware Trojans will not be easily activated and detected during circuit tests. The second proposed DfTr facilitates path delay analysis-based Trojan detection methods. Since the delay of shorter paths varies less than longer ones’, the objective is to generate fake short paths for nets which only belong to long paths by repurposing the masking elements. Our experiments show that this DfTr method increases the Trojan detectability in modified circuits and also provides the advantages of masking methods. The aim of the third DfTr method is to facilitate power-analysis-based Trojan detection. In a masked circuit by the proposed method, one has more control over the switching activity of the different circuit parts. For instance, one can target one part of the circuit, increase its switching activity, and simultaneously decrease the other parts’ switching activity; consequently, if the target part includes an hardware Trojan, its switching activity and so power consumption rises, although the total power consumption of the circuit goes down due to low switching activity rates in most parts of the circuit. When the circuit consumes less power, the power measurement noise abates. The noise can disturb to observe Trojans’ effects on the power consumption of Trojan-infected circuits.In addition, in this thesis, we introduce a CAD tool that can run various masking algorithms on gate-level netlists. The tool can also perform logic simulation and estimate circuit area, power consumption, and performance at the gate level
Cozzi, Maxime. „Infrared Imaging for Integrated Circuit Trust and Hardware Security“. Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS046.
Der volle Inhalt der QuelleThe generalization of integrated circuits and more generally electronics to everyday life systems (military, finance, health, etc) rises the question about their security. Today, the integrity of such circuits relies on a large panel of known attacks for which countermeasures have been developed. Hence, the search of new vulnerabilities represents one of the largest contribution to hardware security. The always rising complexity of dies leads to larger silicon surfaces.Circuit imaging is therefore a popular step among the hardware security community in order to identify regions of interest within the die. In this objective, the work presented here proposes new methodologies for infrared circuit imaging. In particular, it is demonstrated that statistical measurement analysis can be performed for automated localization of active areas in an integrated circuit.Also, a new methodology allowing efficient statistical infrared image comparison is proposed. Finally, all results are acquired using a cost efficient infrared measurement platform that allows the investigation of weak electrical source, detecting power consumption as low as 200 µW
Marconot, Johan. „Fonction Physique Non-clonable pour la Sécurité du Cycle de Vie d'un Objet Cyber-physique“. Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT011.
Der volle Inhalt der QuelleThe thesis focus on the conception of solutions to secure, all along its lifecycle, the assets and the functions which are embedded into a connected object. The lifecycle induces multiple interactions which expose the assets. Still, each actor may need private access in order to perform technical operations which have to be done. The solution has to securely manage the access requests but also takes account of the fact that most of the connected object are resources constraints system.We provide two main contributions: the analysis of security requirements for the device lifecycle and a new model of extraction circuit for strong digital PUF. The identified configuration for the extraction circuit offer trade-off between the circuit area, the frequency and the security metrics. It allows to conceive an efficient DPUF which could be integrated at fabrication chip, ensuring authentication property and performance requirements for lifecycle
Takarabt, Sofiane. „Évaluation pré-silicium de circuits sécurisés face aux attaques par canal auxiliaire“. Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT015.
Der volle Inhalt der QuelleEmbedded systems are constantly threatened by various attacks, including side-channel attacks. To guarantee a certain level of security, cryptographic implementations must validate evaluation tests recommended by the certification standards, and thus meet the market needs. For this reason, it is necessary to implement reliable countermeasures to counter this type of attacks. However, once these countermeasures are implemented, verification and validation tests can be very costly in terms of time and money. Thus, optimizing the lifecycle of the circuit, between the design stage and the evaluation stage is paramount. We will explore a very broad class of existing attacks (passive and active), and propose methods of pre-silicon level assessments, allowing on the one hand, to detect the different types of leakages that a given attacker can exploit, and on the other hand, expose different techniques to counter these attacks, while respecting the performance and area aspect. In our analyses, we apply formal and empirical methods to track the impact of each vulnerability on the different abstraction levels of the circuit, and thus propose optimal countermeasures
Tobich, Karim. „Évaluation de l’efficacité des techniques d’injection de fautes, au sein de microcontrôleurs, par agression électromagnétique“. Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20017.
Der volle Inhalt der QuelleNowadays, LASER remains the tool the most effective and most used to inject faults within the modern secure microcontrollers. Among its main advantages we can quote its strong spatial and temporal resolutions. These advantages are however accessible only to the price of consequent investments in time and money with a cost oscillating between two and four hundreds of thousand euro according to the quality of the LASER. Besides these financial aspects, the publication by scientists, as well as the integration by the manufacturers of smart cards, effective countermeasures, as light detectors, incited to the development of alternative faults injection techniques with moderate costs. Among these alternative techniques, we find the electromagnetic fault injection techniques which allow perturbing the behavior of circuits. It is in this context that this thesis presents the main effects of this kind of fault injection by proceeding to a first decomposition in front side and back side, then in one second bound to the shape of the disturbing signal (harmonic or pulsed) used. So, we highlight coupling effects with metals lines but also a Forward effect on the target circuit
Mkhinini, Asma. „Implantation matérielle de chiffrements homomorphiques“. Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT092/document.
Der volle Inhalt der QuelleOne of the most significant advances in cryptography in recent years is certainly the introduction of the first fully homomorphic encryption scheme by Craig Gentry. This type of cryptosystem allows performing arbitrarily complex computations on encrypted data, without decrypting it. This particularity allows meeting the requirements of security and data protection, for example in the context of the rapid development of cloud computing and the internet of things. The algorithms implemented are currently very time-consuming, and most of them are implemented in software. This thesis deals with the hardware acceleration of homomorphic encryption schemes. A study of the primitives used by these schemes and the possibility of their hardware implementation is presented. Then, a new approach allowing the implementation of the two most expensive functions is proposed. Our approach exploits the high-level synthesis. It has the particularity of being very flexible and generic and makes possible to process operands of arbitrary large sizes. This feature allows it to target a wide range of applications and to apply optimizations such as batching. The performance of our co-design was evaluated on one of the most recent and efficient homomorphic cryptosystems. It can be adapted to other homomorphic schemes or, more generally, in the context of lattice-based cryptography
Ba, Papa-Sidy. „Détection et prévention de Cheval de Troie Matériel (CTM) par des méthodes Orientées Test Logique“. Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT271/document.
Der volle Inhalt der QuelleIn order to reduce the production costs of integrated circuits (ICs), outsourcing the fabrication process has become a major trend in the Integrated Circuits (ICs) industry. As an inevitable unwanted side effect, this outsourcing business model increases threats to hardware products. This process raises the issue of un-trusted foundries in which, circuit descriptions can be manipulated with the aim to possibly insert malicious circuitry or alterations, referred to as Hardware Trojan Horses (HTHs). This motivates semiconductor industries and researchers to study and investigate solutions for detecting during testing and prevent during fabrication, HTH insertion.However, considering the stealthy nature of HTs, it is quite impossible to detect them with conventional testing or even with random patterns. This motivates us to make some contributions in this thesis by proposing solutions to detect and prevent HTH after fabrication (during testing).The proposed methods help to detect HTH as well during testing as during normal mode(run-time), and they are logic testing based.Furthermore, we propose prevention methods, which are also logic testing based, in order tomake harder or quasi impossible the insertion of HTH both in netlist and layout levels
Lecomte, Maxime. „Système embarque de mesure de la tension pour la détection de contrefaçons et de chevaux de Troie matériels“. Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEM018/document.
Der volle Inhalt der QuelleDue to the trend to outsourcing semiconductor manufacturing, the integrity of integrated circuits (ICs) became a hot topic. The two mains threats are hardware Trojan (HT) and counterfeits. The main limit of the integrity verification techniques proposed so far is that the bias, induced by the process variations, restricts their efficiency and practicality. In this thesis we aim to detect HTs and counterfeits in a fully embedded way. To that end we first characterize the impact of malicious insertions on a network of sensors. The measurements are done using a network of Ring oscillators. The malicious adding of logic gates (Hardware Trojan) or the modification of the implementation of a different design (counterfeits) will modify the voltage distribution within the IC.Based on these results we present an on-chip detection method for verifying the integrity of ICs. We propose a novel approach which in practice eliminates this limit of process variation bias by making the assumption that IC infection is done at a lot level. We introduce a new variation model for the performance of CMOS structures. This model is used to create signatures of lots which are independent of the process variations. A new distinguisher has been proposed to evaluate whether an IC is infected. This distinguisher allows automatically setting a decision making threshold that is adapted to the measurement quality and the process variation. The goal of this distinguisher is to reach a 100\% success rate within the set of covered HTs family. All the results have been experientially validated and characterized on a set of FPGA prototyping boards
Leonhard, Julian. „Analog hardware security and trust“. Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS246.
Der volle Inhalt der QuelleThe ongoing globalization and specialization of the integrated circuit (IC) supply chain has led semiconductor companies to share their valuable intellectual property (IP) assets with numerous parties for means of manufacturing, testing, etc. As a consequence, sensitive IPs and ICs are being exposed to untrusted parties, resulting in serious piracy threats such as counterfeiting or reverse engineering. In this thesis we develop methods to secure analog and mixed signal IPs/ICs from piracy threats within the supply chain. We propose an anti-piracy methodology for locking mixed-signal ICs via logic locking of their digital part. Furthermore, we propose an anti-reverse engineering methodology camouflaging the effective geometry of layout components. Finally, we propose an attack to break all analog circuit locking techniques that act upon the biasing of the circuit. The presented techniques have the potential to protect analog and mixed-signal circuits against a large subset of all the possible risk scenarios while inflicting low overheads in terms of area, power and performance
Dallali, Manel. „Analyse de la sécurité et de la protection anti-bélier des conduites coudées d'adduction d'eau potable en polyéthylène haute densité“. Thesis, Université de Lorraine, 2017. http://www.theses.fr/2017LORR0115.
Der volle Inhalt der QuelleWater scarcity will be threatening more than 40% of the world population by 2050, more than 240 million people will not have a source of improved water. In fact, to ensure a sustainable management of this resource, the minimization of the leakages in drinking-water supply network is vital. Pipe rupture, a frequent phenomenon in urban zones, starts with a defect, under the effect of constraints caused by an unusual over pressure: Water Hammer. Since the 80s, polyethylene is being widely considered in manufacturing the pipelines water supply networks. Nevertheless, junctions are the most dangerous zones in the networks. As a result, it is vital to study the tear resistance of the angled conducts in PEHD. To solve this problem, a study is approached with an experimental investigation and a digital approach by fine elements in order to characterize the behavior in the fissuring of pipe bends PE100. Two methodologies are proposed to determine the tenacity of the PEHD: the method of the J-integral and the method of the sharp's movement opening of crack "CTOD ". The combination of these tools permits to choose the critical value of the integral J as a value of the tenacity of the HDPE. In addition, a simplified formula was proposed based on the calculation of the J-integral as a function of the pressure in water supply networks in the presence of a superficial defect. Finally, the water hammer phenomenon was investigated in order to determine the overpressure with a mathematical model which was developed in this thesis. The fluid-structure interaction was found to be important in defining the pressure at elbow pipe
Boige, François. „Caractérisation et modélisation électrothermique compacte étendue du MOSFET SiC en régime extrême de fonctionnement incluant ses modes de défaillance : application à la conception d'une protection intégrée au plus proche du circuit de commande“. Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0084/document.
Der volle Inhalt der QuelleNowaday, the challenge of the transition to carbon-free energy involves a systematic use of electrical energy with power electronics at the heart of the exchanges. To meet the challenges, power electronics requires increasingly high-performance devices to provide a high level of integration, high efficiency and a high level of reliability. Today, the power transistor, of the MOSFET type, made of silicon carbide (SiC) is a breakthrough technology that allows us to meet the challenges of integration and efficiency through their low level of loss and high switching speed. However, their limited reliability and low robustness at extreme operating conditions such as repetitive short-circuits are now hindering their expansion in industrial applications. In this thesis, an in-depth study of the short-circuit behaviour of an exhaustive set of commercial devices, describing all the structural and technological variants involved, was carried out on a specific test bench developed during the thesis, in order to quantify their short-circuit resistance. This study highlighted both generic and singular properties of SiC semiconductors for every Mosfet version such as a dynamic gate leakage current and a failure mode by a short-circuit grid-source leading, under certain conditions of use and for certain Mosfet structures, to a self-blocking drain-source. A systematic research of the physical understanding of the observed mechanisms was carried out by an approach combining an internal technological analysis of the failed devices and a fine electrothermal modelling. A compact electrothermal modeling extended to failure mode consideration has been established and implemented in circuit software. This model was confronted with numerous experimental results describing a short-circuit cycle up to failure. This model offers an interesting analytical support and also helps the design of protection circuits. Thus, as an application, a driver equipped with a digital processing part has been designed and validated in detection mode for several short-circuit scenarios but also potentially for the detection of the degradation of the power component grid. Other more exploratory work has also been carried out in partnership with the University of Nottingham to study the impact of repeated pulse short-circuit regimes on the aging of parallel chips with dispersions. The propagation of a first failure mode from a "weak" device was also studied. This work paves the way for the design of intrinsically safe and available converters by taking advantage of the atypical and original properties of SiC semiconductors and Mosfet in particular
Shrivastwa, Ritu Ranjan. „Enhancements in Embedded Systems Security using Machine Learning“. Electronic Thesis or Diss., Institut polytechnique de Paris, 2023. http://www.theses.fr/2023IPPAT051.
Der volle Inhalt der QuelleThe list of connected devices (or IoT) is growing longer with time and so is the intense vulnerability to security of the devices against targeted attacks originating from network or physical penetration, popularly known as Cyber Physical Security (CPS) attacks. While security sensors and obfuscation techniques exist to counteract and enhance security, it is possible to fool these classical security countermeasures with sophisticated attack equipment and methodologies as shown in recent literature. Additionally, end node embedded systems design is bound by area and is required to be scalable, thus, making it difficult to adjoin complex sensing mechanism against cyberphysical attacks. The solution may lie in Artificial Intelligence (AI) security core (soft or hard) to monitor data behaviour internally from various components. Additionally the AI core can monitor the overall device behaviour, including attached sensors, to detect any outlier activity and provide a smart sensing approach to attacks. AI in hardware security domain is still not widely acceptable due to the probabilistic behaviour of the advanced deep learning techniques, there have been works showing practical implementations for the same. This work is targeted to establish a proof of concept and build trust of AI in security by detailed analysis of different Machine Learning (ML) techniques and their use cases in hardware security followed by a series of case studies to provide practical framework and guidelines to use AI in various embedded security fronts. Applications can be in PUFpredictability assessment, sensor fusion, Side Channel Attacks (SCA), Hardware Trojan detection, Control flow integrity, Adversarial AI, etc
Poucheret, François. „Injections électromagnétiques : développement d’outils et méthodes pour la réalisation d’attaques matérielles“. Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20255/document.
Der volle Inhalt der QuelleAttacks based on fault injection consist in disturbing a cryptographic computation in order to extract critical information on the manipulated data. Fault attacks constitute a serious threat against applications, due to the expected effects: bypassing control and protection, granting access to some restricted operations… Nevertheless, almost of classical ways (T°,V,F) and optical attacks are limited on the newest integrated circuits, which embed several countermeasures as active shield, glitch detectors, sensors… In this context, potentials of Electromagnetic active attacks must undoubtedly be taken into account, because of their benefits (penetrating characteristics, contactless energy transmission, low cost power production…). In this work, EM active attacks based on continuous mode are presented, with a particular attention to the development and optimization of injection probes, with a complete characterization of EM fields provided by each probe at the IC surface. Finally, some experiments are realized on internal clock generator or on true random numbers generators, then evaluated to prove the efficiency of these techniques. Keywords. Hardware Attacks, Faults Attacks, EM induced faults, CMOS Integrated Circuits
Camponogara, Viera Raphael. „Simulating and modeling the effects of laser fault injection on integrated circuits“. Thesis, Montpellier, 2018. http://www.theses.fr/2018MONTS072/document.
Der volle Inhalt der QuelleLaser fault injections induce transient faults into ICs by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the classical laser-fault injection model is based on the addition of current sources to the various sensitive nodes of MOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of ICs designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR drop that contribute to the fault injection process. This thesis describes our research on the assessment of this contribution. It shows by simulation and experiments that during laser fault injection campaigns, laser-induced IR drop is always present when considering circuits designed in deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that uses standard CAD tools to allow the use of the enhanced electrical model to simulate laser-induced faults at the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor as large as 3 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems. Furthermore, experimental and simulation results show that even though laser fault injection is a very local and accurate fault injection technique, the induced IR drops have a global effect spreading through the supply network. This gives experimental evidence that the effect of laser illumination is not as local as usually considered
De, Nardi Christophe. „Techniques d'analyse de défaillance de circuits intégrés appliquées au descrambling et à la lecture de données sur des composants mémoires non volatiles“. Toulouse, INSA, 2009. http://eprint.insa-toulouse.fr/archive/00000307/.
Der volle Inhalt der QuelleProtection of data stored on integrated circuit memories is a major preoccupation of our society. Today, these circuits are everywhere, from electronics for the general public (SIM charts, USB flash memories), to satellites, bank cards and numerical passports. This thesis strives to answer the following question: “Is it possible to physically read the information stored in a non volatile memory (NVM)?”. Contrary to software attacks, physical approaches (hardware) destroy components. To reach the information contained in the core of a memory, this progressive destruction must be controlled. We have developed a four stage method adapted to each NVM family: 1) technological analysis, 2) address descrambling, 3) sample preparation to make data accessible and 4) data reading. The difficulty and complexity of this work can be better understood if we start with the desired result. For example, the data (0 or 1) of flash memory cell corresponds to the presence/absence of a charge of several hundred electrons stored on the floating gate of a transistor. Detecting the correct value requires a technique with strong topographic and potential resolution, which is as non invasive as possible to avoid erasing the electrons which are by nature, highly mobile. For current memory technologies (node ≥90nm), we show that passive voltage contrast (PVC) or electric modes of Atomic Force Microscopy (AFM) are adapted to these constraints. With this approach, stage n°3 of sample preparation is the key step to expose storage location of programmed charges without losing them. The method described in this thesis is based on a functional and physical characterization of memories coupled with an understanding of component preparation and analysis techniques. The experience gained over the past three years shows the importance of choosing the right reading technique and adjusting parameters according to the type of memory to be analyzed. For future technologies (node ≤65nm) or silicon on insulator (SOI), our method should remain applicable