Thematische Bibliographien / Non-Volatile SRAM

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Auswahl der wissenschaftlichen Literatur zum Thema „Non-Volatile SRAM“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

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Zeitschriftenartikel zum Thema "Non-Volatile SRAM"

Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang und Kai Bu. „A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory“. Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.

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NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.

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Mispan, Mohd Syafiq, Aiman Zakwan Jidin, Muhammad Raihaan Kamarudin und Haslinah Mohd Nasir. „Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices“. Indonesian Journal of Electrical Engineering and Computer Science 25, Nr. 1 (01.01.2022): 105. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp105-112.

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An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memory-based PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exploiting the inherent SRAM as PUF could wide-spread the adoption of PUF. Therefore, in this study, we evaluate the suitability of inherent SRAM available in ATMega2560 microcontroller on Arduino platform as PUF that can provide a unique fingerprint. First, we analyze the start-up values (SUVs) of memory cells and select only the cells that show random values after the power-up process. Subsequently, we statistically analyze the characteristic of fifteen SRAM-PUFs which include uniqueness, reliability, and uniformity. Based on our findings, the SUVs of fifteen on-chip SRAMs achieve 42.64% uniqueness, 97.28% reliability, and 69.16% uniformity. Therefore, we concluded that the available SRAM in off-the-shelf commodity hardware has good quality to be used as PUF.

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Angizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben und Deliang Fan. „MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET“. ACM Transactions on Design Automation of Electronic Systems 27, Nr. 2 (31.03.2022): 1–18. http://dx.doi.org/10.1145/3484222.

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Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

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Vijay, H. M., und V. N. Ramakrishnan. „Radiation effects on memristor-based non-volatile SRAM cells“. Journal of Computational Electronics 17, Nr. 1 (08.11.2017): 279–87. http://dx.doi.org/10.1007/s10825-017-1080-x.

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Singh, Damyanti, Neeta Pandey und Kirti Gupta. „Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell“. Microelectronics Journal 135 (Mai 2023): 105773. http://dx.doi.org/10.1016/j.mejo.2023.105773.

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Janniekode, Uma Maheshwar, Rajendra Prasad Somineni, Osamah Ibrahim Khalaf, Malakeh Muhyiddeen Itani, J. Chinna Babu und Ghaida Muttashar Abdulsahib. „A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications“. Symmetry 14, Nr. 4 (07.04.2022): 768. http://dx.doi.org/10.3390/sym14040768.

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This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications.

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Priya, G. Lakshmi, Namita Rawat, Abhishek Sanagavarapu, M. Venkatesh und A. Andrew Roobert. „Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell“. Micromachines 14, Nr. 2 (17.01.2023): 232. http://dx.doi.org/10.3390/mi14020232.

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

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Khan, Asif. „(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories“. ECS Meeting Abstracts MA2022-02, Nr. 15 (09.10.2022): 805. http://dx.doi.org/10.1149/ma2022-0215805mtgabs.

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Ferroelectric field-effect transistors (FEFETs) are receiving significant attention from the microelectronics community for next-generation memory technologies, especially as embedded non-volatile elements for data-centric applications. The main attractive features of FEFETs are that write energy and speed of FEFETs are within an order of magnitude of respective metrics for SRAMs (FEFET ~1 fJ and 1-10 ns vs. SRAM: <1 fJ and <1 ns), all the while requiring a significantly smaller cell size (FEFET 50-60F2 vs. SRAM 120-150F2) and close-to-zero standby leakage power – provided that FEFETs are integrated at the same advanced technology nodes as SRAMs [1]. In this talk, we will discuss the potential path for FEFET toward fulfilling this vision, by addressing the outstanding technological challenges: ultra-fast read-after write, reliability, voltage scaling and variation. To that end, our recent exposition on the trap and reliability physics of FEFETs will highlighted. We will highlight, based on newly developed experimental schemes, how the simultaneous capture and emission of electrons and holes in write cycles occur at the interface and the grain boundaries in the time domain, where in the band-diagram, these traps (acceptors and donors) are located and how exactly they result in the degradation of the read speed and reliability with continued write cycling. Based on these insights, we move on show how engineering the interfacial layer and the ferroelectric grain structure can enable ultra-fast read-after write and write voltage and dramatic improvements in reliability and variation, towards achieving a high-density, ultra-high speed memory technology. This research is supported by the National Science Foundation, the Defense Advanced Research Program Agency (DARPA), the Semiconductor Research Corporation (SRC) - Global Research Collaboration (GRC) program, the Applications and Systems-Driven Center for Energy-Efficient Integrated Nano Technologies (ASCENT), one of six centers in the Joint University Microelectronics Program (JUMP), a SRC program sponsored by the DARPA, and an Intel Rising Star award. [1] Mikolajick, T., Schroeder, U. & Slesazeck, S. The past, the present, and the future of ferroelectric memories. IEEE Trans. Electron Devices 67, 1434–1443 (2020). [2] Asif Islam Khan, Ali Keshavarzi, and Suman Datta. “The future of ferroelectric field-effect transistor technology." Nature Electronics 3.10 (2020): 588-597.

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Pan, James N. „Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology“. MRS Advances 4, Nr. 48 (2019): 2577–84. http://dx.doi.org/10.1557/adv.2019.212.

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ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

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P, Saleem Akram. „Non-Volatile 7T1R SRAM cell design for low voltage applications“. International Journal of Emerging Trends in Engineering Research 7, Nr. 11 (15.11.2019): 704–7. http://dx.doi.org/10.30534/ijeter/2019/487112019.

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Dissertationen zum Thema "Non-Volatile SRAM"

Kotte, Aparna Reddy. „Memristor based SRAM“. OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2790.

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AN ABSTRACT OF THE THESIS OFAPARNA REDDY KOTTE, for the Master of science degree in Electrical and Computer Engineering, presented on November 5,2020, at Southern Illinois University Carbondale. TITLE: MEMRISTOR BASED SRAM MAJOR PROFESSOR: Dr. Haniotokis Themistoklis The easy usage and less standby leakage are the main reasons SRAMs are mostly used for mobile applications both on chip and off chip memories. Various SRAM cells have been under research for many years. In post-CMOS era, rising of memristor technology is expected to be a key driver due to its outstanding features to replace the present memory technologies. Memristor is a non-volatile component that memorizes the proportion of current passed through it, reserving the data in the form of resistance. With its non-volatile characteristics, ultra-low power consumption, higher density capability, fast operating speed, ability to function as a multi-level cell and good scalability and compatibility with CMOS technology, memristor technology is found to be best to replace the SRAM cells. Memristor based SRAM cell can be an efficient circuit component that is being proposed in this thesis which consumes less power and allows the conventional SRAM cell to retain data with lesser number of transistors at power-down without any auxiliary circuit. This thesis contains the operating procedure and simulated results of the proposed four transistor and two memristor SRAM using 90nm technology performed on Cadence Virtuoso tool.

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Dogan, Rabia. „System Level Exploration of RRAM for SRAM Replacement“. Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.

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Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors. This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement. Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency. By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems. In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.

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Bazzi, Hussein. „Resistive memory co-design in CMOS technologies“. Electronic Thesis or Diss., Aix-Marseille, 2020. http://www.theses.fr/2020AIXM0567.

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De nombreuses applications (internet des objets, systèmes embarqués automobiles et médicales, intelligence artificielle) ont besoin d’un circuit intégré (ou SoC pour System on Chip) avec des mémoires non volatiles embarquées performantes pour fonctionner de manière optimale. Bien que la mémoire Flash soit largement utilisée aujourd'hui, cette technologie nécessite une tension élevée pour les opérations de programmation et présente des problèmes de fiabilité difficiles à gérer au-delà du nœud technologique 18 nm, augmentant les coûts de conception et de fabrication des circuits. Dans ce contexte, l'industrie du semi-conducteur est à la recherche d’une mémoire non volatile alternative pouvant remplacer les mémoires Flash. Parmi les candidats actuellement étudiés (MRAM - mémoire à accès aléatoire magnétique, PCM - mémoire à changement de phase, FeRAM - mémoire à accès aléatoire Ferroélectrique), les mémoires résistives (RRAM) offrent de meilleures performances sur différents points capitaux : compatibilité avec le processus de fabrication standard CMOS, consommation de courant, rapidité de fonctionnement, etc. La technologie RRAM peut être aisément introduite dans n'importe quel flot de conception ouvrant la voie au développement de nouvelles architectures qui répondent à l’engorgement des systèmes classiques Von Neumann. Dans cette thèse, l'objet principal est de montrer le potentiel d’intégration des dispositifs RRAM avec la technologie CMOS, à l’aide de simulation et de mesures électriques, afin d’élaborer différentes structures hybrides : mémoires à accès aléatoire statique (SRAM) non volatiles, générateurs de nombres aléatoires (TRNG) et réseaux de neurones artificiels
Many diversified applications (internet of things, embedded systems for automotive and medical applications, artificial intelligence) require an integrated circuit (SoC, System on Chip) with high-performance non-volatile memories to operate optimally. Although Flash memory is widely used today, this technology needs high voltage for programing operations and has reliability issues that are hard to handle beyond 18 nm technological node, increasing the cost of circuit design and fabrication. In this context, the semiconductor industry seeks an alternative non-volatile memory that can replace Flash memories. Among possible candidates (MRAM - Magnetic Random Access Memory, PCM - Phase Change Memory, FeRAM - Ferroelectric Random Access Memory), Resistive memories (RRAMs) offer superior performances on essential key points: compatibility with CMOS manufacturing processes, scalability, current consumption (standby and active), operational speed. Due to its relatively simple structure, RRAM technology can be easily integrated in any design flow opening the way for the development of new architectures that answer Von Neumann bottleneck. In this thesis, the main object is to show the integration abilities of RRAM devices with CMOS technology, using circuit design and electrical measurements, in order to develop different hybrid structures: non-volatile Static Random Access Memories (SRAM), True Random Number Generator (TRNG) and artificial neural networks

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Yi-SungTsou und 鄒亦淞. „Design of a Saving-Write-Energy Non-Volatile SRAM“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/ym6ecc.

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碩士
國立成功大學
電機工程學系
102
With the advancement of technology scaling, the leakage current issue becomes one of the most important challenges for SRAMs. Existing approaches usually use power gating or low supply voltage well-known data retention voltage to reduce the leakage energy consumption in standby mode. With the advent of nvSRAM, leakage current can be fully eliminated. Compared with conventional approaches, it can reach further energy saving by using powering off its supply voltage when data-backup is performed. However, not all of data are needed to back up. In this thesis, we propose a novel 10T2R RRAM-based nvSRAM with redundant bit-writes-aware controller which is considering redundant bit-writes condition. If data stored in SRAM cells are the same as that in RRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, backup energy for the data can be saved under redundant bit-writes conditions. Simulation shows that energy saving can reach by up to 93% when high resistive state is larger than 10MΩ. And as long as the probability of the redundant bit-writes is larger than 25% probability, the backup energy saving is achieved. The technique can be applied to normally-off computing systems, energy harvesting systems, L2/L3 Cache, and so on.

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Buchteile zum Thema "Non-Volatile SRAM"

Lacaze, Pierre Camille, und Jean-Christophe Lacroix. „State of the Art of DRAM, SRAM, Flash, HDD and MRAM Electronic Memories“. In Non-Volatile Memories, 13–57. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2014. http://dx.doi.org/10.1002/9781118789988.ch2.

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Pal, Soumitra, und N. S. Ranjan. „Design of Non-volatile SRAM Cell Using Memristor“. In Advances in Intelligent Systems and Computing, 175–83. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2757-1_19.

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Nikitha, L., N. S. Bhargavi und B. S. Kariyappa. „Design and Development of Non-volatile Multi-threshold Schmitt Trigger SRAM Cell“. In Lecture Notes in Electrical Engineering, 877–84. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5802-9_76.

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Kanika, Nitin Chaturvedi und S. Gurunarayanan. „Design and Analysis of a Hybrid Non-volatile SRAM Cell for Energy Autonomous IoT“. In Intelligent Computing Techniques for Smart Energy Systems, 57–65. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0214-9_8.

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Monga, Kanika, und Nitin Chaturvedi. „A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications“. In Communications in Computer and Information Science, 553–64. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_46.

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Raman Sundara Raman, Siddhartha. „A Review on Non-Volatile and Volatile Emerging Memory Technologies“. In Computer Memory and Data Storage. IntechOpen, 2024. http://dx.doi.org/10.5772/intechopen.110617.

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As technology scaling is approaching a stand-still with architectural advancements on modern day processors struggling to improve performance, coupled with the rise in machine learning topologies demanding better performing processors, there is a pressing need to address the reasons behind today’s performance bottleneck. These reasons include long access latency of memory technologies, scalability of memory designs, energy inefficiency incurred by increased performance, and additional area overhead. To explore these issues, a holistic understanding of existing memory technologies is essential. In this chapter, a review of different memory designs starting from volatile memory technologies such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), NAND/NOR flash to emerging non-volatile memory technologies such as Resistive Random Access Memory (RRAM), Magneto-resistive random access memory (MRAM), Ferroelectric Field effect transistor (FeFET) is presented, with specific consideration of tradeoffs involving area, performance, energy.

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Konferenzberichte zum Thema "Non-Volatile SRAM"

Ma, Yanjun. „Nonvolatile multibit SRAM, bit level caching, and multi-context computing for IoT“. In 2015 15th Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2015. http://dx.doi.org/10.1109/nvmts.2015.7457480.

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„Session 6 overview SRAM and non-volatile memories“. In 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 2002. http://dx.doi.org/10.1109/isscc.2002.992957.

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Yifu Gong, Na Gong, Ligang Hou und Jinhui Wang. „MTJ based data restoration in non-volatile SRAM“. In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016. http://dx.doi.org/10.1109/icsict.2016.7998635.

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Zhao, Weisheng, Eric Belhaire, Claude Chappert und Pascale Mazoyer. „Spintronic Device Based Non-volatile Low Standby Power SRAM“. In 2008 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2008. http://dx.doi.org/10.1109/isvlsi.2008.11.

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Bajjuri, Vishnu, N. Umapathi, G. Valarmathy und SU Suganthi. „A Novel Non-Volatile SRAM with Reduced Read Delay“. In 2023 International Conference on Next Generation Electronics (NEleX). IEEE, 2023. http://dx.doi.org/10.1109/nelex59773.2023.10420862.

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Mizutani, T., K. Takeuchi, T. Saraya, H. Shinohara, M. Kobayashi und T. Hiramoto. „Parallel Programmable Non-volatile Memory Using Normal SRAM Cells“. In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.a-7-04l.

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Lou, Qian, Mengying Zhao, Lei Ju, Chun Jason Xue, Jingtong Hu und Zhiping Jia. „Runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs“. In 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2017. http://dx.doi.org/10.1109/nvmsa.2017.8064477.

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Wang, Lina, Jinhui Wang, Zezhong Yang, Ligang Hou und Na Gong. „A low power CMOS technology compatible non-volatile SRAM cell“. In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021248.

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Kirubaraj, A. Alfred, und A. Affum Emmanuel. „Model design of non-volatile SRAM based on Magnetic Tunnel Junction“. In Technology (ICAST). IEEE, 2009. http://dx.doi.org/10.1109/icastech.2009.5409743.

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Ma, Yanjun. „Novel Multi-Bit Non-Volatile SRAM Cells for Runtime Reconfigurable Computing“. In 2015 IEEE International Memory Workshop (IMW). IEEE, 2015. http://dx.doi.org/10.1109/imw.2015.7150297.

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