Auswahl der wissenschaftlichen Literatur zum Thema „Ni(GeSn)“

Ni-based intermetallics are promising materials for forming efficient contacts in GeSn-based Si photonic devices. However, the role that Sn might have during the Ni/GeSn solid-state reaction (SSR) is not fully understood. A comprehensive analysis focused on Sn segregation during the Ni/GeSn SSR was carried out. In situ X-ray diffraction and cross-section transmission electron microscopy measurements coupled with energy-dispersive X-ray spectrometry and electron energy-loss spectroscopy atomic mappings were performed to follow the phase sequence, Sn distribution and segregation. The results showed that, during the SSR, Sn was incorporated into the intermetallic phases. Sn segregation happened first around the grain boundaries (GBs) and then towards the surface. Sn accumulation around GBs hampered atom diffusion, delaying the growth of the Ni(GeSn) phase. Higher thermal budgets will thus be mandatory for formation of contacts in high-Sn-content photonic devices, which could be detrimental for thermal stability.

The prospect of GeSn semiconductors for silicon-integrated infrared optoelectronics brings new challenges related to the metastability of this class of materials. As a matter of fact, maintaining a reduced thermal budget throughout all processing steps of GeSn devices is essential to avoid possible material degradation. This constraint is exacerbated by the need for higher Sn contents exceeding 8 at. % along with an enhanced strain relaxation to achieve efficient mid-infrared devices. Herein, as a low thermal budget solution for post-epitaxy processing, we elucidate the effects of laser thermal annealing (LTA) on strain-relaxed Ge0.89Sn0.11 layers and Ni-Ge0.89Sn0.11 contacts. Key diffusion and recrystallization processes are proposed and discussed in the light of systematic microstructural studies. LTA treatment at a fluence of 0.40 J/cm2 results in a 200–300 nm-thick layer where Sn atoms segregate toward the surface and in the formation of Sn-rich columnar structures in the LTA-affected region. These structures are reminiscent of those observed in the dislocation-assisted pipe-diffusion mechanism, while the buried GeSn layers remain intact. Moreover, by tailoring the LTA fluence, the contact resistance can be reduced without triggering phase separation across the whole GeSn multi-layer stacking. Indeed, a one order of magnitude decrease in the Ni-based specific contact resistance was obtained at the highest LTA fluence, thus confirming the potential of this method for the functionalization of direct bandgap GeSn materials.

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this Abstract, we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys. On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added. The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel. These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics. Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”. References: [1] M. Liu et al. ACS Appl. Nano Mater. 4, 94-101 (2021) [2] S. Wirths et al. Nature Photonics 9, 88-92 (2015) [3] J. Kouvetakis, J. Menendez, A. V. G. Chizmeshya: Annu. Rev. Mater. Res. 36:497-554 (2006) Figure 1

The Ni/Ge0.9Sn0.1 solid-state reaction was monitored by combining in situ X-ray diffraction, in-plane reciprocal space map measurements and in-plane pole figures. A sequential growth was shown, in which the first phase formed was an Ni-rich phase. Then, at 518 K, the mono-stanogermanide phase Ni(Ge0.9Sn0.1) was observed. This phase was stable up to 873 K. Special attention has been given to the nature and the crystallographic orientation of the Ni-rich phase obtained at low temperature. It is demonstrated, with in-plane pole figure measurements and simulation, that it was the ∊-Ni5(Ge0.9Sn0.1)3 metastable phase with a hexagonal structure.

Des efforts dans l'industrie des semiconducteurs sont constamment déployés afin d'améliorer différents paramètres comme les performances des dispositifs ou la vitesse de transfert des données. Pour atteindre ces avancées, des voies innovantes peuvent être considérées telles que la modification des étapes des procédés de production, l'architecture des dispositifs ou les matériaux qui constitueront ces dispositifs. Le germanium-étain (GeSn), alliage du groupe IV, est un matériau intéressant à intégrer dans des dispositifs électroniques ou opto-électroniques. Le GeSn peut être utilisé comme stresseur des source et drain dans les MOSFET Ge (metal–oxide–semiconductor field-effect transistors) et pour obtenir des canaux à haute mobilité dans les pMOSFET et les pTFET (thin field-effect transistors). D'autre part, l'ajout d'une quantité suffisante de Sn dans le réseau du Ge (environ 10 at.%) offre la possibilité d'obtenir une structure à bande interdite directe. Ce matériau pourrait alors être utilisé pour réaliser un laser du groupe IV intégré de façon monolithique et compatible avec la technologie Si-CMOS (complementary metal-oxide-semiconductor). Quelle que soit l'application, des contacts métalliques ou intermétalliques à faible résistance, stables et fiables sont des composants clés pour injecter le courant électrique dans les dispositifs. Les intermétalliques Ni / GeSn ont été considérés comme un matériau de contact adapté. Cette thèse était donc consacrée au l’étude systématique complète et à la caractérisation d'intermétalliques Ni / GeSn pour contacter des dispositifs basés sur GeSn. Les propriétés des couches de type Ni / GeSn analysées en termes de la séquence de phases, de l’évolution morphologique et électrique au cours de la réaction à l'état solide, sont présentées en premier. Ensuite, différentes alternatives seront décrites pour améliorer la stabilité thermique des contacts à base de Ni : l'utilisation de la pré-amorphisation par implantation (PAI), l’addition d’un élément d’alliage (Co, Pt) et l'utilisation de l'impulsion laser comme technique de recuit. Une autre alternative concernant la métallisation de GeSn a base de Ti est également mentionnée. Grâce à ces études, une analyse complète et systématique du système Ni / GeSn a été réalisée. De plus, l'identification de différentes alternatives pour modifier les conditions du processus qui peuvent améliorer la stabilité thermique du système Ni / GeSn a été réalisée. Les résultats obtenus représentent un bon point de départ pour élaborer des contacts de haute qualité, stables et fiables sur GeSn, qui peuvent être entièrement intégrés dans des dispositifs électroniques ou optoélectroniques
Efforts on the semiconductor industry are constantly made to improve different parameters like the devices performance or the speed of data transference. To reach these advances, innovative alternatives can be considered: changing the production processes steps, the device architecture or the materials that will constitute the devices. Germanium-Tin (GeSn), group-IV alloy, corresponds to an interesting material to integrate in electronic or opto-electronic devices. GeSn material can be used as source and drain stressor in Ge MOSFETs (metal–oxide–semiconductor field-effect transistors), and as high mobility channels in both pMOSFETs and pTFETs (thin field-effect transistors). On the other hand, the addition of a sufficient amount of Sn in the Ge lattice structure (about 10 at.%) offers the potential to get a direct band-gap structure. This material could be then used to achieve a monolithically integrated group-IV laser that is compatible with Si-CMOS technology (complementary metal-oxide-semiconductor). No matter the application, low-resistive, stable and reliable metallic or intermetallic contacts are key components to inject electric current in the devices. Ni / GeSn intermetallics have been considered as suited contact material for these kinds of applications. This PhD thesis was therefore dedicated to the systematic and comprehensive development and characterization of Ni / GeSn intermetallics to contact GeSn-based devices. The Ni / GeSn properties analyzed in terms of: phase sequence, morphological and electrical evolution during the solid-state reaction is presented first. As Ni / GeSn intermetallics exhibit a poor thermal stability, different alternatives such as the use of pre-amorphization by implantation (PAI), the addition of alloying elements (Co, Pt) and the use of laser annealing are also studied to enhance the contact thermal stability. Ultimately, another alternative concerning Ti metallization is also mentioned. Thanks to these studies, a comprehensive and systematic analysis of the Ni / GeSn system was realized. In addition, the identification of different alternatives to modify the process conditions that can enhance the Ni / GeSn system thermal stability was achieved. The results obtained represent a good starting point to elaborate high quality, stable and reliable GeSn-based contacts that can be fully integrated in electronic or opto-electronic devices

L’objectif de cette thèse est d’étudier la fabrication de films minces semi-conducteurs Ge1–xSnx par pulvérisation cathodique magnétron et leurs contacts ohmiques par diffusion réactive. La cristallisation et la croissance cristalline de Ge1–xSnx ont été étudiées. La cristallisation d'une couche amorphe de Ge1–xSnx déposée à température ambiante conduit à la croissance de films polycristallins. De plus, la compétition entre la séparation de phases Ge/Sn et la croissance Ge1–xSnx empêche la formation de couches de Ge1–xSnx riches en Sn à gros grains sans formation d’îlots de β-Sn en surface. Cependant, une croissance à T = 360 °C d'un film de Ge0.9Sn0.1 pseudo-cohérent fortement relaxé avec une faible concentration d'impuretés (< 2 × 1019 cm–3) et une résistivité électrique de quatre ordres de grandeur plus petite que celle du Ge non dopé a été obtenue. Nous avons montré que la mesure du coefficient de Seebeck pour les couches minces de Ge et de Ge1–xSnx permet à la fois de déterminer le type de dopage, la concentration et la variation des mécanismes de diffusion des porteurs de charges. La réaction à l'état solide de Ni/Ge0.9Sn0.1 montre une croissance séquentielle de deux phases. La phase qui se forme en premier est la phase Ni5(GeSn)3, cette dernière est stable jusqu’à 290°C. Puis, à 275 °C, la phase Ni(GeSn) a été observée. Cette phase est stable jusqu'à 430 °C. Un retard de la formation de la phase Ni(GeSn) par rapport à la phase NiGe a été constaté. De plus, la stabilité thermique de la phase NiGe est fortement dégradée par l’ajout du Sn. La cinétique de croissance des phases ainsi que la cinétique de ségrégation du Sn dans la phase Ni(GeSn) ont été étudiées
The aim of this thesis is to study the fabrication of Ge1–xSnx thin films semiconductors by magnetron sputtering and their ohmic contacts by reactive diffusion. The crystallization and the crystalline growth of Ge1–xSnx were studied. The crystallization of an amorphous Ge1–xSnx layer deposited at room temperature leads to a polycrystalline growth. In addition, the competition between Ge / Sn phase separation and Ge1–xSnx growth prevents the formation of large-grain Sn-rich Ge1–xSnx films without the formation of β-Sn islands on the surface. However, the growth at T = 360 ° C of a highly relaxed pseudo-coherent Ge0.9Sn0.1 film on Si(100) with a low concentration of impurities (< 2 × 1019 cm–3) and an electrical resistivity four orders of magnitude smaller than undoped Ge was obtained. We have shown that the measurement of the Seebeck coefficient for Ge and Ge1–xSnx thin films allows the determination of the type of doping, the concentration of the charge carriers and the variation of the scattering mechanisms. The solid state reaction of Ni /Ge0.9Sn0.1 shows a sequential growth of two phases. The first phase to form was the Ni5(GeSn)3 phase, which is stable up to 290 ° C. Then, at 275 ° C, the Ni(GeSn) phase was observed. This phase is stable up to 430 ° C. A delay in the formation of the Ni(GeSn) phase compared to the NiGe phase was observed. In addition, the thermal stability of the NiGe phase is highly affected by the addition of Sn. The phase growth kinetics as well as the Sn segregation kinetics in the Ni(GeSn) phase were studied

碩士
國立臺灣大學
電子工程學研究所
103
Following the advance of technology, silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are reaching their physical limits. In the recent development, Germanium (Ge) and Germanium-tin (GeSn) alloy have been considered as the possible candidates for the channel materials of MOSFET due to the higher carrier mobility compared to silicon (Si). Nevertheless, many challenges concerning Ge and GeSn still need to overcome. Among these issues, the most difficult is to fabricate a low resistance electrical contact between metal and semiconductor. In this thesis, we investigate the electrical characteristics of metal/n-Ge, Ni/n-GeSn, and Ni/i-GeSn/n-Ge. For the metal/n-Ge system, Fermi level pining has caused a severely influence on the metal/n-Ge interface due to the interface states and the Ge native oxide. Here we show that Ohmic contact of AuSb/n-Ge can be achieved by thermal annealing, and the minimum specific contact resistivity is 0.622 (Ω∙cm^2). The electrical parameters of metal/n-Ge system have been extracted, where the values of Schottky barrier height are in the same order of 0.5 (eV). In order to make a stable metal-oxide-semiconductor (MOS) structure, Al2O3 is placed between Ni/n-Ge with different thickness. From the current-voltage (I-V) and capacitance-voltage (C-V) characteristics, it shows a better trend for Ni/Al2O3/n-Ge with 6.7 and 18.4 nm Al2O3 layer. For the Ni/n-GeSn system, film quality of n-GeSn is measured by different characterization techniques. Ohmic contact to Ni/n-GeSn can be achieved, and the specific contact resistivity is 4.361×10-3 (Ω∙cm^2). We have grown an Al2O3 layer to form Ni/Al2O3/n-GeSn, where the electrical parameters have been extracted by the I-V measurement. In the last section, we discuss the influence of different i-GeSn thickness on the Ni/i-GeSn/n-Ge system. From the I-V measurement, forward current of Ni/i-GeSn/n-Ge is reduced when increasing the thickness of i-GeSn.

碩士
國立臺灣大學
電子工程學研究所
105
It have been passing about fifty years from using Si to be the major semiconductor materials of the metal-oxide-semiconductor field effect transistors (MOSTETs). With the progress of nano-fabrication technology, transistors have been successfully scaled done. But the continued scaling will be the problem due to several physical and technical limitations, results in the progress retardation of efficiency of transistors. We need to find another way to keep the efficiency growing, than using the other materials to substitute Si would be a probable way. Because Ge and Si are both belong to group IV material, it can be easily integrated on tradition fabrication of Si. Moreover, the both electron and hole mobility of Ge are higher than Si. so it is considered the promising candidate to replace Si to be the next-generation semiconductor material. However, there exists a serious fermi-level pinning effect in a metal/n-Ge contact system, resulting in high power consumption because of a higher Schottky barrier height between metal/n-Ge interface. To solve the question of power consumption of Ge-based devices, reducing the Schottky barrier height of metal/n-Ge interface is important. In this thesis, a n-GeSn epitaxial layer was inserted into Ni/n-Ge interface, using the analysis method reported on reference, the electrical characteristics of the Ni/n-GeSn/n-Ge and Ni/n-Ge samples were analyzed. The experimental result shows that the Schottky barrier height of sample with GeSn epitaxial layer is lower than the sample without GeSn layer between Ni/Ge interface, Schottky barrier height reduced from 0.557eV to 0.523eV. However, the series resistance was increased due to the added GeSn layer. We measure the electrical characteristics of our contact sample at lower temperature, the results show that the behavior of Schottky diode deviate from pure thermionic emission theory with decreasing temperature. By searching the related reference we realize the inhomogeneity of Schottky barrier height between metal/semiconductor interface, and found that the interface of Ni/GeSn is more flatter than Ni/Ge. We use the pre-annealing(annealing before the metal contacts deposition) treatment for our N922 sample, which can drive the Sn atoms to the surface of GeSn layer, forming a thin GeSn layer with a Sn composition larger than the underlying GeSn film. It can further decrease the band gap of contact GeSn layer, Schottky barrier height will be reduced.