Auswahl der wissenschaftlichen Literatur zum Thema „Ni(GeSn)“

Ni-based intermetallics are promising materials for forming efficient contacts in GeSn-based Si photonic devices. However, the role that Sn might have during the Ni/GeSn solid-state reaction (SSR) is not fully understood. A comprehensive analysis focused on Sn segregation during the Ni/GeSn SSR was carried out. In situ X-ray diffraction and cross-section transmission electron microscopy measurements coupled with energy-dispersive X-ray spectrometry and electron energy-loss spectroscopy atomic mappings were performed to follow the phase sequence, Sn distribution and segregation. The results showed that, during the SSR, Sn was incorporated into the intermetallic phases. Sn segregation happened first around the grain boundaries (GBs) and then towards the surface. Sn accumulation around GBs hampered atom diffusion, delaying the growth of the Ni(GeSn) phase. Higher thermal budgets will thus be mandatory for formation of contacts in high-Sn-content photonic devices, which could be detrimental for thermal stability.

The prospect of GeSn semiconductors for silicon-integrated infrared optoelectronics brings new challenges related to the metastability of this class of materials. As a matter of fact, maintaining a reduced thermal budget throughout all processing steps of GeSn devices is essential to avoid possible material degradation. This constraint is exacerbated by the need for higher Sn contents exceeding 8 at. % along with an enhanced strain relaxation to achieve efficient mid-infrared devices. Herein, as a low thermal budget solution for post-epitaxy processing, we elucidate the effects of laser thermal annealing (LTA) on strain-relaxed Ge0.89Sn0.11 layers and Ni-Ge0.89Sn0.11 contacts. Key diffusion and recrystallization processes are proposed and discussed in the light of systematic microstructural studies. LTA treatment at a fluence of 0.40 J/cm2 results in a 200–300 nm-thick layer where Sn atoms segregate toward the surface and in the formation of Sn-rich columnar structures in the LTA-affected region. These structures are reminiscent of those observed in the dislocation-assisted pipe-diffusion mechanism, while the buried GeSn layers remain intact. Moreover, by tailoring the LTA fluence, the contact resistance can be reduced without triggering phase separation across the whole GeSn multi-layer stacking. Indeed, a one order of magnitude decrease in the Ni-based specific contact resistance was obtained at the highest LTA fluence, thus confirming the potential of this method for the functionalization of direct bandgap GeSn materials.

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this Abstract, we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys. On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added. The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel. These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics. Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”. References: [1] M. Liu et al. ACS Appl. Nano Mater. 4, 94-101 (2021) [2] S. Wirths et al. Nature Photonics 9, 88-92 (2015) [3] J. Kouvetakis, J. Menendez, A. V. G. Chizmeshya: Annu. Rev. Mater. Res. 36:497-554 (2006) Figure 1

The Ni/Ge0.9Sn0.1 solid-state reaction was monitored by combining in situ X-ray diffraction, in-plane reciprocal space map measurements and in-plane pole figures. A sequential growth was shown, in which the first phase formed was an Ni-rich phase. Then, at 518 K, the mono-stanogermanide phase Ni(Ge0.9Sn0.1) was observed. This phase was stable up to 873 K. Special attention has been given to the nature and the crystallographic orientation of the Ni-rich phase obtained at low temperature. It is demonstrated, with in-plane pole figure measurements and simulation, that it was the ∊-Ni5(Ge0.9Sn0.1)3 metastable phase with a hexagonal structure.