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Zeitschriftenartikel zum Thema „Multigate transistor“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

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1

Lee, Chi-Woo, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain und Jean-Pierre Colinge. „Junctionless multigate field-effect transistor“. Applied Physics Letters 94, Nr. 5 (02.02.2009): 053511. http://dx.doi.org/10.1063/1.3079411.

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2

Martins, Rodrigo, Diana Gaspar, Manuel J. Mendes, Luis Pereira, Jorge Martins, Pydi Bahubalindruni, Pedro Barquinha und Elvira Fortunato. „Papertronics: Multigate paper transistor for multifunction applications“. Applied Materials Today 12 (September 2018): 402–14. http://dx.doi.org/10.1016/j.apmt.2018.07.002.

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3

Jayachandran, Remya, Dhanaraj Jagalchandran und Perinkolam Chidambaram Subramaniam. „Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load“. Facta universitatis - series: Electronics and Energetics 35, Nr. 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.

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Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to 5 V/V is achieved with RL equal to 50 ?, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 k? exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V.

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4

Selvi, K. Kalai, K. S. Dhanalakshmi und Kalaivani Kanagarajan. „Performance Estimation of Recessed Modified Junctionless Multigate Transistor“. Journal of Nano- and Electronic Physics 14, Nr. 1 (2022): 01008–1. http://dx.doi.org/10.21272/jnep.14(1).01008.

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5

Kohda, S., K. Masuda, K. Matsuzawa und Y. Kitano. „A giant chip multigate transistor ROM circuit design“. IEEE Journal of Solid-State Circuits 21, Nr. 5 (Oktober 1986): 713–19. http://dx.doi.org/10.1109/jssc.1986.1052599.

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6

Delgado-Notario, Juan A., Wojciech Knap, Vito Clericò, Juan Salvador-Sánchez, Jaime Calvo-Gallego, Takashi Taniguchi, Kenji Watanabe et al. „Enhanced terahertz detection of multigate graphene nanostructures“. Nanophotonics 11, Nr. 3 (03.01.2022): 519–29. http://dx.doi.org/10.1515/nanoph-2021-0573.

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Abstract Terahertz (THz) waves have revealed a great potential for use in various fields and for a wide range of challenging applications. High-performance detectors are, however, vital for exploitation of THz technology. Graphene plasmonic THz detectors have proven to be promising optoelectronic devices, but improving their performance is still necessary. In this work, an asymmetric-dual-grating-gate graphene-terahertz-field-effect-transistor with a graphite back-gate was fabricated and characterized under illumination of 0.3 THz radiation in the temperature range from 4.5 K up to the room temperature. The device was fabricated as a sub-THz detector using a heterostructure of h-BN/Graphene/h-BN/Graphite to make a transistor with a double asymmetric-grating-top-gate and a continuous graphite back-gate. By biasing the metallic top-gates and the graphite back-gate, abrupt n+n (or p+p) or np (or pn) junctions with different potential barriers are formed along the graphene layer leading to enhancement of the THz rectified signal by about an order of magnitude. The plasmonic rectification for graphene containing np junctions is interpreted as due to the plasmonic electron-hole ratchet mechanism, whereas, for graphene with n+n junctions, rectification is attributed to the differential plasmonic drag effect. This work shows a new way of responsivity enhancement and paves the way towards new record performances of graphene THz nano-photodetectors.

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7

Ono, Y., H. Inokawa und Y. Takahashi. „Binary adders of multigate single-electron transistors: specific design using pass-transistor logic“. IEEE Transactions on Nanotechnology 1, Nr. 2 (Juni 2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.

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8

Wahid, Syamsudin Nur. „SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)“. Jurnal Qua Teknika 7, Nr. 1 (15.03.2017): 53–64. http://dx.doi.org/10.35457/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.

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9

Wahid, Syamsudin Nur. „SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)“. JURNAL QUA TEKNIKA 7, Nr. 1 (15.03.2017): 53–64. http://dx.doi.org/10.30957/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.

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10

Cheng, Hui-Wen, und Yiming Li. „Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor Field-Effect Transistor“. Japanese Journal of Applied Physics 49, Nr. 4 (20.04.2010): 04DC09. http://dx.doi.org/10.1143/jjap.49.04dc09.

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11

Pandian, M. Karthigai, N. B. Balamurugan und A. Pricilla. „Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs“. Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/153157.

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An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.

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12

Park, Jae-Hong, und Chul-Ju Kim. „A Study on the Fabrication of a Multigate/Multichannel Polysilicon Thin Film Transistor“. Japanese Journal of Applied Physics 36, Part 1, No. 3B (30.03.1997): 1428–32. http://dx.doi.org/10.1143/jjap.36.1428.

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13

Othman, Noraini, Mohd Khairuddin Md Arshad, Syarifah Norfaezah Sabki und U. Hashim. „Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review“. Advanced Materials Research 1109 (Juni 2015): 257–61. http://dx.doi.org/10.4028/www.scientific.net/amr.1109.257.

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This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

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14

Bonnaud, Olivier, Peng Zhang, Emmanuel Jacques und Régis Rogel. „(Invited) Vertical Channel Thin Film Transistor: Improvement Approach Similar to Multigate Monolithic CMOS Technology“. ECS Transactions 37, Nr. 1 (16.12.2019): 29–37. http://dx.doi.org/10.1149/1.3600721.

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15

Jana, Biswabandhu, Anindya Jana, Jamuna Kanta Sing und Subir Kumar Sarkar. „Performance of Multigate Single Electron Transistor in Wide Temperature Range and 22 nm Hybrid Technology“. Journal of Nanoelectronics and Optoelectronics 9, Nr. 3 (01.06.2014): 357–62. http://dx.doi.org/10.1166/jno.2014.1595.

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16

Parkula, Vitaliy, Marcello Berto, Chiara Diacci, Bianca Patrahau, Michele Di Lauro, Alessandro Kovtun, Andrea Liscio et al. „Harnessing Selectivity and Sensitivity in Electronic Biosensing: A Novel Lab-on-Chip Multigate Organic Transistor“. Analytical Chemistry 92, Nr. 13 (02.06.2020): 9330–37. http://dx.doi.org/10.1021/acs.analchem.0c01655.

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17

Shao, Feng, Ping Feng, Changjin Wan, Xiang Wan, Yi Yang, Yi Shi und Qing Wan. „Multifunctional Logic Demonstrated in a Flexible Multigate Oxide-Based Electric-Double-Layer Transistor on Paper Substrate“. Advanced Electronic Materials 3, Nr. 3 (10.02.2017): 1600509. http://dx.doi.org/10.1002/aelm.201600509.

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18

Kumar, Ravi, E. Sathish Kumar, S. Vijayalakshmi, Dumpa Prasad, A. Mohamedyaseen, Shruti Bhargava Choubey, N. Arun Vignesh und A. Johnson Santhosh. „Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications“. Journal of Nanomaterials 2023 (24.07.2023): 1–7. http://dx.doi.org/10.1155/2023/6460617.

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Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

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19

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty und Ravikumar Guru Samy. „Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application“. Indonesian Journal of Electrical Engineering and Computer Science 28, Nr. 2 (01.11.2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

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20

Saha, Priyanka, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar und Moath Alathbah. „The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length“. Nanomaterials 13, Nr. 23 (23.11.2023): 3008. http://dx.doi.org/10.3390/nano13233008.

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The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO2) with a stacked gate oxide of 0.5 nm of SiO2 with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si3N4, Al2O3, ZrO2, and HfO2. It was found that the use of strained silicon and replacing only the SiO2 device with the stacked SiO2 and HfO2 device was more beneficial to obtain an optimized device with the least leakage and improved drive currents.

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21

Łukasiak, Lidia, und Andrzej Jakubowski. „History of Semiconductors“. Journal of Telecommunications and Information Technology, Nr. 1 (26.06.2023): 3–9. http://dx.doi.org/10.26636/jtit.2010.1.1015.

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The history of semiconductors is presented beginning with the first documented observation of a semiconductor effect (Faraday), through the development of the first devices (point-contact rectifiers and transistors, early field-effect transistors) and the theory of semiconductors up to the contemporary devices (SOI and multigate devices).

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22

Lee, Chi-Woo, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi und Jean-Pierre Colinge. „Performance estimation of junctionless multigate transistors“. Solid-State Electronics 54, Nr. 2 (Februar 2010): 97–103. http://dx.doi.org/10.1016/j.sse.2009.12.003.

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23

Lee, Chi-Woo, Alexei N. Nazarov, Isabelle Ferain, Nima Dehdashti Akhavan, Ran Yan, Pedram Razavi, Ran Yu, Rodrigo T. Doria und Jean-Pierre Colinge. „Low subthreshold slope in junctionless multigate transistors“. Applied Physics Letters 96, Nr. 10 (08.03.2010): 102106. http://dx.doi.org/10.1063/1.3358131.

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24

Jang, Doyoung, Jae Woo Lee, Chi-Woo Lee, Jean-Pierre Colinge, Laurent Montès, Jung Il Lee, Gyu Tae Kim und Gérard Ghibaudo. „Low-frequency noise in junctionless multigate transistors“. Applied Physics Letters 98, Nr. 13 (28.03.2011): 133502. http://dx.doi.org/10.1063/1.3569724.

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25

Ferain, Isabelle, Cynthia A. Colinge und Jean-Pierre Colinge. „Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors“. Nature 479, Nr. 7373 (November 2011): 310–16. http://dx.doi.org/10.1038/nature10676.

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26

Song, Yi, und Xiuling Li. „Scaling junctionless multigate field-effect transistors by step-doping“. Applied Physics Letters 105, Nr. 22 (Dezember 2014): 223506. http://dx.doi.org/10.1063/1.4902864.

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27

Pan, Andrew, Songtao Chen und Chi On Chui. „Electrostatic Modeling and Insights Regarding Multigate Lateral Tunneling Transistors“. IEEE Transactions on Electron Devices 60, Nr. 9 (September 2013): 2712–20. http://dx.doi.org/10.1109/ted.2013.2272040.

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28

Prasad, Divya, Ahmet Ceyhan, Chenyun Pan und Azad Naeemi. „Adapting Interconnect Technology to Multigate Transistors for Optimum Performance“. IEEE Transactions on Electron Devices 62, Nr. 12 (Dezember 2015): 3938–44. http://dx.doi.org/10.1109/ted.2015.2487888.

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29

Hofheinz, M., X. Jehl, M. Sanquer, R. Cerutti, A. Cros, P. Coronel, H. Brut und T. Skotnicki. „Measurement of Capacitances in Multigate Transistors by Coulomb Blockade Spectroscopy“. IEEE Transactions on Nanotechnology 7, Nr. 1 (Januar 2008): 74–78. http://dx.doi.org/10.1109/tnano.2007.908683.

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30

Aldegunde, Manuel, Antonio Jesus Garcia-Loureiro und Karol Kalna. „3D Finite Element Monte Carlo Simulations of Multigate Nanoscale Transistors“. IEEE Transactions on Electron Devices 60, Nr. 5 (Mai 2013): 1561–67. http://dx.doi.org/10.1109/ted.2013.2253465.

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31

Shin, Mincheol. „Three-dimensional quantum simulation of multigate nanowire field effect transistors“. Mathematics and Computers in Simulation 79, Nr. 4 (Dezember 2008): 1060–70. http://dx.doi.org/10.1016/j.matcom.2007.10.007.

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32

Xie, Dingdong, Jie Jiang, Wennan Hu, Yongli He, Junliang Yang, Jun He, Yongli Gao und Qing Wan. „Coplanar Multigate MoS2 Electric-Double-Layer Transistors for Neuromorphic Visual Recognition“. ACS Applied Materials & Interfaces 10, Nr. 31 (24.07.2018): 25943–48. http://dx.doi.org/10.1021/acsami.8b07234.

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33

Bradford, T., und S. P. McAlister. „The use of multiple-gated MOSFETs in a simple application“. Canadian Journal of Physics 74, S1 (01.12.1996): 182–85. http://dx.doi.org/10.1139/p96-855.

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We describe the design and simulation of the use of neuron MOSFETs in a simple application — that of a parallel-carry adder circuit. The neuron MOSFETs are multigated MOSFETs where the multiple coupling to a MOSFET's gate is made capacitatively. By using such devices a multilevel logic is achieved that allows functions in a circuit to be achieved with fewer transistors than in a conventional CMOS design.

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34

Jung, Doohwan, Huan Zhao und Hua Wang. „A CMOS Highly Linear Doherty Power Amplifier With Multigated Transistors“. IEEE Transactions on Microwave Theory and Techniques 67, Nr. 5 (Mai 2019): 1883–91. http://dx.doi.org/10.1109/tmtt.2019.2899596.

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35

Lou, Haijun, Dan Li, Yan Dong, Xinnan Lin, Shengqi Yang, Jin He und Mansun Chan. „Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors“. Japanese Journal of Applied Physics 52, Nr. 10R (01.10.2013): 104302. http://dx.doi.org/10.7567/jjap.52.104302.

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36

Zhang, Dongli, Mingxiang Wang, Huaisheng Wang und Yilin Yang. „Enhanced Negative Bias Stress Degradation in Multigate Polycrystalline Silicon Thin-Film Transistors“. IEEE Transactions on Electron Devices 64, Nr. 10 (Oktober 2017): 4363–67. http://dx.doi.org/10.1109/ted.2017.2737489.

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37

Takahashi, Yasuo, Akira Fujiwara, Kenji Yamazaki, Hideo Namatsu, Kenji Kurihara und Katsumi Murase. „Multigate single-electron transistors and their application to an exclusive-OR gate“. Applied Physics Letters 76, Nr. 5 (31.01.2000): 637–39. http://dx.doi.org/10.1063/1.125843.

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38

Lou, Haijun, Baili Zhang, Dan Li, Xinnan Lin, Jin He und Mansun Chan. „Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers“. Semiconductor Science and Technology 30, Nr. 1 (05.12.2014): 015008. http://dx.doi.org/10.1088/0268-1242/30/1/015008.

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39

Ranjan, Akhil, Ravikiran Lingaparthi, Nethaji Dharmarasu und K. Radhakrishnan. „Enhanced NO2 Gas Sensing Performance of Multigate Pt/AlGaN/GaN High Electron Mobility Transistors“. Journal of The Electrochemical Society 168, Nr. 4 (01.04.2021): 047502. http://dx.doi.org/10.1149/1945-7111/abed42.

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40

Colinge, Jean-Pierre, Aryan Afzalian, Chi-Woo Lee, Ran Yan und Nima Dehdashti Akhavan. „Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors“. Applied Physics Letters 92, Nr. 13 (31.03.2008): 133511. http://dx.doi.org/10.1063/1.2907330.

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41

Chen, Lun-Chun, Yu-Ru Lin, Yu-Shuo Chang und Yung-Chun Wu. „High-Performance Stacked Double-Layer N-Channel Poly-Si Nanosheet Multigate Thin-Film Transistors“. IEEE Electron Device Letters 38, Nr. 9 (September 2017): 1256–58. http://dx.doi.org/10.1109/led.2017.2725325.

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42

Tae Park, Jong, Jin Young Kim und Jean Pierre Colinge. „Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors“. Applied Physics Letters 100, Nr. 8 (20.02.2012): 083504. http://dx.doi.org/10.1063/1.3688245.

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43

Garcia-Loureiro, Antonio J., Natalia Seoane, Manuel Aldegunde, Raúl Valin, Asen Asenov, Antonio Martinez und Karol Kalna. „Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors“. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, Nr. 6 (Juni 2011): 841–51. http://dx.doi.org/10.1109/tcad.2011.2107990.

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44

Elmessary, Muhammad A., Daniel Nagy, Manuel Aldegunde, Jari Lindberg, Wulf G. Dettmer, Djordje Peric, Antonio J. Garcia-Loureiro und Karol Kalna. „Anisotropic Quantum Corrections for 3-D Finite-Element Monte Carlo Simulations of Nanoscale Multigate Transistors“. IEEE Transactions on Electron Devices 63, Nr. 3 (März 2016): 933–39. http://dx.doi.org/10.1109/ted.2016.2519822.

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45

Chao Lu, A. V. H. Pham, M. Shaw und C. Saint. „Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation“. IEEE Transactions on Microwave Theory and Techniques 55, Nr. 11 (November 2007): 2320–28. http://dx.doi.org/10.1109/tmtt.2007.907734.

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46

Kumar, Nitish, Jialuo Chen, Monodeep Kar, Suresh K. Sitaraman, Saibal Mukhopadhyay und Satish Kumar. „Multigated Carbon Nanotube Field Effect Transistors-Based Physically Unclonable Functions As Security Keys“. IEEE Internet of Things Journal 6, Nr. 1 (Februar 2019): 325–34. http://dx.doi.org/10.1109/jiot.2018.2838580.

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Akhavan, Nima Dehdashti, Aryan Afzalian, Chi-Woo Lee, Ran Yan, Isabelle Ferain, Pedram Razavi, Ran Yu, Giorgos Fagas und Jean-Pierre Colinge. „Effect of intravalley acoustic phonon scattering on quantum transport in multigate silicon nanowire metal-oxide-semiconductor field-effect transistors“. Journal of Applied Physics 108, Nr. 3 (August 2010): 034510. http://dx.doi.org/10.1063/1.3457848.

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