Dissertationen: „Memory transistor“

1

Nominanda, Helinda. „Amorphous silicon thin film transistor as nonvolatile device“. Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.

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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.

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2

Sarkar, Manju. „Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell“. Thesis, Indian Institute of Science, 1995. https://etd.iisc.ac.in/handle/2005/124.

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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.

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3

Sarkar, Manju. „Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell“. Thesis, Indian Institute of Science, 1995. http://hdl.handle.net/2005/124.

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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.

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4

Vagts, Christopher Bryan. „A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory“. Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/24038.

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Approved for public release; distribution is unlimited
This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.

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5

Chaudhary, Mahima. „Colloidal nanocrystals for optoelectronic devices optically controlled at the nanometric scale“. Electronic Thesis or Diss., Université Paris sciences et lettres, 2022. http://www.theses.fr/2022UPSLS072.

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L'optoélectronique est un domaine technologique en croissance rapide qui implique l'utilisation d'appareils électroniques pour générer, détecter et contrôler la lumière. Ces dispositifs peuvent être utilisés dans une variété d'applications telles que les commutateurs photoconducteurs, les systèmes de contrôle d'accès automatique, les télécommunications, la mémoire et bien d'autres. Parce qu'il s'agit d'un domaine si vaste, la variété des dispositifs qui relèvent de l'optoélectronique est vaste. Dans ceThèse de doctorat, Je suis particulièrement intéressédanstraitable en solutionnanomatériaux colloïdaux qui peuventpermettre les interactions lumière-matière.Pour commencer, je me suis d'abord concentré sur la synthèse colloïdale. Latravailler sur cette partie rendementsdeux types différents de nanocristaux colloïdaux :(1)NaYF4 dopé Er3+ nanocristaux, capables d'absorberet up-convertphotons infrarouges à ondes courtes tels que ceux avec= 1,5 µmaux photons visibles ; (2)points quantiques de carbone(CQD)avec dopage à l'azote, capable d'absorber les photons UVet les rétrograder en visiblefluorescence.Dès l'obtention du résultat souhaitécolloïdalnanocristaux aux propriétés optiques adaptées, j'ai ensuiteles a appliqués dansdeux types dedispositifs optoélectroniques : (je) Pcommutateurs thermoconducteurs, qui permettent un contrôle optique de l'amplitude et de la phase des signaux micro-ondes à transmettre. Pour obtenir des commutateurs photoconducteurs micro-ondes fonctionnels à = 1,55µm éclairage,le NaYF4 dopé Er3+ mentionné ci-dessusnanocristaux de conversion ascendanteétaientdéposé directement sur l'arséniure de gallium cultivé à basse température (LT-GaAs)pour réaliser des interrupteurs photoconducteurs. Les propriétés de ces appareils ont ensuite étécaractérisé. Grâce aux propriétés d'upconversion des photons de ces nanocristaux,l'exposition sur les interrupteurs photoconducteurs hybrides unRapport marche/arrêtplus de 2 fois plus élevé en décibels queladispositif de commande sansnanocristals appliqué. (ii) Effet de champmémoires optoélectroniques à base de transistors (FET).Dans ce champ,le support de stockage de chargejoue uncritiquerôleaude la mémoireperformance.Dans cette partie,jeexploite les propriétés uniques de piégeage et de rétention de charge dele susmentionnédes CQD colloïdaux dopés à l'azote (dopé N) pour réaliser des mémoires optoélectroniques fonctionnelles programmables par illumination UV et avec une possibilité d'écriture à plusieurs niveaux. En particulier, une fonction de mémoire de longue durée peut être obtenue grâce aux vastes sites de piégeage de trous fournis par ces CQD et à l'effet de photo-gating qui en résulte.excercised sur le graphène FET, tandis que l'effacement de la mémoire peut être réalisé via une polarisation de grille positive qui fournit suffisamment de porteurs pour la recombinaison de charge.Le résultat de cette thèse de doctoratpoints fortsles contrôles techniques et chimiques pour obtenirhaute performancedispositifs optoélectroniques tels que micro-ondescommutateurs photoconducteurs etmémoires optoélectroniques à base de FET non volatiles tout carbone par manipulation etrécoltelapropriétés optiques et électroniques des nanomatériaux colloïdaux
Optoelectronics is a rapidly growing technology field that involves the use of electronic devices to source, detect, and control light. These devices can be used in a variety of applications such as photoconductive switches, automatic access control systems, telecommunications, memory, and many others. Because this is such a broad field, the variety of devices that fall under optoelectronics is vast. In this, PhD thesis, I am particularily intrested in solution processed colloidal nanomaterials that can allow light-matter intraction. To begin, I first focused on colloidal synthesis. The work on this part yileds two different types of colloidal nanocrystals : (1) Er3+-doped NaYF4 nanocrystals, capable to absorb and up-convert short-wave infrared photons such as those with  = 1.5 µm to visible photons; (2) carbon quantum dots (CQDs) with nitrogen-doping, capable to absorb UV photons and down-shift them into visible fluorescence. Upon obtaining the desired colloidal nanocrystals with suitable optical properties, I subsequently applied them into two type of optoelectronic devices: Photoconductive switches, which allow optical control over the magnitude and phase of microwave signals to be transmitted. To achieve microwave photoconductive switches functional at  = 1.55 µm illumination, the above-mentioned Er3+-doped NaYF4 upconversion nanocrystals were deposited directly onto low-temperature-grown gallium arsenide (LT-GaAs) to achieve photoconductive switches. The properties of these devices were then characterized. Thanks to the photon upconversion properties of these nanocrystals, the hybrid photoconductive switch exhibit an ON/OFF ratio more than 2-fold higher in decibels than the control device without nanocrystals applied. (ii) Field-effect transistor (FET)-based optoelectronic memories. In this field, the charge storage medium plays a critical role to the memory’s performance. In this part, I harnessed the unique charge-trapping and charge-retention properties of the above-mentioned colloidal nitrogen-doped (N-doped) CQDs to achieve functional optoelectronic memories programmable by UV illumination and with a multilevel writing possibility. In particular, a long-lasting memory function can be achieved thanks to the vast hole trapping sites provided by these CQDs and the resultant photo-gating effect excercised on the graphene FET, while memory erasing can be achieved via a positive gate bias that provides sufficient carriers for charge recombination. The result of this PhD thesis highlights the engineering and chemical controls to obtain high-performance optoelectronic devices such as microwave photoconductive switches and all-carbon non-volatile FET-based optoelectronic memories through manipulating and harvesting the optical and electronic properties of colloidal nanomaterials

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Almeida, Luciano Mendes. „Estudo de célula de memória dinâmica de apenas um transistor SOI de óxido enterrado ultrafino“. Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18072013-144946/.

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Neste trabalho foi analisado o comportamento de um transistor UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo n, operando como uma célula de memória 1T-FBRAM (single transistor floating body random access memory). A memória em questão trata-se de uma evolução das memórias 1T1C-DRAM convencionais formada, porém, de apenas um transistor, sendo o próprio transistor o responsável pelo armazenamento da informação por meio do efeito de corpo flutuante. Assim, foram realizadas simulações numéricas bidimensionais, obtendo-se curvas dinâmicas e, a partir destas, foi possível extrair e analisar alguns dos principais parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Foram estudadas as polarizações da célula de memória. Dentre as possíveis maneiras de programação do dado 1 desta tecnologia foram abordadas neste trabalho a programação pelos métodos GIDL (Gate Induced Drain Leakage) e BJT (Bipolar Junction Transistor). Pelo método de escrita por GIDL foi possível operar a célula de memória em alta velocidade sem dissipar potência expressiva. Mostrou-se que esse método é bastante promissor para a tecnologia low-power high-speed. E ainda, obteve-se maior estabilidade na operação de leitura quando esta é polarizada no ponto ZTC (Zero Temperature-Coefficient) devido ao nível de corrente do dado 0 ficar estável mesmo com a variação da temperatura. Pelo método de escrita por BJT, estudou-se a influência das espessuras do filme de silício e também do óxido enterrado, notou-se uma forte dependência da tensão mínima de dreno para a programação do dado 1 em função destas espessuras e também em função da temperatura. Conforme a espessura do filme de silício torna-se mais fina, a tensão de disparo aplicada ao dreno aumenta devido ao maior acoplamento. Porém, observou-se que o nível da tensão de disparo do dreno pode ser modulada através da tensão aplicada ao substrato, tornando possível operar a célula em uma tensão de disparo menor aumentando a vida útil do dispositivo. Quanto à temperatura, com o seu aumento observou-se que a tensão mínima de dreno necessária para disparar a escrita do dado 1 diminuiu favorecendo a programação da célula. Porém o tempo de retenção é prejudicado (torna-se menor) por causa do aumento da corrente de fuga na junção PN. Na análise sobre o impacto que a primeira e a segunda porta causam na margem de sensibilidade de corrente e no tempo de retenção, verificou-se que dependendo da tensão aplicada à porta durante a condição de armazenamento do dado, o tempo de retenção pode ser limitado ou pela geração ou pela recombinação dos portadores (lacunas). Notou-se que há um compromisso entre a obtenção da melhor margem de sensibilidade de corrente e o melhor tempo de retenção. Como o tempo retenção é um parâmetro mais crítico, mais atenção foi dada para a otimização deste. Concluiu-se nesta análise que a melhor polarização para reter o dado por mais tempo é a primeira interface estar em modo acumulação e a segunda em modo depleção. No estudo da polarização de dreno durante a operação de leitura, observou-se que quando aplicado alta tensão de dreno é obtido alta margem de sensibilidade, porém ao mesmo tempo esta polarização prejudica o dado 0 devido ao alto nível de geração de lacunas induzidas pela ionização por impacto, o qual diminui o tempo de retenção e destrói o dado 0 quando operações de múltiplas leituras são realizadas. Já para baixo nível de tensão de dreno durante a leitura notou-se que é possível realizar múltiplas operações de leitura sem perder o dado armazenado e também maior tempo de retenção foi obtido.
In this study was analyzed the behavior of one transistor called UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) working as a 1T-FBRAM (Single Transistor Floating Body Random Access Memory). This memory device is an evolution from conventional memories 1T1C-DRAM, however formed by only one transistor, the device itself is responsible for the storage of the information through the floating body effect. Thus two dimensional simulations were performed, where were obtained dynamic curves, and from these curves it was possible to extract and analyze some of the main parameters, such as, trigger drain voltage, sense margin current, read window, and the retention time, beyond the mechanisms in each state of memory (write, read and hold). Among the possible ways to program the data 1 in this technology were used the methods GIDL (Gate Induced Drain Leakage) and BJT (Bipolar Junction Transistor). By the GIDL method it was possible to operate the memory cell at high speed without spending significant power, showing that this method is very promising for low-power high-speed. Furthermore, greater stability was obtained in read operation when it is biased at point ZTC (zero-Temperature Coefficient) due to the current level of datum \'0\' remain stable even with temperature variation. By the BJT method, it was studied the influence of the silicon film thickness and the buried oxide thickness, and it was noted a strong dependence on minimum drain voltage for programming the data \'1\' as a function of both thicknesses. As the thickness of the silicon film becomes thinner, the trigger drain voltage increases due to stronger coupling. However, it was observed that the level of the trigger drain voltage can be modulated by the substrate bias in this way it is possible to operate the cell with lower voltage avoiding the damage and increasing the lifetime of the device. About the temperature, with its increase it was observed that the minimum drain voltage required to trigger the writing datum \'1\' decreased favoring the programming the cell. However the retention time is harmed (becomes smaller) due to the increment of leakage current in the PN junction. Analyzing the impact of the first and second gate on sense margin current and retention time, it was verified that depending on the voltage applied to the gate during the hold condition, the retention time may be limited by the generation or recombination of the carriers (holes). It was noted that there is a compromise between obtaining the best sense margin current and the best retention time. Since the retention is the most critical parameter, more attention should be given in order to obtain the optimization of this latter. It is concluded in this analysis that the best bias to retain the datum for longer time is the first interface being in accumulation mode and the second in depletion mode. In the study of biasing the drain during the read operation, it has been observed that the use of high drain voltage provides high sense margin, but at the same time, this polarization affect the data \'0\' due to high level of holes generation induced by impact ionization, which shortens the retention time and destroys the data \'0\' in multiple read operations. However, for low drain voltage during read operations it was possible to perform multiple read operations without losing the stored data and also higher retention time was obtained.

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Hilgers, Brandon. „SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies“. DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1423.

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This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates memory for two process technologies (IBM 180nm cmrf7sf and ON Semiconductor 600nm SCMOS) and requires a minimum number of specifications from the user for ease of use, while still offering the option to customize the performance for speed or area of the generated SRAM cell. By automatically creating SRAM arrays, the compiler saves the user time from having to layout and test memory and allows for quick updates and changes to a design. Memory compilers with various features already exist, but they have several disadvantages. Most memory compilers are expensive, usually only generate memory for one process technology, and don’t allow for user-defined custom SRAM cell optimizations. This free design makes it available for students and institutions that would not be able to afford an industry-made compiler. A compiler that offers multiple process technologies allows for more freedom to design in other processes if needed or desired. An attempt was made for this design to be modular for different process technologies so new processes could be added with ease; however, different process technologies have different DRC rules, making that option very difficult to attain. A customizable SRAM cell based on transistor sizing ratios allows for optimized designs in speed, area, or power, and for academic research. Even for an experienced designer, the layout of a single SRAM cell (1 bit) can take an hour. This command-line-based tool can draw a 1Kb SRAM block in seconds and a 1Mb SRAM block in about 15 minutes. In addition, this compiler also adds a manually laid out precharge circuit to each of the SRAM columns for an enhanced read operation by ensuring the bit lines have valid logic output values. Finally, an analysis on SRAM cell stability is done for creating a robust cell as the default design for the compiler. The default cell design is verified for stability during read and write operations, and has an area of 14.067 µm2 for the cmrf7sf process and 246.42 µm2 for the SCMOS process. All factors considered, this SRAM compiler design overcomes several of the drawbacks of other existing memory compilers.

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Sasaki, Kátia Regina Akemi. „Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI“. Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26072013-173443/.

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Neste trabalho foi analisado o comportamento de um transistor UTBOX FD SOI MOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo N, em sua aplicação como uma célula de memória 1T-DRAM, dando ênfase no estudo das polarizações e propostas de melhorias de desempenho para viabilizar sua aplicação como uma célula de memória. Dessa forma, foram analisados os efeitos das diferentes polarizações (de porta, de dreno e de substrato), bem como a influência da concentração de uma região de extensão de fonte e dreno menos dopada (LDD Lightly Doped Drain), nos principais parâmetros da referida memória. Assim, foram analisados alguns parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Por fim, foram propostas algumas melhorias de desempenho para o tempo de retenção. Foi observado que o aumento da temperatura facilita a escrita na memória diminuindo a mínima tensão no dreno (até 72% para temperatura de 25 a 300°C, ficando limitada a 0,8V) e o tempo necessários para a escrita (até 95%), porém reduz a margem de sensibilidade (até 90%) e o tempo de retenção (até 2 ordens de grandeza). Verificou-se também que, apesar da menor espessura do filme de silício e do óxido enterrado aumentar a tensão no dreno necessária para ativar o efeito BJT (efeito bipolar parasitário), um potencial positivo no substrato pode reduzir este requisito (61% para tensão de substrato variando de 0 V até 1,5 V). Além disso, foi visto que pode haver uma geração ou uma recombinação de portadores, dependendo da tensão na porta durante o repouso, degradando o bit \'0\' ou \'1\'. Já a otimização da polarização de substrato demonstrou ser limitada pelo compromisso de ser alta o suficiente para ativar o efeito de corpo flutuante durante a escrita, sem prejudicar a leitura do \'0\'. Os resultados também demonstraram que a margem de sensibilidade é menos dependente da tensão do substrato que o tempo de retenção, levando a este último parâmetro ser considerado mais crítico. Com relação à leitura, maiores tensões no dreno resultaram na presença do efeito BJT também neste estado, aumentando a margem de sensibilidade (60%) e diminuindo o tempo de retenção (66%) e o número de leituras possíveis sem atualização do dado (de mais de 30 para 22 leituras). No tópico da concentração das extensões de fonte e dreno, os dispositivos sem extensão de fonte e dreno apresentaram uma taxa de geração de lacunas menor (aproximadamente 12 ordens de grandeza), levando a um tempo de retenção muito maior (aproximadamente 3 ordens de grandeza) quando comparado ao dispositivo referência. Em seu estudo no escalamento, verificou-se uma diminuição no tempo de retenção para canais mais curtos (quase 2 ordens de grandeza), demonstrando ser um fator limitante para as futuras gerações das memórias 1T-DRAM. Apesar disso, quando comparados com os dispositivos convencionais com extensão de fonte e dreno (com extensão), seu tempo de retenção aumentou (quase 1 ordem de grandeza), permitindo a utilização de menores comprimentos de canal (30nm contra 50nm do dispositivo com extensão) e polarizações de substrato menores. Outra proposta de melhoria no tempo de retenção apresentada foi a utilização da polarização de substrato pulsada apenas durante a escrita do nível \'1\', o que resultou no aumento do tempo de retenção em 17%. Finalmente, estudou-se também a variação da banda proibida motivado pela utilização de novos materiais para o filme semicondutor. Observou-se que o aumento da banda proibida aumentou o tempo de retenção em até 5 ordens de grandeza, possibilitando retenções mais próximas das DRAMs convencionais atuais.
In this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor), as a 1T-DRAM (Single Transistor Dynamic Random Access Memory) cell, focusing on the best biases and other proposals for enabling the 1T-DRAM applications. Therefore, it was analyzed the effects of different biases (gate, drain and substrate), as well as the influence of the concentration of a less doped source/drain extension region on the main parameters of this kind of memory. Thus, it was analyzed some of the main memory parameters such as the trigger drain voltage, the sense margin, the read window and the retention time, as well as the mechanisms operating in each state of the memory (writing, reading and holding). Finally, it were proposed some performance enhancements for the retention time of this kind of memory. It was observed that the increase in temperature facilitates the memory write decreasing the minimum drain bias and time required for writing, but reduces the sense margin. It was also verified that, despite the thinner silicon film and buried oxide increase the drain voltage required to activate the BJT effect (parasitic bipolar effect), a positive potential on the substrate may reduce this requirement (61% for back gate bias varying from 0 to 1,5V), being an alternative for solving the problem and allowing the use of smaller devices as a memory cell. Furthermore, it was seen that there can be a carriers generation or recombination, depending on the gate voltage during the holding state, degrading the bit \'0\' or \'1\'. Moreover, the optimization of substrate bias proved to be limited by enabling the writing state, without degrading the reading of \'0\'. The results also demonstrated the sense margin is less dependent on the substrate voltage than the retention time, therefore, the retention time was considered as a more critical parameter. With respect to the reading state, there was the presence of BJT effect also in this state, increasing the margin of sensitivity (60%) and reducing the retention time (66%) and the number of possible readings without updating the data (over 30 for 22 readings) in cases of higher drain bias. On the topic of the concentration of the source and drain extensions, the devices with source and drain extensions presented a generation rate lower (about 12 orders of magnitude), resulting in a retention time far longer than the reference one (about 3 orders of magnitude). About its downscaling, the retention time decreased for shorter channel lengths (almost 2 orders of magnitude), which is a limiting factor for 1T-DRAM future generations. Nevertheless, when it was compared to the conventional devices with source and drain extensions, theirs retention time increased (almost 1 order of magnitude), allowing the use of shorter channel lengths (30nm against 50nm of reference device) and lower back gate biases. Another proposal presented to improve the retention time was the pulsed back gate only during the writing \'1\' state, which resulted in an increase on the retention time by 17%. Finally, we also studied the band gap influence motivated by the use of new materials for the semiconductor film. It was observed that higher band gaps increase the retention time by up to 5 orders of magnitude, allowing a retention time closer to the current conventional DRAMs.

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Boubaker, Aimen. „Modelisation des composants mono-electroniques : Single-Electron Transistor et Single-Electron Memory“. Lyon, INSA, 2010. http://theses.insa-lyon.fr/publication/2010ISAL0046/these.pdf.

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[Ce travail concerne le développement des mémoires à un électron de type SET/SEM pour les technologies CMOS silicium. Le premier chapitre du manuscrit est consacré à la présentation d' une revue bibliographique des phénomènes apparaissant dans les nanodispositifs électroniques (effets quantiques, blocage de Coulomb) de type transistors et mémoires à un électron. Dans le deuxième chapitre, nous nous intéressons aux diffë rents modèles électriques proposés pour les SETs. Grâce à des simulations numériques développées sous SPICE, nous avons approfondi notre compréhension du fonctionnement des SETs dans quelques exemples d'applications. Il s' agissait notamment de comparer les modèles dans le cas de SETs métalliques et semiconducteurs. Le troisième chapitre concerne la définition de l' architecture mémoire à un électron de type SET/SEM que nous proposons d'étudier. Après avoir présenté le concept de la structure SET/SEM, et expliqué le principe de fonctionnement dans les modes de lecture et de programmation, nous détaillons les résultats de simulations des caractéristiques du dispositif proposé. Après avoir opté pour une mémoire utilisant deux îlots métalliques pour les opérations de stockage de charge et de lecture respectivement, nous avons utilisé le logiciel SIMON afi n de proposer une architecture optimisée. Les travaux de simulations de l'architecture SET/SEM nous ont permis de calculer les éléments de circuits du modèle électrique équivalent permettant un fonctionnement optimal de la mémoire. Un aspect fondamental pour cette étude était en effet d'optimiser le décalage OVg des caractéristiques Ig-Vg observé lors de l' injection d'électrons uniques dans le point mémoire. Finalement, nous avons démontré qu'un décalage de quelques dizaines de m V/ électron était possible dans notre architecture. Dans le quatrième chapitre, nous présentons une étude détaillée des mécanismes de transport dans le bloc de mémorisation. Un modèle électrique de la cinétique de charge et décharge a été utilisé en prenant en compte l'effet du champ électrique. Finalement, nous avons étudié l' influence des paramètres technologiques comme les épaisseurs d'oxyde et la surface de l' îlot de mémorisation afin de proposer un dimensionnement de l'architecture SET/SEM. Ces simulations faites dans un premier temps à partir du système Ti / Tiüx utilisé dans la technologie nanodamascène développée à l'Université de Sherbrooke, ont pu dans un second temps être étendues à d'autres systèmes de matériaux afin de pro poser les matériaux présentant les meilleurs temps de rétention théoriques. Après avoir comparé les simulations d'îlots métalliques en Pt, Au, TiSi2, NiSi et Ti, nos travaux montrent que titane associé au Ti02 présente les meilleurs temps de rétention à 85% y compris à des températures aussi élevées que 430K qui représente actuellement la température maximale de fonctionnement des SETs réalisés à l'uni versité de Sherbrooke. ]
[This work concerns the study of SET/SEM single electron memories for CMOS technologies. The first part presents a review of quantum and Coulomb blockade effects in electronic nanodevices. In a second part, we present the main electrical models proposed for single electron devices. A comparison between semiconductor-based and metall ic-based single electron transistors. The third part of the thesis presents the SET/SEM memory structure on the basis of SIMON simulations. The device consists on the coupling of a metallic SET operating at high temperature with a metalli c memory node. Finnaly, an optimized memory device has been proposed in the Ti/Tiüx system. The proposed memory is able to write and erase a discrete number of electrons varying from 0 to 7 at room temperature. This opens the possibility of multilevel memory circuits. Finally, we have studied the data retenti on performances of the memory in the last part of this thesis. After the first simulations with the Ti/Tiüx materials system, we have simulated various metallic systems such as Pt, Au, TiSi2, and NiSi. We have shown that finally, the Ti/Ti02 systems gives the best data retention performances even at high temperatures, up to 430K. . ]

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CASULA, SILVIA. „Non-volatile organic memory devices: from design to applications“. Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266601.

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The research activity described in the attached dissertation focused on the development, fabrication and characterization of new non-volatile memory elements based on organic technology. During the last few decades, organic materials based devices have attracted considerable interest due to their great potential for future electronic systems. Low fabrication costs, high mechanical flexibility and versatility of the chemical structure, good scalability and easy processing are the unique advantages of organic electronics. As memory devices are essential elements of any kind of electronic system, the development of organic memory devices is fundamental in order to extend the application of organic materials to different electronic circuits. Research on organic electronic memories is currently at a rapid growth stage, since it is recognized that they may be an alternative or supplementary to the conventional memory technologies. Despite considerable progress in the advancement of novel memory technologies in recent years, some challenging tasks still need to be resolved. The Ph.D. research activity of this thesis is related to the still -opened challenges in the organic memories technologies. In particular, it focused mainly on the study, development, fabrication and characterization of new non-volatile organic memory elements based on resistive switching. The activity has been carried out in the frame of the European project “HYbrid organic/inorganic Memory Elements for integration of electronic and photonic Circuitry” (HYMEC), which involved the University of Cagliari during the last three years. The project goal was to realize new hybrid inorganic/organic resistive memory devices with functionality far beyond the state of the art. A complementary activity on transistor-based organic memory devices has been also carried out and described in this thesis. As regards resistive memory devices, the research activity included design, fabrication and testing of a novel non-volatile memory device based on the combination of an air-stable organic semiconductor and metal nanoparticles. This topic required the development of technology and procedures for easy and reliable production of devices as well as the definition of measurement protocols. The proposed structure was thoroughly characterized by morphological techniques, which allowed to interpret the resistive switching mechanisms in terms of formation and rupture of metallic filaments inside the organic layer assisted by the metal NPs. The obtained performances are the best reported so far in literature, and, to our knowledge, the statistics analysis is the largest ever reported for organic-based resistive memories. The developed technology was then successfully applied on flexible plastic substrates. The definition of technological processes for the reliable fabrication of high performance printed organic memory devices was also carried out: this work clearly demonstrates the real possibility of fabricating high performance printed memory elements. A significant effort was also devoted to the development of basic memory/sensor systems entirely fabricated on plastic substrates. The suitability of organic non-volatile memory devices for the detection and the storage of external parameters was demonstrated. The results definitely demonstrated the feasibility of the proposed technology for the fabrication of systems including organic memories for their final application in different industrial processes, including e-textile and smart packaging. As regards transistor memory devices, highly flexible Organic Field-Effect Transistor (OFET)-based memory elements with excellent mechanical stability and high retention time were developed. As main innovation with respect to the state of the art, low voltage operation of the OFET-based memory was investigated. Such an activity was also related to the development of reliable measurement procedures

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Couto, Andre Luis do. „Caracterização de memorias analogicas implementadas com transistores MOS floating gate“. [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.

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Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005
Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área
Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

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Marron, Dominique. „Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche“. Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.

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Afin d'accroitre la complexite des composants electroniques, leur architecture utilise des elements redondants. On pallie ainsi les problemes de rendements. Cette these traite d'un element de reconfiguration, le transistor a grille flottante, et de sa programmation par un faisceau d'electrons. Les conditions de programmation, la tenue dans le temps de la charge deposee ainsi que les problemes pratiques rencontres sont etudies. Ce transistor est ensuite utilise dans la conception d'une memoire sram de 4. 5 mbit reconfigurable integree sur une tranche d=100. Les contraintes pratiques et l'architecture sont exposees de meme que la partie realisation et test. Cette etude est en fait une etude de faisabilite pour des circuits de type wsi industriels

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Kareer, Shobhit. „Fabrication of Carbon Nanotube Field Effect Transistor Using Dielectrophoresis and Its Application as Static Random Access Memory Bit Cell“. Thesis, Université d'Ottawa / University of Ottawa, 2019. http://hdl.handle.net/10393/39983.

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The aim of the thesis is to fabricate Schottky contact carbon nanotube field effect transistor (CNFET) using the dielectrophoresis (DEP) to resolve the alignment issue and show its transistor behaviour. The work presented is a combination of fabrication and simulation of CNFET. Fabrication of the device electrode had been done using the electron beam lithography to achieve a channel length of 150nm and analysis was done on an optical microscope, SEM, AFM and Raman spectroscopy. Second half of the thesis provides a solution to “bottleneck communication” between microprocessor and memory to increase the computation for applications like AI, IoT etc and 3D monolithic memories. As a solution, we propose a novel CNFET based processing in-memory architecture using a novel CNFET dual port single-ended SRAM bit cell. The combination of the CNFET and processing in-memory can be a new phase for memory and computation.

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Candelier, Philippe. „Contribution à l'amélioration de la fiabilité des mémoires non volatiles de type flash EEPROM“. Université Joseph Fourier (Grenoble ; 1971-2015), 1997. http://www.theses.fr/1997GRE10245.

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L'augmentation continue de la densite d'integration des memoires non-volatiles de type flash eeprom passe par la comprehension des mecanismes de degradation intervenant dans le cadre du fonctionnement de ces memoires. Nous avons pu correler les degradations observees sur des dispositifs elementaires (transistors et capacites) aux derives des caracteristiques de la cellule flash. Cette etude demontre que de nouveaux modes de fonctionnement devront etre envisages. Le mode d'effacement par la source, habituellement utilise, pose des problemes d'optimisation technologique pour les cellules de faible longueur de grille (generation de trous chauds difficile a controler). Il devra vraisemblablement etre remplace par l'effacement fn qui est plus fiable pour les criteres d'endurance et de retention apres endurance. Parmi les degradations observees, le probleme principal est l'augmentation de la perte de charge avec l'amincissement des dielectriques et avec la degradation de l'oxyde de grille lors des cycles ecriture/effacement. Face au premier probleme, la mise en place d'une fonction de rafraichissement periodique semble necessaire. Face au second probleme, l'effacement fn a ete optimise en minimisant le champ electrique dans l'oxyde de grille par l'utilisation d'impulsions trapezoidales. Des progres technologiques importants (dielectriques interpolysilicium deposes, isolation laterale de type box) ont ensuite ete introduits dans le procede de fabrication afin permettre une integration plus poussee. La validation de ces evolutions technologiques ouvre les portes de la generation de cellules flash 0. 25 m. Finalement, face au probleme d'augmentation de la densite d'integration, la programmation multi-niveaux est une solution simple dont la fiabilite a ete amelioree grace a la realisation d'un systeme de programmation convergente. La faisabilite d'un doublement de capacite memoire a alors ete demontree.

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Gomes, José Miguel Alves Faria. „Characterization and modelling of long-term memory effects in GaN HEMTs“. Master's thesis, Universidade de Aveiro, 2016. http://hdl.handle.net/10773/18456.

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Mestrado em Engenharia Eletrónica e de Telecomunicações
Gallium nitride (GaN) high electron mobility transistor (HEMT) technology has been revolutionizing the RF power amplifier (PA) market. Its potential, versus existing technologies, such as Silicon (Si) Laterally-Diffused MOS(LDMOS), is yet to be completely explored. However, the lack of good characterization and modelling of charge carrier trapping related phenomena has been hampering PA designers from extracting this technology’s promised performance. Hence, GaN HEMT trapping has been given a great amount of attention by the scientific and industrial worlds. This is mainly because the overall linearity of the PA built with this technology is affected, to a great extent, by the trapping state dependence on the device’s drain peak voltage. Circuit computer-aided design (CAD) tools are almost ubiquitous at research and development labs. However, these tools rely, not only on their simulation algorithms, but also on their built-in device models. This makes the development of accurate models a fundamental task. This work reports a multi-bias small-signal equivalent circuit (SSEC) model extraction procedure of a 3.3 W GaN HEMT from pulsed S-parameters as well as the development of a pulsed DC I-V measurement system and its use in the characterization of trapping-effects. This system, which is based on two pulser circuits, designed specifically for gate and drain pulsed measurements, was then automated through a MATLAB/PC controller. The pulser circuits allowed pulse widths on the microsecond scale at very low duty cycles as well as high peak voltages - close to 50 V - and currents - up to 4 A. With the developed system, isothermal standard pulsed I-V curves, as well as trapping-state dependent, isodynamic, pulsed I-V curves were obtained from a 15 W GaN HEMT device. In order to obtain the latter, the so-called double-pulse measurement technique was used. The expected asymmetric time constants associated with drain-lag were clearly observed: on the ns scale for the trapping and on the hundreds of milliseconds for the de-trapping. The predicted relatively reduced impact of gate-lag phenomena in more recent GaN HEMT technologies was also verified.
A tecnologia GaN HEMT tem revolucionado o mercado dos amplificadores de potência para RF. O seu potencial, comparado com tecnologias anteriores, como a Si LDMOS, continua por ser completamente explorado. Contudo, a falta de uma boa caracterização e modelação dos efeitos de memória lenta causados pelo armadilhamento de cargas têm impedido o total aproveitamento desta tecnologia no desenho de amplificadores de potência. Consequentemente, estes fenómenos de armadilhamento têm sido alvo de um amplo estudo tanto a nível científico como industrial. Isto deve-se, sobretudo, porque a linearidade dos amplificadores baseados nesta tecnologia é bastante afectada pelo estado de armadilhamento de cargas no dispositivo, que, por sua vez, é definido pela tensão de pico na saída, drain, do transístor. As ferramentas de desenho de circuitos auxiliado por computador estão presentes na maioria dos laboratórios de investigação. No entanto, estas dependem não só dos seus algoritmos de simulação mas também, em larga medida, dos modelos nelas utilizados, tornando fundamental o desenvolvimento de melhores modelos. O presente documento descreve a extracção de um modelo de circuito equivalente de pequeno signal dependente da polarização, de um transístor GaN HEMT de 3.3 W, a partir de medidas de parâmetros-S pulsadas, assim como a construcção de um sistema de medidas pulsadas DC I-V e a utilização deste último na caracterização de efeitos de armadilhamento. O sistema desenvolvido, baseado em dois circuitos pulsadores desenhados para medidas pulsadas quer no terminal de entrada, gate, quer no de saída, drain, foi automatizado através do software MATLAB instalado num PC. Os circuitos pulsadores permitem larguras de pulso na escala dos microsegundos com duty-cycles tão pequenos como 0.001%, assim como, elevadas tensões de saída - perto de 50 V - e correntes - pelo menos até 4 A. Com o sistema desenvolvido, obtiveram-se curvas I-V iso-térmicas e também curvas I-V iso-dinâmicas, dependentes do estado de armadilhamento, de um transístor GaN HEMT de 15 W. De modo a obter as últimas, foram utilizadas medidas de duplo-pulso. A assimetria esperada nas constantes de tempo associadas com o drain-lag foram claramente observadas: na escala dos ns para o armadilhamento e das centenas de milisegundos para o desarmadilhamento. Tal como a literatura prevê para tecnologias mais recentes de GaN HEMTs, o impacto dos fenónemos de gate-lag que foi observado revelou-se bastante reduzido.

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Yurchuk, Ekaterina. „Electrical Characterisation of Ferroelectric Field Effect Transistors based on Ferroelectric HfO2 Thin Films“. Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-172000.

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Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

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Carlson, Ingvar. „Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors“. Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2286.

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This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre.

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Hesse, Marjorie. „Développement de nouvelles architectures mémoires non-volatiles embarquées pour les plateformes technologiques avancées 40nm et 28nm“. Thesis, Université Côte d'Azur (ComUE), 2019. http://www.theses.fr/2019AZUR4069.

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Les applications avancées à base de microcontrôleurs couvrent de multiples domaines. L’accroissement du champ d’application des microcontrôleurs s’accompagne d’une augmentation de la puissance consommée qui limite l’autonomie des systèmes nomades. L’avancée technologique vers des plateformes CMOS à ultra basse consommation est un défi majeur pour répondre aux exigences des marchés nomades et autres applications émergentes avec mémoires non volatiles embarquées. Ces mémoires sont en constante évolution, notamment par la diminution de leur dimension vers des nœuds technologiques avancés comme le 40nm et le 28nm. Dans cette thèse, nous présenterons une mémoire non volatile innovante appelée eSTM (embedded Select Trench Memory). Cette cellule possède un transistor mémoire et un transistor de sélection vertical. Ce dernier est un atout essentiel pour l’optimisation de la consommation de la cellule. Son architecture permet d’obtenir une mémoire du type 2T en minimisant la surface occupée. L’objectif de cette thèse est d’étudier cette cellule développée sur une plateforme technologique 40nm et d’identifier les différentes problématiques liées à la miniaturisation vers le nœud technologique 28nm. A travers la modélisation, la caractérisation électrique et les calculs théoriques, nous verrons qu’il est possible de trouver des solutions d’intégration notamment avec l’adaptation des divers implants et des dimensionnels du transistor mémoire. La réduction des paramètres dimensionnels peut engendrer de nouvelles architectures, comme la cellule à recouvrement. Cette optimisation de la cellule eSTM fera également l’objet de ces travaux de thèse
Advanced applications based on microcontrollers cover multiple domains. The increase of the field of microcontrollers application is accompanied by a growth of the power consumption. This is a limit of the autonomy of nomadic systems. The technological advance towards ultra-low-consumption CMOS platforms is a major challenge to the requirements of mobile markets and other emerging applications with embedded non-volatile memories. These memories are constantly evolving, particularly by the size shrinking to advanced technological nodes such as 40nm and 28nm. In this thesis, we will present an innovative non-volatile memory called eSTM (embedded Select Trench Memory). This cell possesses a memory transistor and a vertical select transistor. The select transistor is essential to the optimization of the cell consumption. This memory constitutes a 2T architecture with a reduction of area. The objective of this thesis is to study this cell developed on a 40nm technological platform. We will identify the various problems related to miniaturization towards the 28nm technological node. Through the modelling, the electrical characterization and the theoretical calculations, we will see that it is possible to find solutions as the adaptation of the various implants and the dimensions of the memory transistor. This optimization of the eSTM cell will also be the subject of this thesis work

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Becker, Thales Exenberger. „Caracterização elétrica temporal de transistores de filmes finos de nanopartículas de óxido de zinco“. reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179538.

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Neste trabalho, são discutidas as características de transistores de filmes finos (TFTs) nos quais nanopartículas de óxido de zinco (ZnO) são empregadas como material ativo na camada semicondutora. O crescimento contínuo do interesse por este componente está associado à busca pelo desenvolvimento da tecnologia de dispositivos eletrônicos flexíveis, transparentes e de baixo custo. TFTs integrados com nanopartículas de ZnO são apresentados, e uma extensa rotina de caracterização elétrica transiente é realizada para avaliar como estes dispositivos se comportam e degradam ao longo do tempo. Foram medidas, ao total, 80 amostras de transistores integrados em duas configurações distintas: inverted staggered e inverted coplanar. A partir das medidas analisadas foram identificados dois grupos de comportamentos elétricos dominantes, os quais foram classificados em: efeitos abruptos e efeitos de memória. A partir dos dados coletados, foram formuladas hipóteses para modelar o comportamento típico observado. Para tanto, utiliza-se dos mecanismos de atividade de traps, de interação da camada semicondutora com o meio ambiente, de polarização de dipolos e difusão de cargas móveis no dielétrico, de formação de caminhos percolados paralelos pelas nanopartículas e de difusão de vacâncias de oxigênio e íons metálicos que podem estar associados ao comportamento elétrico observado.
In this work, the characteristics of thin-film transistors (TFTs) employing nanoparticulated zinc oxide (ZnO) as the active semiconductor channel layer are discussed. The growing interest in this component is associated to the development of low-cost, flexible and transparent electronic devices. The TFTs integrated with ZnO nanoparticles are presented and an extensive transient electrical characterization campaign was performed in order to evaluate how these devices behave and degrade over time. The measurement was performed for 80 samples of two different integration setups: inverted staggered and inverted coplanar. In the performed tests two main disturbances were identified, which were classified as abrupt and memory effects. From the collected data, hypothesis to model the observed typical behavior are formulated. Trapping activity, ambient interaction, dielectric dipoles, mobile charges, formed parallel-paths, oxygen vacancies and metallic ions diffusion are mechanisms that may be associated to the observed behavior.

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Marzaki, Abderrezak. „Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS“. Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4768.

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La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de technologie existante, la technologie CMOS est la plus utilisée. Dans le cadre du développement de la technologie CMOS 90nm à double niveau de poly, des recherches sur l’introduction de techniques innovantes de procédé de fabrication et d’une nouvelle architecture de transistor MOS à tension de seuil ajustable ont été menées dans le but d’améliorer les performances des ICs. Une première étude sur l’implémentation des effets de pointe dans les ICs, en particulier pour les mémoires non volatiles est entreprise. Un nouveau procédé de fabrication permettant d’obtenir des pointes dans un matériau est proposé. Il est démontré le gain en courant tunnel obtenu sur une structure pointue par rapport à une structure plane. Une seconde étude est orientée sur le développement d’une nouvelle technique de « patterning ». Les techniques de « patterning » permettent de réduire les dimensions de la photolithographie sans utiliser de masque ayant des dimensions agressives. Les avantages de cette nouvelle technique aux niveaux de sa mise en œuvre et de la suppression des problèmes d’alignement sont présentés. Une dernière étude sur le développement d’un transistor à tension de seuil ajustable est développée. Il est démontré l’avantage de ce composant par rapport aux autres composants à tension de seuil ajustable. La réalisation du modèle et des premières simulations électriques de circuit élémentaire à base de se composant sont présentés. L’amélioration de certaines performances des circuits élémentaire est démontrée
The component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first electrical simulations of elementary circuits composed with this new component are presented. The performance improvement of some elementary circuits is demonstrated

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Liao, Si-yu. „Caractérisation électrique et électro-optique de transistor à base de nanotube de carbone en vue de leur modélisation compacte“. Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14254/document.

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Afin de permettre de développer un modèle de mémoire non-volatile basée sur le transistor à nanotube de carbone à commande optique qui est utilisée dans des circuits électroniques neuromorphiques, il est nécessaire de comprendre les physiques électroniques et optoélectroniques des nanotubes de carbone, en particulier l’origine de l'effet mémoire que présente ces transistors. C’est dans ce contexte général que cette thèse s'intègre. Le travail est mené sur trois plans :• Caractériser électriquement et optoélectroniquement des structures de test des CNTFETs et des OG-CNTFETs.• Développer un modèle compact pour les contacts Schottky dans les transistors à nanotube de carbone de la façon auto-cohérente basé sur le diamètre et la nature du métal d’électrode en utilisant la méthode de la barrière effective avec les paramètres nécessaires calibrés.• Modéliser l'OG-CNTFET selon les régimes de fonctionnement, lecture, écriture, effacement ou programmation pour application à une mémoire non-volatile en intégrant le mécanisme de piégeage et dépiégeage à l’interface polymère/oxyde
This PhD thesis presents a computationally efficient physics-based compact model for optically-gated carbon nanotube field effect transistors (OG-CNTFETs), especially in the non-volatile memory application. This model includes memory operations such as “read”, “write”, “erase” or “program”, and “reset” which are modeled using trapping and detrapping mechanisms at the polymer/oxide interface. The relaxation of the memory state is taken into account. Furthermore, the self-consistent modeling of Schottky barriers at contacts between the carbon nanotube channel and metal electrodes is integrated in this model applying the effective Schottky barrier method. The Schottky contact model can be included in CNTFET based devices for a typical biasing range of carbon nanotube transistors. This compact model is validated by the good agreement between simulation results and experimental data (I-V characteristics). In the non-volatile memory application, this model can fully reproduce device behaviors in transient simulations. A prediction study of the key technological parameter, the CNT diameter variety is established to expect its impact on the transistor performance, and more importantly, on the memory operation. In the other hand, this thesis presents a preliminary electric characterization (I-V) of CNTFETs and OG-CNTFETs for the device modeling database. A preliminary optoelectronic characterization method is proposed

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Guenery, Pierre-Vincent. „Nanostructures d’oxyde d’indium pour les mémoires résistives RRAM intégrées en CMOS Back-End-Of-Line“. Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI114.

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Les mémoires informatiques actuelles qui ne sont que l'extrême miniaturisation de la technologie développée dans les années 1960, atteignent des limites technologiques difficilement surmontables techniquement et très couteuses. Les mémoires doivent donc se réinventer par une modification profonde de leur forme, comme le développement de structures en 3 dimensions par exemple, ou par l'utilisation de technologies innovantes. C'est un phénomène récent dans le domaine des mémoires qui nous a intéressé au cours de cette thèse. Il consiste à maîtriser électriquement et de manière réversible la résistivité d'une structure pour coder de l'information de manière pérenne, d'où son nom de mémoires résistive non volatile. Un grand nombre de recherches sont menées pour comprendre et maîtriser cette technologie dont le principal défaut actuel est son manque de reproductibilité. Nous proposons une approche originale consistant à l'intégration de nanoparticules d'oxyde d'indium dans la structure d'une mémoire résistive qui est directement compatible avec les puces déjà existantes. L’intégration de particules a pour but d'aider à rendre ces mémoires plus homogènes par un contrôle du comportement électrique de la structure. L'étude menée porte dans un premier temps sur les défis liés à la fabrication de la mémoire et en particulier sur le dépôt de nanoparticules. Pour avoir un effet bénéfique, la fabrication de celles-ci doit être parfaitement maîtrisée. Nous détaillons ensuite à la caractérisation électrique des mémoires et à la compréhension des phénomènes qui sont à l’origine du changement de résistivité des matériaux afin de tenter de mieux les contrôler
The current computer memories are nothing more than the extreme miniaturization of the technology developed in the 1960s. These memories reached technological limits that are technically difficult and very costly to overcome. Memories must therefore be reinvented by a profound change in their shape, such as the development of three-dimensional structures for example, or by the use of innovative technologies. A new physical phenomenon in the field of memories interested us during this thesis. It consists in an electrically and reversibly control of the resistivity of a structure that can reach at least two level to code the information in a durable way. These memories are called non-volatile resistive memories. A lot of research is being carried out to understand and control this technology. The main current defect of this emerging technology is its lack of reproducibility. We propose an original approach consisting in the integration of indium oxide nanoparticles into the structure of a resistive memory that is directly compatible with existing chips. The purpose of particle integration is to increase the homogeneity of these memories by controlling the electrical behaviour of the structure. The study initially focused on the challenges of memory manufacturing and in particular on the deposition of nanoparticles. To have a beneficial effect, the manufacture of these products must be perfectly controlled. The study then details the electrical characterization of the memories. We discuss about the phenomena that are at the origin of the change in resistivity in order to try to better control them

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Najari, Montassar. „Modélisation compacte des transistors à nanotube de carbone à contacts Schottky et application aux circuits numériques“. Phd thesis, Université Sciences et Technologies - Bordeaux I, 2010. http://tel.archives-ouvertes.fr/tel-00560346.

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Afin de permettre le développement de modèles manipulables par les concepteurs, il est nécessaire de pouvoir comprendre le fonctionnement des nanotubes, en particulier le transport des électrons et leurs propriétés électroniques. C'est dans ce contexte général que cette thèse s'intègre. Le travail a été mené sur quatre plans : • Développement de modèles permettant la description des phénomènes physiques importants au niveau des dispositifs, • Expertise sur le fonctionnement des nano-composants permettant de dégager les ordres de grandeurs pertinents pour les dispositifs, les contraintes, la pertinence de quelques procédés de fabrication (reproductibilité, taux de défauts), • Collection de caractéristiques mesurées et développement éventuel d'expériences spécifiques, • Expertise et conception des circuits innovatifs pour l'électronique numérique avec ces nano-composants. Mots clés — Modélisation compacte, transistor Schottky à nanotube de carbone, simulation circuit, cellule mémoire SRAM, effet tunnel, WKB.

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Wan, Jing. „Dispositifs innovants à pente sous le seuil abrupte : du TEFT au Z²-FET“. Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00845632.

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Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d'effet tunnel. Un modèle analytique combinantl'effet tunnel et le transport dans le canal a été développé, montrant un bon accord entre les résultatsexpérimentaux et les simulations.Nous avons conçu et démontré un nouveau dispositif (Z2-FET, pour pente sous le seuil verticale et zéroionisation par impact), qui présente une commutation extrêmement abrupte (moins de 1 mV par décade decourant), avec un rapport ION / IOFF >109, un large effet de hystérésis et un potentiel de miniaturisation jusqu'à 20nm. La simulation TCAD a été utilisée pour confirmer que la commutation électrique du Z2-FET fonctionne parl'intermédiaire de rétroaction entre les flux des électrons et trous et leurs barrières d'injection respectives. LeZ2-FET est idéalement adapté pour des applications mémoire à un transistor. La mémoire DRAM basée sur leZ2-FET montre des performances très bonnes, avec des tensions d'alimentation jusqu'à 1,1 V, des temps derétention jusqu'à 5,5 s et des vitesses d'accès atteignant 1 ns. Une mémoire SRAM utilisant un seul Z²-FET estégalement démontrée sans nécessité de rafraichissement de l'information stockée.Notre travail sur le courant GIDL intervenant dans les MOSFETs de type FDSOI a été combiné avec leTFET afin de proposer une nouvelle structure de TFETs optimisés, basée sur l'amplification bipolaire du couranttunnel. Les simulations de nouveau dispostif à injection tunnel amélioré par effet bipolaire (BET-FET) montrentdes résultats prometteurs, avec des ION supérierus à 4mA/��m et des pentes sous le seuil SS inférieures à 60mV/dec sur plus de sept décades de courant, surpassant tous les TFETs silicium rapportés à ce jour.La thèse se conclut par les directions de recherche futures dans le domaine des dispositifs à pente sous leseuil abrupte.

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Nicoletti, Talitha. „Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória“. Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.

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O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL.
The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.

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Melul, Franck. „Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration“. Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.

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L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle architecture mémoire a été proposée : la cellule BitErasable. Elle a montré une excellente fiabilité et a permis d’apporter des éléments de compréhension sur les mécanismes de dégradation présents dans ces dispositifs mémoires à transistor de sélection enterré. Cette nouvelle architecture offre de plus la possibilité d’effacer les cellules d’un plan mémoire de façon individuelle : bit à bit. Conscient du grand intérêt que présente l’effacement bit à bit, un nouveau mécanisme d’effacement pour injection de trous chauds a été proposé pour la cellule eSTM. Il a montré des performances et un niveau de fiabilité parfaitement compatible avec les exigences industrielles des applications Flash-NOR
The objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications

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Masani, Deekshitha. „Analysis of radiation induced errors in transistors in memory elements“. OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2791.

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From the first integrated circuit which has 16-transistor chip built by Heiman and Steven Hofstein in 1962 to the latest 39.54 billion MOSFET’s using 7nm FinFET technology as of 2019 the scaling of transistors is still challenging. The scaling always needs to satisfy the minimal power constraint, minimal area constraint and high speed as possible. As of 2020, the worlds smallest transistor is 1nm long build by a team at Lawrence Berkeley National Laboratory. Looking at the latest trends of 14nm, 7nm technologies present where a single die holds more than a billion transistors on it. Thinking of it, it is more challenging for dyeing a 1nm technology. The scaling keeps going on and if silicon does not satisfy the requirement, they switch to carbon nanotubes and molybdenum disulfide or some newer materials. The transistor sizing is reducing but the pressure of radiation effects on transistor is in quench of more and more efficient circuits to tolerate errors. The radiation errors which are of higher voltage are capable of hitting a node and flipping its value. However, it is not possible to have a perfect material to satisfy no error requirement for a circuit. But it is possible to maintain the value before causing the error and retain the value even after occurrence of the error. In the advanced technologies due to transistor scaling multiple simultaneous radiation induced errors are the issue. Different latch designs are proposed to fix this problem. Using the CMOS 90nm technology different latch designs are proposed which will recover the value even after the error strikes the latch. Initially the errors are generally Single event upsets (SEUs) which when the high radiation particle strikes only one transistor. Since the era of scaling, the multiple simultaneous radiation errors are common. The general errors are Double Node Upset (DNU) which occurs when the high radiation particle strikes the two transistors due to replacing one transistor by more than one after scaling. Existing designs of SEUs and DNUs accurately determine the error rates in a circuit. However, with reference to the dissertation of Dr. Adam Watkins, proposed HRDNUT latch in the paper “Analysis and mitigation of multiple radiation induced errors in modern circuits”, the circuits can retain its error value in 2.13ps. Two circuits are introduced to increase the speed in retaining the error value after the high energy particle strikes the node. Upon the evaluation of the past designs how the error is introduced inside the circuit is not clear. Some designs used a pass gate to actually introduce the error logic value but not in terms of voltage. The current thesis introduces a method to introduce error with reduced power and delay overhead compared to the previous circuits. Introducing the error in the circuits from the literature survey and comparing the delay and power with and without introducing the error is shown. Introducing the errors in the two new circuits are also shown and compared with when no errors are injected.

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Fakher, Sundes Juma. „Advanced study of pentacene-based organic memory structures“. Thesis, Bangor University, 2014. https://research.bangor.ac.uk/portal/en/theses/advanced-study-of-pentacenebased-organic-memory-structures(5319a571-2c4c-4f90-a26c-fa5e7da82cfb).html.

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A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.

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Jessen, Gregg Huascar. „Investigation and Characterization of AlGaN/GaN Device Structures and the Effects of Material Defects and Processing on Device Performance“. Connect to this title online, 2002. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1038605384.

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Thesis (Ph. D)--Ohio State University, 2002.
Title from first page of PDF file. Document formatted into pages; contains xxx,198 p.: ill. (some col.). Includes abstract and vita. Advisor: Leonard J. Brillson, Dept. of Electrical Engineering. Includes bibliographical references (p. 188-198).

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Peng, Tzu-Hsuan, und 彭子瑄. „A Study of Memory Transistor Comprised of Thin-film Transistor and Nonvolatile Floating Gate Memory“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/62890518263582294112.

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碩士
國立交通大學
材料科學與工程學系所
103
Preparation and characterizations of the memory transistor (MT) with 1-transistor-and-1-capacitor device structure by combining the InGaZnO (IGZO) thin-film transistor and the nonvolatile floating gate memory (NFGM) containing AgInSbTe (AIST)-SiO2 nanocomposite layer as the charge storage layer are investigated. First, Si wafer as the substrate and thermally grown SiO2 gate dielectric layer were utilized to prepare MT sample in order to verify that the feasibility of IGZO TFT and AIST NFGM to MT architecture. Secondly, the FTO glass substrate and SiNx/SiO2 composite gate dielectric grown by plasma-enhanced chemical vapor deposition were adopted for MT preparation. It was found that, with an annealing at 200C for 60 sec, MT sample containing SiNx(10 nm)/SiO2(90 nm) composite gate dielectric structure exhibits the best electrical properties of Ig = 0.11 A, VTH = 2 V, on/off ratio = 4.3×104, sat = 8.2 cm2V−1sec−1, SS = 2.5 Vdecade−1 and VTH,MT = 8.7. In addition, a fairly good retention property of 22.7% degradation of memory window (VTH,MT) was observed after the retention test for 104 sec. In third part of study, the source/drain electrodes of MT samples accomplished previously were replaced by Mo/ITO layer so as to fabricate the fully transparent MT device. With an about 70% transparency in visible-light wavelength range, the MT device somehow exhibited an inferior electrical performance compared with the device with Al as the electrodes, i.e., Ig = 0.68 A, VTH = 3.8 V, On/Off Ratio = 6.5×102, sat = 0.38 cm2V−1sec−1, SS = 4.8 Vdecade−1, VTH,MT = 2.4 V. The degradation of electrical properties was ascribed to the increment of contact resistance at the interface of Mo and IGZO. X-ray photoelectron spectroscopy revealed the annealing at 200C might effectively reduce the crystalline defects in the samples and improve the electrical properties; nevertheless, the annealing at 300C caused the oxidization of Sb in AIST nanocrystals and jeopardized the memory capability of MT samples.

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Simões, João Pedro Rodrigues Branco de Almeida de. „Development of paper transistor with memory effect“. Master's thesis, 2015. http://hdl.handle.net/10362/16600.

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This work will discuss the use of different paper membranes as both the substrate and dielectric for field-effect memory transistors. Three different nanofibrillated cellulose membranes (NFC) were used as the dielectric layer of the memory transistors (NFC), one with no additives, one with an added polymer PAE and one with added HCl. Gallium indium zinc oxide (GIZO) was used as the device’s semiconductor and gallium aluminium zinc oxide (GAZO) was used as the gate electrode. Fourier transform infrared spectroscopy (FTIR) was used to access the water content of the paper membranes before and after vacuum. It was found that the devices recovered their water too quickly for a difference to be noticeable in FTIR. The transistor’s electrical performance tests yielded a maximum ION/IOFF ratio of around 3,52x105 and a maximum subthreshold swing of 0,804 V/decade. The retention time of the dielectric charge that grants the transistor its memory capabilities was accessed by the measurement of the drain current periodically during 144 days. During this period the mean drain current did not lower, leaving the retention time of the device indeterminate. These results were compared with similar devices revealing these devices to be at the top tier of the state-of-the-art.

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Chou, Ying-Hsuan, und 周映暶. „Electroactive Polymer Systems for Transistor-type Memory Devices“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/02601741702132689312.

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博士
國立臺灣大學
化學工程學研究所
102
Organic-based memory devices have received extensive scientific interest due to their advantages of flexibility, scalability, and material variety. A typical configuration of OFET memory devices is a conventional transistor with an additional charge storage layer ( named as the electret) between a semiconductor layer and dielectric layer. However, there is no systematic study on the above structure effects. In this thesis, we report the nonvolatile transistor memory device characteristics of n-type organic semiconducting nanowires, and reveal the geometry effects on memory characteristics. We further explored the effects of donor-acceptor charge transfer of polyimide electrets on the memory characteristics. In addition, high dielectric constant PI/TiO2 and polymer/graphene oxide (GO) composites as charge-storage dielectrics for the low-voltage nonvolatile memory devices were also investigated. The following summarize the important discovery of this thesis. 1. Self-Assembled Nanowires of Organic N-type Semiconductor for Nonvolatile Transistor Memory Devices (Chapter 2): Organic nonvolatile transistor-type memory devices using self-assembled nanowires of n-type semiconductor, N,N’-bis(2-phenylethyl)-perylene-3,4:9,10-tetracarboxylic diimide (BPE-PTCDI). The BPE-PTCDI nanowires with small diameters induced high electrical field and resulted in a large memory window (the shifting of the threshold voltage). The value of BPE-PTCDI nanowire based memory devices on the bare substrate could reach 51 V, which was significantly larger than that (~ 5 V) of thin film. The memory window was further enhanced to 78 V with the on/off ratio of 2.1x104 and the long retention time (104 s), using the hydrophobic surface. 2. Nonvolatile Organic Field-Effect Transistor Memory Devices Using Polymer Electrets with Different Thiophene Chain Lengths (Chapter 3): Synthesis of poly(5-hexyl-2-vinylthiophene) (PVT) and poly(5-Hexyl-5”-vinyl-2,2’:5,2” -terthiophene) (PVTT) as charge storage electrets for memory devices using BPE-PTCDI. The mobility of the memory device using PVTT electret was significantly smaller compared with that of PVT because its large torsional angle hindered the molecular packing of BPE-PTCDI. Besides, the highest HOMO energy level of PVTT facilitated the charges transfer from BPE-PTCDI and led to the largest memory window of 81V. 3. Thiophene and Selenophene Donor-Acceptor Polyimides as Polymer Electrets for Nonvolatile Transistor Memory Devices (Chapter 4): Nonvolatile memory characteristics of n-type BPE-PTCDI-based organic field-effect transistors (OFET) using the polyimide electrets of poly[2,5-bis(4-aminophenylenesulfanyl) -selenophene-hexafluoroisopropylidenediphthalimide] (PI(APSP-6FDA)), poly[2,5-bis(4-aminophenylenesulfanyl)-thiophene-hexafluoroisopropylidene -diphthalimide] (PI(APST-6FDA)), and poly (4,4’-oxydianiline-4,4’ -hexafluoroisopropylidenediphthalic anhydride) (PI(ODA-6FDA)). The device with PI(APSP-6FDA) exhibited the largest memory window because the highest HOMO energy level and heavy-atom effect facilitated the charges transferring from BPE-PTCDI and trapping in the PI electret. 4. Nonvolatile Transistor Memory Devices using High Dielectric Constant Polyimides Electrets (Chapter 5): The memory characteristics of pentacene-based OFET using polyimide electrets of PI(6FDA-TPA-CN), PI(DSDA-TPA-CN), and PI(BTDA-TPA-CN), consisted of electron-donating 4,4′-diamino-4〃 -cyanotriphenylamine (TPA-CN) and different electron-accepting dianhydrides The higher dipole moment and larger torsion angle of PI(6FDA-TPA-CN) resulted in the more stable charge transfer complex and accompanied with the largest memory window of 84 V of the fabricated device. 5. Nonvolatile Transistor Memory Devices Based on High-k Electrets of Polyimide/TiO2 Hybrids (Chapter 6): Novel nonvolatile memory behaviors of BPE-PTCDI-based OFET using the new polyimides (PIs), (poly[9,9-bis(4-(4-amino-3-hydroxyphenoxy)phenyl)fluorene-oxydiphthalimide]) PI(F-ODPA) and (poly[4,4’-bis(4-amino-3-hydroxyphenylthio)diphenyl sulfide -oxydiphthalimide]) PI(3S-ODPA) and their PI/TiO2 hybrids as electrets were reported. The OFET memory device derived from PI(F-ODPA) with π-conjugated fluorene moiety exhibited larger memory window (8.6V), and could be further enhanced by introducing TiO2 (up to 20wt%) into the PIs. 6. High-k Polymer/Graphene Oxide Dielectrics for Low-Voltage Flexible Nonvolatile Transistor Memories (Chapter 7): Solution-processable nonvolatile transistor memories on flexible ITO-PEN substrate were demonstrated using the electrets of poly(methacrylic acid) (PMAA) and graphene oxide (PMAA-GO) composites. The hydrogen bonding interaction effectively dispersed GO sheets in the high-k PMAA matrix. Besides, the fabricated transistor memories have a low operation voltage, a large threshold voltage shift, a long retention ability of up to 104 s, and good stress endurance of at least 100 cycles. Our study revealed the significance of the nano-morphology and donor/acceptor structure of the electrets on the OFET memory characteristics for advanced data storage applications.

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Hong, Chuan-Jie, und 洪川傑. „2D materials field-effect transistor and memory device“. Thesis, 2018. http://ndltd.ncl.edu.tw/handle/f3n5h7.

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碩士
中原大學
物理研究所
106
With the advancement of modern science and technology, electronic products have become an indispensable existence in people''s lives. Each product consists of electronic circuits, processors, logic components, etc., and the base of these components is the field-effect transistor. The miniaturization of the transistor faces the challenge of physical limits and requires new materials to solve. In recent years, two-dimensional materials are one of the most popular nano-materials. We will use 2D materials as channel materials to make field effect transistors. In this paper, we will analyze and discuss the results after measuring electrical properties. Memory plays a very important role in electronic products, but current memory development is facing the challenge of high density capacity. This research demonstrates the novel memory device based on two-dimensional material field effect transistor, in which self-assembled molecular layer is formed on two-dimensional material channel by molecular modification. The molecular configurations can be altered by different gate voltage pulse, leading to the different channel conductance and charge storage states. Using different gate voltage pulse and pulse duration times to control how many molecules are affected, devices can achieve multi-level storage states. We think this is a good step for the attempt in the development of novel memory device.

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Chang, Hsuan-Chun, und 張亘鈞. „Floating-gate Material Systems for Transistor-type Memory Devices“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/23690571512168087481.

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博士
國立臺灣大學
化學工程學研究所
103
Abstract Organic-based memory devices have received extensive scientific interest due to their advantages of flexibility, scalability, and material variety. A typical type of charge-trapping OFET memory is organic floating-gate memory. In this device, charges are stored in a metal or in a semiconducting layer called a floating gate, located within the insulating gate dielectric, and completely surrounded by insulator. However, there is no systematic study on the above structure effects. In this thesis, we report the effects of self-assembled monolayer (SAM) modification on the electrical memory characteristics. We further explored the organic heterojunction transistor with donor/acceptor interface on the electrical characteristics of transistor-type memory devices. Additionally, the C60 Needle/CuPc Nanoparticle Double Floating-Gate for the low-voltage nonvolatile memory devices were also investigated. The following summarize the important discovery of this thesis. 1. Improving the characteristics of an organic nano floating gate memory by a self-assembled monolayer (Chapter 2): SAM-based interfacial engineering significantly improved the hysteresis, memory window, and on/off ratio of a nano floating gate memory (NFGM) at zero gate voltage. This NFGM showed a large memory window of up to 190 V and on/off current ratio of 105 during writing and erasing with an operation voltage of 100 V of gate bias in a short time, less than 1 s. Furthermore, the devices show excellent nonvolatile behavior for bistable switching. The ON and OFF state can be stably maintained for 103 s with an Ion/Ioff current ratio of 106 for a pentafluorophenyl trimethoxysilane (FB-SAM) modified device. 2. Nonvolatile Organic Thin Film Transistor Memory Devices Based on Hybrid Nanocomposites of Semiconducting Polymers: Gold Nanoparticles (Chapter 3): Organic thin film transistor (OTFT)-based nonvolatile memory devices using the hybrid nanocomposites of semiconducting poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and ligand-capped Au nanoparticles (NPs), thereby serving as a charge storage medium. Electrical bias sweep/excitation effectively modulates the current response of hybrid memory devices through the charge transfer between F8T2 channel and functionalized Au NPs trapping sites. The electrical performance of the hybrid memory devices can be effectively controlled though the loading concentrations (0−9 %) of Au NPs and organic thiolate ligands on Au NP surfaces with different carbon chain lengths (Au-L6, Au-L10, and Au-L18). The memory window induced by voltage sweep is considerably increased by the high content of Au NPs or short carbon chain on the ligand. The hybrid nanocomposite of F8T2 : 9% Au-L6 provides the OTFT memories with a memory window of ∼41 V operated at ±30 V and memory ratio of ∼1 × 103 maintained for 1 × 104 s. 3. Flexible Nonvolatile Transistor Memory Devices Based on One-dimensional Electrospun P3HT:Au Hybrid Nanofibers (Chapter 4): A novel flexible nonvolatile flash transistor memory devices on flexible polyethylene naphthalate (PEN) substrate using one-dimensional (1D) electrospun nanofiber of poly(3-hexylthiophene) (P3HT):gold nanoparticles (Au NPs) hybrid as the channel. The Au NPs are functionalized with self-assembled monolayer (SAM) of para-substituted amino (Au-NH2), methyl (Au-CH3) or trifluoromethyl (Au-CF3) tail groups on the benzenethiol moiety. With the low operation voltage of ±5 V, the hybrid nanofiber transistor memories exhibit a 3.5~10.6 V threshold voltage shifting and at least 104 s data retention, with a minimum effect on ~100 programmed/erased stress endurances. The devices remain reliable and stable even under the bending conditions (radius: 5~30 mm) or 1000 repetitive bending cycles. 4. One-Dimensional Electrospun Nanofiber Channel for Organic Field Effect Transistor using Donor/Acceptor Planar Heterojunction Architecture (Chapter 5): Organic planar p-n heterojunction transistors based on electronspun poly(3-hexlthiophene) (P3HT) nanofibers/thermally deposited copper hexadecafluorophthalocyanine (F16CuPc) active layer have been developed for unipolar p-type nonvolatile memory and ambipolar device through simple tuning of top F16CuPc capping layer thickness. 5. Single-Crystal C60 Needle/CuPc Nanoparticle Double Floating-Gate for Low-Voltage Organic Transistor Based Non-volatile Memory Devices (Chapter 6): The double floating-gate device structure was formed from the semiconducting channel and heterostructured dual chargeable layers of CuPc NPs/single crystal C60 needles (N-C60) covered by crosslinking poly(4-vinylphenol) (c-PVP) tunneling barrier. Discrete p-type CuPc NPs and n-type N-C60 were independently selected as the hole and electron trapping sites for the above double floating-gate transistor memory to further enhance memory window and related data storage capacity. N-C60 trapping sites (diameters~590±15 nm) were first fabricated and then thermal-evaporated CuPc NPs (~15±3 nm) were deposited discretely on the N-C60 or the HfO2 interface. A systematic investigation on memory characteristics of double floating-gate devices were impartially compared to those of individual single floating-gate memory structure (N-C60 or CuPc-only devices) Our study revealed the significance of the self-assembled monolayer, donor/acceptor heterojunction architecture and double floating gate on the OFET memory characteristics for advanced data storage applications.

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Chien, Yu-Hsin Chang, und 張簡聿心. „Analysis and Application for Transparent Oxide Thin Film Transistor and Organic Thin Film Transistor Type Memory“. Thesis, 2017. http://ndltd.ncl.edu.tw/handle/tnh8ge.

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碩士
國立中央大學
化學工程與材料工程學系
106
The research can be divided into two parts. The first one is Solution-processable low-voltage driven transparent oxide thin film transistor. The second is Donor Acceptor and linkage effect for transistor type memory devices application. In the first part, we use ITO glass as substrate and gate. Then, about 120 nm TSO thin film was deposited on ITO glass. Its capacitance is approximately 172 nF cm-2, dielectric constant is 27.5. The TSO/ITO glass substrate was preheated to 400 oC, and then 65 nm ZnO semiconductor layer was deposited on it by using spray coating method, followed by annealing at 400 oC for 1 min. The elecrtrode was fabricated by two steps. Firstly, we deposited AgNWs through a shadow mask by using spray coating method. Then, we deposited another PEDOT:PSS layer through the shadow mask on the same position as we deposited AgNWs. The operation voltage of the thin film transistor is only 3 V, on/off current ratio 105, threshold voltage 0.36 V, subthreshold swing 815 mv dec-1, electron mobility 9.1 cm2 V-1 s-1. The results show the thin film transistor possessed well electrical characteristics and was stable under ambient air while doing experiment. In the second part, we use SiO2/Si as substrate and deposited electret by using spin coating method. Electret layer is fabricated for the purpose of storing holes or electrons. In this work, the electrets are TPA-PIS (Triphenylamine Sulfonyl-containing polyimide)、TPA-PES (Triphenylamine Sulfonyl-containing polyether) and TPA-PETS (Triphenylamine Sulfonyl-containing polyester), respectively. By researching and analyzing the electric characteristics and structure effects, we can be told that transistor type memory devices based on the three materials are all volatile memory. Yet, different structure, energy level or other relative characteristics can influent electric characteristics of transistor type memory. Therefore, we can learn knowledge by analyzing the relationships between structure and its effects on memory characteristics.

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Yeh, Mu Shih, und 葉沐詩. „3D IC Applicable Fin Field Effect Transistor and Nonvolatile Memory“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24hjgp.

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Fan, Zhen-Jia, und 范振嘉. „The Study of Novel Single Transistor Non-Volatile Memory Device“. Thesis, 2004. http://ndltd.ncl.edu.tw/handle/84783384156476316160.

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碩士
中原大學
電子工程研究所
92
Abstract Non-Volatile Memories (NVMs) have been developed and progressing in past decades, and recently it has been received much attention in mobile and portable applications, such as mobile phones, smart cards and digital cameras. In the First part of this thesis, the history of the Non-Volatile Memory (NVM) and the concept of the NVM are introduced. And the typical NVMs, such as EPROM, EEPROM, and flash memory are also introduced. The main purpose of this thesis presents the characteristics of a single-polysilicon non-volatile memory (NVM) device by using a novel NOI n-MOSFETs. Hot carriers are generated in NOI devices and to be stored as memories . The characteristics of this potential single-transistor NVM cell, including 2-bit operation, programming and erasing characteristics, are investigated. Their stability and reliability characteristics such as retention and cycling are also evaluated.

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Chen, Shih-Ching, und 陳世青. „Novel Nanowire SONOS TFTs Functioned as Nonvolatile Memory and Transistor“. Thesis, 2007. http://ndltd.ncl.edu.tw/handle/94449017372591563788.

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博士
國立清華大學
電子工程研究所
95
In first part, presents a method to enhance the performance of polycrystalline silicon thin film transistors (ploy-Si TFTs) by using an oxide-nitride-oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics than other TFTs. Since the crowding of the gate fringing field at the narrow channel surface of nanowire causes the large electrical field, the devices with nanowire structure have the better gate control ability. Hence, the device characteristics of SONOS-TFT with NW structure are mainly improved by the high electrical field originated from fringing electrical field effect. Furthermore, the SONOS-TFT also can be functioned as a nonvolatile memory under adequate bias operation. The proposed NW SONOS-TFT can exhibit high program/erase (P/E) efficiency due to the good gate control ability originated from fringing electrical field effects. Next, as the thickness of ONO layer thinner than that of poly-Si channel, the SONOS-TFT with nanowire channels is surrounded by poly-gate. The experimental results show that the NW SONOS-TFT has the superior electrical characteristics due to the tri-gate structure and additional corner current induced by corner effect. The simulation of electrical field results verified that the enhancement of P/E efficiency in NW SONOS-TFT is mainly attributed to the large number of corners and their corner effect. Also, the simulation result on electrical field reveals that the electrical field across the tunnel oxide is enhanced and that across the blocking oxide is reduced at the corner regions. This will lead the parasitic gate injection activity and the erasing speed can be apparently improved in the memory device, due to the pronounced corner effect and narrow channel width. In addition, the good endurance and retention are also obtained in this device. Finally, we apply the pi-gate structure on nanowire channel for polycrystalline silicon thin-film transistor (poly-SiTFT) combined with nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory. The proposed pi-gate TFT-SONOS has superior electrical characteristics of transistor, such as smaller threshold voltage (Vth) and steeper subthreshold slope (SS). The output characteristic also exhibits the high driving current and suppression of the kink-effect. For memory application, the device can provide high program/erase (P/E) efficiency and large threshold voltage shift under adequate bias operation. The enhanced performance for pi-gate SONOS-TFT is attributed to the larger effective channel width and number of corners.

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吳盈宏. „Study of Tri-Gate Tunneling Transistor and Its Flash Memory“. Thesis, 2012. http://ndltd.ncl.edu.tw/handle/18770672415349582090.

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40

Chu, Guan-Yu, und 朱冠宇. „Negative Capacitance Field-Effect Transistor and 1T Memory with Ferroelectric Effect“. Thesis, 2015. http://ndltd.ncl.edu.tw/handle/99420346246758814368.

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碩士
國立臺灣師範大學
光電科技研究所
103
The paper of T. S. Böscke’s team reported in IEDM 2011.The FeFET is a long-term contender for a fast, low power and nonvolatile memory technology. Physical limitation of Boltzmann tyranny with 2.3kbT/decade for MOSFET at room temperature restricts the switching slope. For break through the physical limitation, the equation of body factor of subthreshold swing must be < 1, the Cins turn into negative capacitance by select insulator material. Subthreshold swing will be < 60mv/dec. at room temperature. In FeRAM, information is permanently stored as polarization state of the gate insulator and can be read non-destructively as a shift of the threshold voltage. The FeRAM concept was experimentally demonstrated, but the practical implementation has remained elusive. In this study, we will develop the low swing FET and 1T Memory by negative capacitance concept. Therefore, we will develop HfO2:Zr to achieve polarization effect. The objective is to improve the subthreshold swing and hysteresis window let the information stored in FeRAM.

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Shen沈盈君, Ying-Jun, und 沈盈君. „Investigation of Thin Film Transistor Memory Devices with Graphene Quantum Dots“. Thesis, 2016. http://ndltd.ncl.edu.tw/handle/48506339536390253368.

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碩士
國立成功大學
微電子工程研究所
104
The main purpose of this thesis is to investigate the impact on thin film transistor’s operation properties after graphene quantum dots (GQDs) blend into poly (methyl methacrylate) (PMMA) as floating gate. This study focused on discussing the condition of adding GQDs or not, and then did a series of physical and electrical analyses. At the end, I did the further reliability testing. Here we divided the experiment into three parts. The purpose was to do the comparisons of pentacene-based OTFT memory using different materials as floating gate. In experiment I, we used PMMA as floating gate. The structure was composed by n^+-Si (gate electrode) / SiO2 (dielectric layer) / PMMA (floating gate) / pentacene (channel layer) / Au (source and drain electrodes). The threshold voltage of -20.46 V, on/off current ratio of 9.02×104, sub-threshold swing of 2.37 V/decade, and memory window of 8.52 V can be obtained from transfer characteristics. In experiment II, the structure was the same as experiment I, but the floating gate material was changed as PMMA:GQDs composite layer. The GQDs play an important role to capture the carrier charges in the transistor device. From the results of electrical measurement, we could find that it achieved about two times higher on/off current ratio, two times faster sub-threshold swing and eleven times larger memory window after adding GQDs into the PMMA layer. Moreover, in write-read-erase-read cycle test, it had well switching cycle performance. The curves revealed that the probe current of the on-state was four orders of magnitude higher than that of the off-state. Besides, according to the retention time, we found that it could promote the charge storage time after adding in GQDs. All of the results illustrated that it could improve the memory properties by adding GQDs into the PMMA layer. In experiment III, we used the experiment II’s structure as based, and added the PMMA on the top of PMMA:GQDs composite layer as tunneling layer. Originally, we expected that it can reduce the surface roughness which made the interface between floating gate and channel layer become well. However, the results showed it didn’t enhance the electrical and switching properties. On the contrary, the memory window became smaller. We attributed these results to the PMMA- PMMA:GQDs interface was not good and the total PMMA-PMMA:GQDs-SiO2 three layers was so thick that made the gate control decline.

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42

Wang, Po-Sheng, und 王柏勝. „Electrical properties and memory effects in self-oxidized MoOx/MoS2 transistor“. Thesis, 2017. http://ndltd.ncl.edu.tw/handle/6bfew8.

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碩士
國立交通大學
電子物理系所
105
Mechanically exfoliated molybdenum disulfide (MoS2) flakes are dispersed on silicon substrates capped with a 300-nm thick silicon dioxide layer. The standard electron beam lithography and thermal evaporation were used to pattern Au leads on the MoS2 flakes. The as-patterned MoS2 field effect transistors (FETs) were then annealed in a high vacuum to reduce the contact resistance. The MoS2 FETs demonstrates n-type semiconductor and possess good ohmic contact behaviors. The MoS2 FETs were exposed to ozone gas for self-limiting oxidation and the surface layer was converted to MoOx (x≤3). By controlling the ozone treatment, the FET devices changed from its natively n-type to an either ambipolar or a p-type semiconductor. The on-off ratio of transistors is up to 104. The variation of electron or hole dominated transport is owing to the change of the work function after oxidation. The oxidized MoOx has higher work function and gives efficient hole injections. Current-voltage (Ids -Vds) curves showed back-to-back Schottky diodes, which implies that the Schottky junction is formed between Au electrodes and MoOx. The Schottky barrier was inspected, showing a variation with bias and gating voltages. In the following discussion, we categorized oxidized MoS2 FETs into n-type, ambipolar, and p-type FETs. Electron transport of n-type FETs (MoS2) is well described by the theory of two-dimensional variable range hopping at temperatures in the range between 80 and 180 K. At higher temperatures from 180 to 240 K, it can be fitted using thermally activated transport. Nevertheless, electron transport of ambipolar FETs (mildly oxidized MoS2) can be separated into two regions of either electron or hole doping. The electron doping regime is well described by the theory of two-dimensional variable range hopping at temperatures from 80 to 180 K whereas, at higher temperatures from 180 to 240 K, it is better described by thermally activated transport. The hole doping regime is well described by the theory of two-dimensional variable range hopping from 220 to 280 K. At temperatures lower than 220 K, electron transport is dominated by tunneling. The hole transport of p-type FETs is well described by the theory of two-dimensional variable range hopping at temperatures from 120 to 200 K. On the other hand, we discovered a memory effect on p-type FETs. The state of the p-type FETs can be changed by a writing voltage. If the writing current are precisely controlled, the devices can be operated at multiple states and the states can be stored for a long time. After a simple reliability test, we observe reproducible and stable current states in the memory devices.

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43

Dong, Lei, und 董磊. „Novel Polyimides Systems for Organic Field-effect Transistor (OFET) Memory Device Applications“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/23252445829692300863.

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碩士
國立臺灣大學
化學工程學研究所
102
Organic-based memory devices have received extensive research interest due to their advantages of flexibility, solution processability, low cost and materials variety compared to traditional inorganic silicon ones. Meanwhile, polyimide is mostly thought to be one of the best candidates for memory materials, concerning its good thermal stability, chemical resistance and outstanding mechanical strength. However, the relationships between the molecular structures of polyimides and corresponding electrical memory characteristics have not been fully explored yet. In this thesis, both single acceptor and donor/acceptor systems were explored for a better understanding of structural effects on the electrical characteristics of transistor-type memory devices. In chapter 2, the new semi-conjugated polyimides as the charge-storage electrets for the p-type pentacene-based non-volatile field-effect transistor (OFET) memory devices, comprising different electron-accepting dianhydride moieties, PI(BPDA-DAP), PI(PMDA-DAP), and PI(ODPA-DAP), and varied aliphatic lengths, PI(PMDA-DAH) and PI(PMDA-DAD) were successfully developed. The device fabricated upon PI(BPDA-DAP) electret exhibited the largest memory window owing to its low-lying LUMO energy level resulting from the largest conjugation. Besides, the increment of aliphatic length, from PI(PMDA-DAP) to PI(PMDA-DAH) to PI(PMDA-DAD), led to a gradual switch from flash to WORM (write once read many times) type memory property, accompanied by the reduced memory window. This study demonstrated that the memory characteristics and charge mobility of the transistor memory could be effectively modulated through the adaptation of the electron accepting moiety and spacer moiety in the semi-conjugated polyimide based electrets. In chapter 3, the nonvolatile memory characteristics of p-type pentacene-based organic field-effect transistor (OFET) using the synthesized polymer electrets PA(BAPF-AC), PI(BAPF-6FDA) and PI(BAPF-ODPA) were systematically studied. These three polymers contain identical electron-donating 9,9-Bis(4-aminophenyl)fluorene (BAPF) and different building blocks of neutral (hexanediamide (AC) ) and electron-accepting (aromatic hexa&;#64258;uoroisopropylidenediphthalimide (6FDA) and oxydiphthalimide (ODPA)), respectively. The OEFT memory characteristic of devices fabricated with these three polymers vary from the EORM (erase once and read many times) behavior (PA(BAPF-AC)) to semi-flash (PI(BAPF-ODPA)), and to flash (PI(BAPF-6FDA)), mainly due to the differences in energy levels and charge transfer effects. Furthermore, the memory device based on PI(BAPF-6FDA) exhibits the largest memory window, which is attributed to the strong electron-trapping facilitated by the induced charge separation effect from hexafluoropropane moiety. Similarly, the larger torsion angle of PI(BAPF-6FDA) results in the more stable charge transfer complex, leading to more electrons trapped. The present study provided an insight into the relationship between the charge transfer effect and the memory characteristic, and revealed the possible tuning strategies on the chemical structure of materials to achieve varied capabilities of storing charges for advanced OFET memory applications.

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44

Lu, Tien-Lin, und 呂天麟. „Iridium Nanocrystal Assisted Thin Film Transistor Nonvolatile Memory with Asymmetric Tunnel Barrier“. Thesis, 2011. http://ndltd.ncl.edu.tw/handle/15164010668256930611.

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碩士
中華大學
電機工程學系碩士班
99
Since Sze et al invented the first floating-gate nonvolatile memory (NVM) at Bell Lab in 1967, various kinds of nonvolatile memories and the process technologies have been rapidly proposed and progressed over the past 40 years. In recent years, the scaling of tunneling oxide of conventional floating gate memories is hard to be realized due to the data retention is difficult to maintain with ultra thin tunneling oxide. One of possible solutions is nanocrystals (NCs) assisted nonvolatile memory. The greatest advantage of using NCs is that charges are distributed in more trapping centers, which minimizes charge loss. This great advantage results a thinner tunnel layer, a lower working voltage, and a higher programming/erasing (P/E) speed. In all kinds of NCs, metallic NCs were observed to exhibit higher performance characteristics than semiconductor NCs owing to a stronger coupling with the conduction channel, a wider range of available work functions, a higher density of states around the Fermi level for storing more charges, and a smaller energy perturbation due to carrier confinement. Therefore, the studies of metallic NCs in NVM applications were proposed greatly in the last half decade. Another of possible solution for breaking the scaling limit of tunneling layer thickness is to use multi-stacked tunneling layer for modulating energy band-gap. It can enhance the P/E efficiency significantly and maintain storage of carriers effectively. In some researches, bi-stacked tunneling layer structures were called asymmetric tunnel barrier (ATB) structures. However, most of those studies were conducted to examine effects of NCs or tunneling layer engineering in metal-insulator-semiconductor devices on memory performance. In this work, an iridium nanocrystals (Ir-NCs) assisted thin film transistor (TFT) NVM with Si3N4/SiO2 stack of asymmetric tunnel barrier was fabricated, and its P/E characteristics and performances were investigated.

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45

劉冠呈. „Study of Inversion mode and Junctionless Twin Thin-Film-Transistor Nonvolatile Memory“. Thesis, 2013. http://ndltd.ncl.edu.tw/handle/73807685285606825977.

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碩士
國立清華大學
工程與系統科學系
101
This study proposed the n-channel and p-channel twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory (NVM) with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its p-channel Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after ten years, the charge is 53 % of its initial value. Further, a new generation study of junctionless NVM was studied in this work. The memory is also based on twin structure. It can be programmed but erasing is still a challenge. Surprisingly, the device exhibits a good retention characteristic and have a great potential been used as one time programmable device. In the future, these twin poly-Si FinFET NVM devices have a great potential to be used in multilayer Si ICs in fully functional system-on-panel, active matrix liquid crystal display and 3D stacked flash memory applications.

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46

Cheng, Chih-Hung, und 鄭智鴻. „The Design and Optimization of the One Transistor Resistance Switching Nonvolatile Memory“. Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8386e5.

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47

Liu, I.-Min, und 劉逸民. „Analysis and Design of New SRAM Memory Cells Based on Lambda Bipolar Transistor“. Thesis, 1995. http://ndltd.ncl.edu.tw/handle/00072784302286549535.

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碩士
國立交通大學
電子研究所
83
The voltage-controlled negative-differential-resistance device by using merged integrated circuit of n-channel enhancement mode MOSFET's and parasitic NPN bipolar transistors, called Lambda bipolar transistor (LBT), is known for its memory application. In this thesis, new LBT structures are developed, and their characteristics are derived by simple circuit model and device physics. Novel single-sided static memory cells based on the proposed LBT's are presented. Comparisons between the proposed and conventional cells are also made. A new current sense amplifier suitable for the read operation of single-bit- line SRAM's is analyzed and applied to our circuit. Finally, timing simulations based on our organization are presented, which demonstrate a high-performance SRAM can be achieved by the proposed methodology.

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48

Chin-YangLin und 林志陽. „The study of organic field-effect transistor based memory devices with polymeric electrets“. Thesis, 2013. http://ndltd.ncl.edu.tw/handle/96693095042039979571.

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碩士
國立成功大學
光電科學與工程學系
101
This thesis discusses N-type memory devices with various charge trapping layers. N,N’-dioctadecyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C13H27) and polyimide (PI) are used as the active and the charge trapping materials in the fabrication of organic non-volatile memory devices. The surface properties of charge trapping layers made a great impact on electrical properties of memory devices. First, TiO2 nanoparticles (NPs) were doped into the PI to role as the charge trapping material in N-type organic memory devices. In the experiment, three type PIs with different concentrations of TiO2 NPs, namely (a) DA7013 (pure PI), (b) DA7013 with 5 wt% TiO2 NPs, and (c) DA7013 with 20 wt% TiO2 NPs, were used. It was found that the memory window of the devices increased with increasing with the concentration of TiO2 NPs. Therefore, the memory window can be controlled by varying the concentration of TiO2 NPs. Second, another three type PIs with different side chain densities, namely PI-1B (20% side chain), PI-2B (10% side chain), PI-3B (6% side chain),and DA9000A without side chain, were used as trapping material to study the influence of the side chain density on the memory window. The main chain of these PIs with side chain is the same as that of DA9000A. Interestingly, on memory widow was observed in the DA9000A-based device owing to its lack of the ability of capturing carriers by the side chain. In the experiment, the effect of carriers captured by the side chain of PI was studied clearly.

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49

Yu-FuWang und 王裕夫. „The study of organic field-effect transistor based memory devices with polymeric electrets“. Thesis, 2016. http://ndltd.ncl.edu.tw/handle/08246149799485849044.

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博士
國立成功大學
光電科學與工程學系
104
In the past years, organic field-effect transistor (OFET) based memory devices have attracted many attentions in organic electronics, because of their unique advantages, such as easily packed with integrated circuits, low-temperature manufacturing, and non-destructive reading out of digital signals. In OFETs, pentacene is usually used as a standard organic semiconductor for being an active layer in p-type device, owing to its superior hole transport property between molecules. However, the researches of n-type OFET device was relatively backward comparing with p-type device. This may attribute to the difficult synthesis and unstable structures under atmosphere environment for n-type semiconductors, which restricts the electron transport ability of OFETs. Therefore, the researches for n-type semiconductor-based OFET memory device are still scarcity. On the other hand, the interfacial property between semiconductor layer and gate dielectric layer plays an important role for developing high performance OFET memories. In this thesis, we propose some simple routes to improving both electrical characteristics and electrical memory windows of n-type OFET memories. A novel polyimide (PI) electret with a quasi-permanent electrostatic dipole on side chain structures was synthesized in this study. We demonstrate that the carriers can be trapped by the polar groups near the semiconductor/PI interface, and the electrical properties and memory effects of memory device were successfully controlled by the mixing ratios of PI electret. Finally, we also propose an easy method to improve the memory window and operation speed of n-type OFET-based photomemory devices by constructing a discontinuous pn-heterojnuction structure within the active layer that can effectively enhance charge carrier transportation at interfaces to broaden the memory window of memory devices. In the first part, a molecular design for the electret material of n-operating organic field-effect transistor-based (OFET) memories is introduced. A large memory window and high operating speed were achieved while the polar groups are connected to the polymer chain of polyimide, which plays the role of electret of a transistor memory device. In fact, the significant memory effect in the device with PI electret can be ascribed to the charge carriers that were rapidly trapped and released by the polar groups of PI electret. The phase variation of electrical force microscopy (EFM) images showed that polarization field induces charge trapping states on the surface of electret layer and accumulates charged carriers within the conducting channel of OFET to achieve high-performance memory and transistor simultaneously. In conclusion, an extra-large memory window was also obtained by introducing photo-induced charge transfer effect. In the second part, a series of polyimides (PIs) containing different weight ratios of polar piperazinyl and cholesterol side chains, denoted as PCPI, was synthesized in this study. These PIs were used as gate dielectrics of n-type organic field-effect transistors (OFETs) and as electrets of photo-assisted organic memories. The thermal properties of the PI/PCPI composite films were improved by increasing the spatial distribution of the PCPI molecules to form a thermally stable dielectric film. The performances of OFETs, as PIs were used as gate dielectrics, were gradually enhanced by increasing the mixture ratios of the PCPI molecules. A dipole field, which originated from the PCPI molecules into the OFETs, was introduced to observe the special phenomenon of output current growth under a long operation time. The application of these superior transistors with PCPI- and PI-mixed electrets to the field of organic memory resulted in a photo-assisted memory window of more than 38 V. The mechanisms of the carriers trapped in and released from the PI electrets were elucidated. Results showed that our devices possess excellent stability for OFETs and an extra-large memory window for organic memory devices. In the third part, a discontinuous pentacene layer was formed on the PI/PTCDI interface by controlling the parameters of thermal evaporation process. The thicknesses of pentacene layers were varied from 0 nm (serve as standard device) to 10 nm. The transmission electron microscopy (TEM) images show that the dispersion of the island type pentacene crystals on n-type PTCDI-C13H27 monolayer, which confirms that the three dimension growth of pentacene molecules instead of the traditional layer-by-layer growth mechanism. Interesting crystalline properties of pentacene films in in-plane and out of-plane directions were obtained by grazing angle x-ray diffraction (GIXRD) measurements. The GIXRD results demonstrate that the pentacene crystals are trending to three dimension growth on PTCDI-C13H27 monolayer below 5 nm thickness, and then transfer to layer-by-layer growth model when the thickness of pentacene layer is above 5 nm. This discontinuous pn-heterojunction structure can reduce the chances of charge recombination of injected electrons in top contact geometry OFETs. As this structure was applied in an organic memory device, the electrical memory window of the device with 5 nm-thick pentacene layer was gradually extended to 47.6 V, which is larger than the past reports for n-type memory device. This result demonstrates that the inserted pn-heterojunction structure possesses more effective interface to lead the photo-induce charges dissociation into conducting channel and increase the density of minority carriers to extend the negative shift of VT. Moreover, as the operation time of programing and erasing process was reduces to 0.2 ms, the electrical memory window is still maintain at 32.6 V, which realizes the high performance and high-speed operation n-type photomemory device.

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50

Chang, Yu-Chia, und 張育嘉. „A Novel Double-Gated Poly-Si Nanowire Thin Film Transistor and SONOS Memory“. Thesis, 2009. http://ndltd.ncl.edu.tw/handle/45359432632450068432.

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碩士
國立交通大學
電子工程系所
97
In this thesis, a simple and cost-effective method for fabricating poly-Si nanowire (NW) thin film transistor (TFT) without the necessity of advanced lithography tools is proposed and demonstrated. In this scheme, a unique two-step etching is developed to form nano cavities at the sidewalls of an electrode. After filling the cavities with a Si film, an anisotropic etch is subsequently performed to define the NW structures in a self-aligned manner. With the proposed scheme, independent double-gated NW devices could be constructed. With such configuration, more flexibility in device operation could be provided. Characteristics of different operation mode are compared and analyzed. With the implementation of oxide-nitride-oxide (ONO) gate dielectrics and in-situ doped source/drain (S/D), dramatic improvements in device characteristics can be achieved. Based on the proposed scheme, NW TFT-SONOS memory devices were also fabricated and characterized. The two independent gates are shown to increase the flexibility and improve the programming/erasing efficiency.

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Dissertationen zum Thema „Memory transistor“

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