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Zeitschriftenartikel zum Thema „Logic optimizations“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 29. Juli 2025

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1

Rus, Teodor, and Eric van Wyk. "Using Model Checking in a Parallelizing Compiler." Parallel Processing Letters 08, no. 04 (1998): 459–71. http://dx.doi.org/10.1142/s0129626498000468.

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In this paper we describe the usage of temporal logic model checking in a parallelizing compiler to analyze the structure of a source program and locate opportunities for optimization and parallelization. The source program is represented as a process graph in which the nodes are sequential processes and the edges are control and data dependence relationships between the computations at the nodes. By labeling the nodes and edges with descriptive atomic propositions and by specifying the conditions necessary for optimizations and parallelizations as temporal logic formulas, we can use a model c

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Kudva, P., Associate, A. Sullivan, and W. Dougherty. "Measurements for structural logic synthesis optimizations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 6 (2003): 665–74. http://dx.doi.org/10.1109/tcad.2003.811456.

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3

Khurshid, Burhan, and Roohie Naaz. "Technology - Dependent Optimization of FIR Filters based on Carry - Save Multiplier and 4:2 Compressor unit." Electronics ETF 20, no. 2 (2017): 43. http://dx.doi.org/10.7251/els1620043k.

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This work presents an FPGA implementation of FIR filter based on 4:2 compressor and CSA multiplier unit. The hardware realizations presented in this pa per are based on the technology-dependent optimization of these individual units. The aim is to achieve an efficient mapping of these isolated units on Xilinx FPGAs. Conventional filter implementations consider only technology-independent optimizations and rely on Xilinx CAD tools to map the logic onto FPGA fabric. Very often this results in inefficient mapping. In this paper, we consider the traditional CSA-4:2 compressor based FIR filte rs an

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Gäher, Lennard, Michael Sammler, Simon Spies, et al. "Simuliris: a separation logic framework for verifying concurrent program optimizations." Proceedings of the ACM on Programming Languages 6, POPL (2022): 1–31. http://dx.doi.org/10.1145/3498689.

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Today’s compilers employ a variety of non-trivial optimizations to achieve good performance. One key trick compilers use to justify transformations of concurrent programs is to assume that the source program has no data races : if it does, they cause the program to have undefined behavior (UB) and give the compiler free rein. However, verifying correctness of optimizations that exploit this assumption is a non-trivial problem. In particular, prior work either has not proven that such optimizations preserve program termination (particularly non-obvious when considering optimizations that move i

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BÁRÁNY, VINCE, MICHAEL BENEDIKT, and BALDER TEN CATE. "SOME MODEL THEORY OF GUARDED NEGATION." Journal of Symbolic Logic 83, no. 04 (2018): 1307–44. http://dx.doi.org/10.1017/jsl.2018.64.

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AbstractThe Guarded Negation Fragment (GNFO) is a fragment of first-order logic that contains all positive existential formulas, can express the first-order translations of basic modal logic and of many description logics, along with many sentences that arise in databases. It has been shown that the syntax of GNFO is restrictive enough so that computational problems such as validity and satisfiability are still decidable. This suggests that, in spite of its expressive power, GNFO formulas are amenable to novel optimizations. In this article we study the model theory of GNFO formulas. Our resul

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Lacey, David, Neil D. Jones, Eric Van Wyk, and Carl Christian Frederiksen. "Proving correctness of compiler optimizations by temporal logic." ACM SIGPLAN Notices 37, no. 1 (2002): 283–94. http://dx.doi.org/10.1145/565816.503299.

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ZHOU, NENG-FA, TAISUKE SATO, and YI-DONG SHEN. "Linear tabling strategies and optimizations." Theory and Practice of Logic Programming 8, no. 01 (2007): 81–109. http://dx.doi.org/10.1017/s147106840700316x.

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AbstractRecently there has been a growing interest in research in tabling in the logic programming community because of its usefulness in a variety of application domains including program analysis, parsing, deductive databases, theorem proving, model checking, and logic-based probabilistic learning. The main idea of tabling is to memorize the answers to some subgoals and use the answers to resolve subsequent variant subgoals. Early resolution mechanisms proposed for tabling such as OLDT and SLG rely on suspension and resumption of subgoals to compute fixpoints. Recently, the iterative approac

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Zhou, Neng-Fa. "Global Optimizations in a Prolog Compiler for the Toam." Journal of Logic Programming 15, no. 4 (1993): 275–94. http://dx.doi.org/10.1016/s0743-1066(14)80001-0.

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Xu, Ziyang, Yebin Chon, Yian Su, et al. "PROMPT: A Fast and Extensible Memory Profiling Framework." Proceedings of the ACM on Programming Languages 8, OOPSLA1 (2024): 449–73. http://dx.doi.org/10.1145/3649827.

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Memory profiling captures programs’ dynamic memory behavior, assisting programmers in debugging, tuning, and enabling advanced compiler optimizations like speculation-based automatic parallelization. As each use case demands its unique program trace summary, various memory profiler types have been developed. Yet, designing practical memory profilers often requires extensive compiler expertise, adeptness in program optimization, and significant implementation effort. This often results in a void where aspirations for fast and robust profilers remain unfulfilled. To bridge this gap, this paper p

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Apoorva, Reddy Proddutoori. "Improvizing Power Optimizations Using Dynamic Cascode Voltage Switching Logic." Journal of Scientific and Engineering Research 6, no. 11 (2019): 311–14. https://doi.org/10.5281/zenodo.12798330.

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In this paper we display another choice the 13-decision demonstrate, based on a graph chart that can be utilized to maximize proficiency Make DCVS circuits yourself. We assess our compared to customary DCVS amalgamation strategies that utilize requested parallel choices graphs that illustrate that our approach will without a doubt succeed as well as or on the other hand superior compared to OBDD based methodologies. Within the journey for high-performance CMOS, dynamic cascode voltage switch (DCVS) circuits are rising as an vital modern range of ponder. consolidated circuits Potential benefits

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Kim, Yonghyun, Minki Cho, Jaehyung Lee, et al. "Archmage and CompCertCast: End-to-End Verification Supporting Integer-Pointer Casting." Proceedings of the ACM on Programming Languages 9, POPL (2025): 1326–54. https://doi.org/10.1145/3704881.

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Although there have been many approaches for developing formal memory models that support integer-pointer casts, previous approaches share the drawback that they are not designed for end-to-end verification, failing to support some important source-level coding patterns, justify some backend optimizations, or lack a source-level logic for program verification. This paper presents Archmage, a framework for integer-pointer casting designed for end-to-end verification, supporting a wide range of source-level coding patterns, backend optimizations, and a formal notion of out-of-memory. To facilita

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Song, Jiansen, Wensheng Dou, Yu Gao, et al. "Detecting Metadata-Related Logic Bugs in Database Systems via Raw Database Construction." Proceedings of the VLDB Endowment 17, no. 8 (2024): 1884–97. http://dx.doi.org/10.14778/3659437.3659445.

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Database Management Systems (DBMSs) are widely used to efficiently store and retrieve data. DBMSs usually support various metadata, e.g., integrity constraints for ensuring data integrity and indexes for locating data. DBMSs can further utilize these metadata to optimize query evaluation. However, incorrect metadata-related optimizations can introduce metadata-related logic bugs, which can cause a DBMS to return an incorrect query result for a given query. In this paper, we propose a general and effective testing approach, Raw database construction (Radar), to detect metadata-related logic bug

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Heo, Jinmoo, Seongjoo Lee, and Yunho Jung. "Field-Programmable Gate Array Implementation of Backprojection Algorithm for Circular Synthetic Aperture Radar." Electronics 14, no. 8 (2025): 1544. https://doi.org/10.3390/electronics14081544.

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This paper presents a backprojection algorithm (BPA) accelerator implemented on a field-programmable gate array (FPGA) for circular synthetic aperture radar (SAR) systems. Although the BPA offers superior image quality, it requires significantly more computation and is memory intensive, necessitating hardware optimization. In particular, the BPA accumulates image data, leading to high memory requirements that must be reduced for embedded system implementation. To address this issue, we optimized the floating-point (FP) bit width, focusing on the output data that form the image, rather than onl

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Hernández-Ramos, José L., Antonio J. Jara, Leandro Marín, and Antonio F. Skarmeta Gómez. "DCapBAC: embedding authorization logic into smart things through ECC optimizations." International Journal of Computer Mathematics 93, no. 2 (2014): 345–66. http://dx.doi.org/10.1080/00207160.2014.915316.

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Zhang, Chi, and Manuel Rigger. "Constant Optimization Driven Database System Testing." Proceedings of the ACM on Management of Data 3, no. 1 (2025): 1–24. https://doi.org/10.1145/3709674.

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Logic bugs are bugs that can cause database management systems (DBMSs) to silently produce incorrect results for given queries. Such bugs are severe, because they can easily be overlooked by both developers and users, and can cause applications that rely on the DBMSs to malfunction. In this work, we propose Constant-Optimization-Driven Database Testing (CODDTest) as a novel approach for detecting logic bugs in DBMSs. This method draws inspiration from two well-known optimizations in compilers: constant folding and constant propagation. Our key insight is that for a certain database state and q

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Potikas, Petros, Panos Rondogiannis, and Manolis Gergatsoulis. "A Value-propagating Transformation Technique for Datalog Programs Based on Non-Deterministic Constructs." Fundamenta Informaticae 72, no. 4 (2006): 485–527. https://doi.org/10.3233/fun-2006-72404.

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The branching-time transformation is a recent technique for optimizing Chain Datalog programs. In this paper we propose a significant extension of the branching-time transformation which we believe opens up a promising new direction of research in the area of value-propagating Datalog optimizations. More specifically, the proposed transformation can handle more general programs that allow multiple consumptive occurrences of variables in the bodies of clauses. This extension is achieved by using as target language the temporal logic programming formalism Datalog _{nS} enriched with choice predi

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Saeedi, Mehdi, Mona Arabzadeh, Morteza Saheb Zamani, and Mehdi Sedighi. "Block-based quantum-logic synthesis." Quantum Information and Computation 11, no. 3&4 (2011): 262–77. http://dx.doi.org/10.26421/qic11.3-4-6.

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In this paper, the problem of constructing an efficient quantum circuit for the implementation of an arbitrary quantum computation is addressed. To this end, a basic block based on the cosine-sine decomposition method is suggested which contains $l$ qubits. In addition, a previously proposed quantum-logic synthesis method based on quantum Shannon decomposition is recursively applied to reach unitary gates over $l$ qubits. Then, the basic block is used and some optimizations are applied to remove redundant gates. It is shown that the exact value of $l$ affects the number of one-qubit and CNOT g

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Sheriff, Bonnie A., Dunwei Wang, James R. Heath, and Juanita N. Kurtin. "Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations." ACS Nano 2, no. 9 (2008): 1789–98. http://dx.doi.org/10.1021/nn800025q.

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Hsiao, K. S., and C. H. Chen. "Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 10 (2006): 1089–102. http://dx.doi.org/10.1109/tvlsi.2006.884150.

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Balasubramanian, P., D. A. Edwards, and W. B. Toms. "Redundant Logic Insertion and Latency Reduction in Self-Timed Adders." VLSI Design 2012 (May 17, 2012): 1–13. http://dx.doi.org/10.1155/2012/575389.

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A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self-timed adder circuits. The proposed concept is universal in the sense that it can be extended to a variety of self-timed design methods. Redundant logic can be incorporated to generate efficient self-timed realizations of iterative logic specifications. Based on the case study of a 32-bit self-timed carry-ripple adder, it has been found that redundant implementations minimize the data path latency by 21.1% at the expense of increases in area and power by 2.3% and 0.8% on average com

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Zhang, Ming Ming, Shu Guang Zhao, and Xu Wang. "Reversible Logic Synthesis-Oriented Multi-Objective Automatic Design Method Based on Evolutionary Design Techniques." Key Engineering Materials 439-440 (June 2010): 534–39. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.534.

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This paper applies evolutionary design techniques to the reversible logic synthesis, and proposes a reversible logic synthesis-oriented multi-objective automatic design method based on evolutionary design techniques. Firstly, build a gate-level array model of reversible logic circuits (RLC) in order to model the synthesis problems as ones of constrained multi-objective optimizations. Then, encode the candidate RLC to a set of binary evolutionary individuals which are solved by the specialized Pareto-optimal multi-objective evolutionary algorithm. In addition, adopt “pre-bit priority” mechanism

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Ba, Jinsheng, and Manuel Rigger. "Keep It Simple: Testing Databases via Differential Query Plans." Proceedings of the ACM on Management of Data 2, no. 3 (2024): 1–26. http://dx.doi.org/10.1145/3654991.

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Query optimizers perform various optimizations, many of which have been proposed to optimize joins. It is pivotal that these optimizations are correct, meaning that they should be extensively tested. Besides manually written tests, automated testing approaches have gained broad adoption. Such approaches semi-randomly generate databases and queries. More importantly, they provide a so-called test oracle that can deduce whether the system's result is correct. Recently, researchers have proposed a novel testing approach called Transformed Query Synthesis (TQS) specifically designed to find logic

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Wang, Hsiao-Fan, and Kuang-Yao Wu. "Preference Approach to Fuzzy Linear Inequalities and Optimizations." Fuzzy Optimization and Decision Making 4, no. 1 (2005): 7–23. http://dx.doi.org/10.1007/s10700-004-5567-0.

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Rajeanderan Revichandran, Jaffar Syed Mohamed Ali, Moumen Idres, and A. K. M. Mohiuddin. "A Review of HVAC System Optimization and Its Effects on Saving Total Energy Utilization of a Building." Journal of Advanced Research in Fluid Mechanics and Thermal Sciences 93, no. 1 (2022): 64–82. http://dx.doi.org/10.37934/arfmts.93.1.6482.

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The paper illustrates the review on the optimizations studies of HVAC systems based on three main methods – HVAC operational variables optimization, optimization of control parameters in HVAC system and parameter optimization in building models. For the HVAC system’s operational variables, the optimization process is based on the common and prescient energy utilization models. Thus, by comparing both, the non-common HVAC system models can get better output of energy reduction. Based on most of the studies, the occupancies thermal comfort requirements, are represented by the indoor air quality

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Zhang, Chi, Linzhang Wang, and Manuel Rigger. "Finding Cross-Rule Optimization Bugs in Datalog Engines." Proceedings of the ACM on Programming Languages 8, OOPSLA1 (2024): 110–36. http://dx.doi.org/10.1145/3649815.

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Datalog is a popular and widely-used declarative logic programming language. Datalog engines apply many cross-rule optimizations; bugs in them can cause incorrect results. To detect such optimization bugs, we propose an automated testing approach called Incremental Rule Evaluation (IRE), which synergistically tackles the test oracle and test case generation problem. The core idea behind the test oracle is to compare the results of an optimized program and a program without cross-rule optimization; any difference indicates a bug in the Datalog engine. Our core insight is that, for an optimized,

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Ni, Haiyan, Jianping Hu, Xuqiang Zhang, and Haotian Zhu. "The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs." Journal of Circuits, Systems and Computers 29, no. 07 (2019): 2050114. http://dx.doi.org/10.1142/s0218126620501145.

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In this paper, a method of optimizing dual-threshold independent-gate FinFET devices is discussed, and the optimal circuit design is carried out by using these optimized devices. Dual-threshold independent-gate FinFETs include low threshold devices and high threshold devices. The low threshold device is equivalent to two merging parallel short-gate devices and high threshold device is equivalent to two merging series SG devices. We optimize the device mainly by selecting the appropriate gate work function, gate oxide thickness, silicon body thickness and so on. Our optimization is based on the

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Manoj Murali. "Power, Performance, and Area-efficient Designs at Lower Nodes: Saving Billions in Semiconductor Manufacturing." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 11, no. 2 (2025): 2168–83. https://doi.org/10.32628/cseit23112577.

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The semiconductor industry faces increasing challenges as technology nodes advance below 7nm, with optimization of power consumption, performance, and silicon area (PPA) becoming critical for financial success. This article explores the journey from Register-Transfer Level code to manufactured silicon, detailing optimization opportunities at each design stage. From RTL design and functional verification through logic synthesis, physical design, and timing closure, each phase offers significant potential for efficiency improvements. The economic implications of these optimizations span across m

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Bowles, Andrew. "Trends in applying abstract interpretation." Knowledge Engineering Review 7, no. 2 (1992): 157–71. http://dx.doi.org/10.1017/s0269888900006275.

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AbstractAbstract interpretation is a principled approach to inferring properties of a program's execution by simulating that execution using an interpreter which computes over some abstraction of the program's usual, concrete domain, and which collects the information of interest during the execution. Abstract interpretation has been used as the basis of research in logic and functional programming, particularly in applications concerned with compiler optimizations. However, abstract interpretation has the potential to be used in other applications, such as debugging or verification of program

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Spriha, Dibbi, and K.B.Ramesh. "DESIGN OF OPTIMIZED ALU." Journal of VLSI Design and its Advancement 7, no. 3 (2024): 26–36. https://doi.org/10.5281/zenodo.13683009.

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<em>The pursuit of enhanced performance and efficiency in digital circuits has led to a continuous evolution of Arithmetic Logic Units (ALUs) – pivotal components in modern processors. This paper explores novel strategies for optimizing ALU design by dissecting the optimization process into key components. We delve into the intricacies of each design aspect, emphasizing the synthesis of Verilog Hardware Description Language (HDL) for simulation and verification.  The objective is to present a comprehensive view of ALU optimization, addressing both speed and power consumption conside

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Al-Rabadi, Anas. "Three-dimensional lattice logic circuits, Part III: Solving 3D volume congestion problem." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 29–43. http://dx.doi.org/10.2298/fuee0501029a.

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This part is a continuation of the first and second parts of my paper. In a previous work, symmetry indices have been related to regular logic circuits for the realization of logic functions. In this paper, a more general treatment that produces 3D regular lattice circuits using operations on symmetry indices is presented. A new decomposition called the Iterative Symmetry Indices Decomposition (ISID) is implemented for the 3D design of lattice circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using

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BOBILLO, FERNANDO, MIGUEL DELGADO, and JUAN GÓMEZ-ROMERO. "CRISP REPRESENTATIONS AND REASONING FOR FUZZY ONTOLOGIES." International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems 17, no. 04 (2009): 501–30. http://dx.doi.org/10.1142/s0218488509006121.

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Classical ontologies are not suitable to represent imprecise nor uncertain pieces of information. Fuzzy Description Logics were born to represent the former type of knowledge, but they require an appropriate fuzzy language to be agreed on and an important number of available resources to be adapted. This paper faces these problems by presenting a reasoning preserving procedure to obtain a crisp representation for a fuzzy extension of the logic [Formula: see text] which includes fuzzy nominals and trapezoidal membership functions, and uses Gödel implication in the semantics of fuzzy concept and

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Zhang, Cheng, Arthur Azevedo de Amorim, and Marco Gaboardi. "On incorrectness logic and Kleene algebra with top and tests." Proceedings of the ACM on Programming Languages 6, POPL (2022): 1–30. http://dx.doi.org/10.1145/3498690.

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Kleene algebra with tests (KAT) is a foundational equational framework for reasoning about programs, which has found applications in program transformations, networking and compiler optimizations, among many other areas. In his seminal work, Kozen proved that KAT subsumes propositional Hoare logic, showing that one can reason about the (partial) correctness of while programs by means of the equational theory of KAT. In this work, we investigate the support that KAT provides for reasoning about incorrectness, instead, as embodied by O'Hearn's recently proposed incorrectness logic. We show that

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Ourahou, Meriem, Wiam Ayrir, and Ali Haddi. "Current correction and fuzzy logic optimizations of Perturb & Observe MPPT technique in photovoltaic panel." International Journal for Simulation and Multidisciplinary Design Optimization 10 (2019): A6. http://dx.doi.org/10.1051/smdo/2019007.

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This paper presents a two-way optimization of the Perturb & Observe (P&O) maximum power point tracking (MPPT) technique using current correction and fuzzy logic techniques. In fact, photovoltaic (PV) energy has become more and more coveted today. In the future, it will become a necessity. To ensure its optimization, maximum operating point tracking method is considered as a technological key in PV systems. One of the most used MPPT methods is the P&O technique. In this paper, we will focus on optimizing this method based on two techniques. A first attempt has been made to estimate

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Moine, Alexandre, Sam Westrick, and Stephanie Balzer. "DisLog: A Separation Logic for Disentanglement." Proceedings of the ACM on Programming Languages 8, POPL (2024): 302–31. http://dx.doi.org/10.1145/3632853.

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Disentanglement is a run-time property of parallel programs that facilitates task-local reasoning about the memory footprint of parallel tasks. In particular, it ensures that a task does not access any memory locations allocated by another concurrently executing task. Disentanglement can be exploited, for example, to implement a high-performance parallel memory manager, such as in the MPL (MaPLe) compiler for Parallel ML. Prior research on disentanglement has focused on the design of optimizations, either trusting the programmer to provide a disentangled program or relying on runtime instrumen

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Martinez, Roylan. "Optimization proposals to the payment clearing." Data Science in Finance and Economics 3, no. 1 (2023): 76–100. http://dx.doi.org/10.3934/dsfe.2023005.

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<abstract><p>In recent years, the amount of payment transactions have exponentially increased and with them, new abstract payment methods and techniques have emerged. In this paper, we provide two new interesting optimization problem solutions aimed to reduce the amount of money needed in a multilateral set-off system. The presented concepts—built upon solutions of relatively new but well-known graph theory and mathematical optimization theory—show how the use of some payment transaction methods can improve the traditional compensation logic behind a payment transaction. These theo

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Cassiers, Gaëtan, Barbara Gigerl, Stefan Mangard, Charles Momin, and Rishub Nagpal. "Compress: Generate Small and Fast Masked Pipelined Circuits." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 3 (2024): 500–529. http://dx.doi.org/10.46586/tches.v2024.i3.500-529.

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Masking is an effective countermeasure against side-channel attacks. It replaces every logic gate in a computation by a gadget that performs the operation over secret sharings of the circuit’s variables. When masking is implemented in hardware, care should be taken to protect against leakage from glitches, which could otherwise undermine the security of masking. This is generally done by adding registers, which stop the propagation of glitches, but introduce additional latency and area cost. In masked pipeline circuits, a high latency further increases the area overheads of masking, due to the

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A. Aruna. "Enhanced Lung Cancer Detection via Modified Fuzzy Analytic Hierarchy Process and FuzSquResMobileNet." Communications on Applied Nonlinear Analysis 31, no. 6s (2024): 499–523. http://dx.doi.org/10.52783/cana.v31.1240.

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Lung cancer emphasizes the vital need of early detection in order to increase survival rates due to its high incidence of death worldwide. An effective methodology for lung cancer detection is proposed utilizing the Modified Fuzzy Analytic Hierarchy Process, a hybrid optimization algorithm. Gaussian filter and a modified Contrast Limited Adaptive Histogram Equalization (CLAHE) are employed for reliable pre-processing. This enhances the image quality and facilitates additional analysis. A novel hybrid ChimpGaz optimization that combines the optimizations of Gazelle and Chimp is employed to fine

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Yang, Chenyuan, Yinlin Deng, Runyu Lu, et al. "WhiteFox: White-Box Compiler Fuzzing Empowered by Large Language Models." Proceedings of the ACM on Programming Languages 8, OOPSLA2 (2024): 709–35. http://dx.doi.org/10.1145/3689736.

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Compiler correctness is crucial, as miscompilation can falsify program behaviors, leading to serious consequences over the software supply chain. In the literature, fuzzing has been extensively studied to uncover compiler defects. However, compiler fuzzing remains challenging: Existing arts focus on black- and grey-box fuzzing, which generates test programs without sufficient understanding of internal compiler behaviors. As such, they often fail to construct test programs to exercise intricate optimizations. Meanwhile, traditional white-box techniques, such as symbolic execution, are computati

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Sasamal, Trailokya Nath, Anand Mohan, and Ashutosh Kumar Singh. "Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata." Journal of Circuits, Systems and Computers 27, no. 02 (2017): 1850021. http://dx.doi.org/10.1142/s0218126618500214.

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Quantum-dot Cellular Automata (QCA) based reversible logic is the utmost necessity to achieve an architecture at nano-scale, which promises extremely low power consumption with high device density and faster computation. This paper emphasises on the design of an efficient reversible Arithmetic Logical Unit (ALU) block in QCA technology. We have considered [Formula: see text] RUG (Reversible Universal Gate) as the basic unit, and also report a HDLQ model for RUG with 52.2% fault tolerance capability. Further, the reversible ALU has synthesized with reversible logic unit (RLU) and reversible ari

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Saabas, Ando, and Tarmo Uustalu. "Program and proof optimizations with type systems." Journal of Logic and Algebraic Programming 77, no. 1-2 (2008): 131–54. http://dx.doi.org/10.1016/j.jlap.2008.05.007.

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Zhao, Lingying, Min Ye, and Xinxin Xu. "Intelligent optimization of EV comfort based on a cooperative braking system." Proceedings of the Institution of Mechanical Engineers, Part D: Journal of Automobile Engineering 235, no. 10-11 (2021): 2904–16. http://dx.doi.org/10.1177/09544070211004461.

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To address the comfort of an electric vehicle, a coupling mechanism between mechanical friction braking and electric regenerative braking was studied. A cooperative braking system model was established, and comprehensive simulations and system optimizations were carried out. The performance of the cooperative braking system was analyzed. The distribution of the braking force was optimized by an intelligent method, and the distribution of a braking force logic diagram based on comfort was proposed. Using an intelligent algorithm, the braking force was distributed between the two braking systems

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Gunay, Noel S., and Elmer P. Dadios. "An Optimized Multi-Output Fuzzy Logic Controller for Real-Time Control." Journal of Advanced Computational Intelligence and Intelligent Informatics 12, no. 4 (2008): 370–76. http://dx.doi.org/10.20965/jaciii.2008.p0370.

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Any real-time control application run by a digital computer (or any sequential machine) demands a very fast processor in order to make the time-lag from data sensing to issuance of a control action closest to zero. In some instances, the algorithm used requires a relatively large primary memory which is crucial especially when implemented in a microcontroller. This paper presents a novel implementation of a multi-output fuzzy controller (which is known in this paper as MultiOFuz), which utilizes lesser memory and executes faster than a type of an existing multiple single-output fuzzy logic con

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RIGUZZI, FABRIZIO, and TERRANCE SWIFT. "The PITA system: Tabling and answer subsumption for reasoning under uncertainty." Theory and Practice of Logic Programming 11, no. 4-5 (2011): 433–49. http://dx.doi.org/10.1017/s147106841100010x.

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AbstractMany real world domains require the representation of a measure of uncertainty. The most common such representation is probability, and the combination of probability with logic programs has given rise to the field of Probabilistic Logic Programming (PLP), leading to languages such as the Independent Choice Logic, Logic Programs with Annotated Disjunctions (LPADs), Problog, PRISM, and others. These languages share a similar distribution semantics, and methods have been devised to translate programs between these languages. The complexity of computing the probability of queries to these

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Ly, Hai-Bang, Lu Minh Le, Luong Van Phi, et al. "Development of an AI Model to Measure Traffic Air Pollution from Multisensor and Weather Data." Sensors 19, no. 22 (2019): 4941. http://dx.doi.org/10.3390/s19224941.

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Gas multisensor devices offer an effective approach to monitor air pollution, which has become a pandemic in many cities, especially because of transport emissions. To be reliable, properly trained models need to be developed that combine output from sensors with weather data; however, many factors can affect the accuracy of the models. The main objective of this study was to explore the impact of several input variables in training different air quality indexes using fuzzy logic combined with two metaheuristic optimizations: simulated annealing (SA) and particle swarm optimization (PSO). In t

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Subramanyam, Radha, S. Rekha, P. Nagabushanam, and Sai Krishna Kondoju. "Optimization Techniques in Cooperative and Distributed MAC Protocols." International Journal of Intelligent Information Technologies 20, no. 1 (2024): 1–23. http://dx.doi.org/10.4018/ijiit.335523.

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The tremendous increase in wireless network application finds distributed allocation of resources allocation very useful in the network. Packet delivery ratio and delay can be improved by concentrating on payload size, mobility, and density of nodes in the network. In this article, a survey is carried out on different cooperative and distributed MAC protocols for communication and optimization algorithms for various applications and the mathematical issues related to game theory optimizations in MAC protocol. Spatial reuse of channel improved by (3-29) % and multi-channel improves throughput b

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Abdelmassih, Gorg, Mohammed Al-Numay, and Abdelali El Aroudi. "Map Optimization Fuzzy Logic Framework in Wind Turbine Site Selection with Application to the USA Wind Farms." Energies 14, no. 19 (2021): 6127. http://dx.doi.org/10.3390/en14196127.

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In this study, we analyze observational and predicted wind energy datasets of the lower 48 states of the United States, and we intend to predict an optimal map for new turbines placement. Several approaches have been implemented to investigate the correlation between current wind power stations, power capacity, wind seasonality, and site selection. The correlation between stations is carried out according to Pearson correlation coefficient approach joined with the spherical law of cosines to calculate the distances. The high correlation values between the stations spaced within a distance of 1

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Ibraheem, Kais I., and Hisham M. Khudhur. "Optimization algorithm based on the Euler method for solving fuzzy nonlinear equations." Eastern-European Journal of Enterprise Technologies 1, no. 4 (115) (2022): 13–19. http://dx.doi.org/10.15587/1729-4061.2022.252014.

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In a variety of engineering, scientific challenges, mathematics, chemistry, physics, biology, machine learning, deep learning, regression classification, computer science, programming, artificial intelligence, in the military, medical and engineering industries, robotics and smart cars, fuzzy nonlinear equations play a critical role. As a result, in this paper, an Optimization Algorithm based on the Euler Method approach for solving fuzzy nonlinear equations is proposed. In mathematics and computer science, the Euler approach (sometimes called the forward Euler method) is a first-order numeric

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Kais, I. Ibraheem, and M. Khudhur Hisham. "Optimization algorithm based on the Euler method for solving fuzzy nonlinear equations." Eastern-European Journal of Enterprise Technologies 1, no. 4 (115) (2022): 13–19. https://doi.org/10.15587/1729-4061.2022.252014.

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In a variety of engineering, scientific challenges, mathematics, chemistry, physics, biology, machine learning, deep learning, regression classification, computer science, programming, artificial intelligence, in the military, medical and engineering industries, robotics and smart cars, fuzzy nonlinear equations play a critical role. As a result, in this paper, an Optimization Algorithm based on the Euler Method approach for solving fuzzy nonlinear equations is proposed. In mathematics and computer science, the Euler approach (sometimes called the forward Euler method) is a first-order numeric

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Rajkumar, G., M. Saravanan, A. Bovas Herbert Bejaxhin, et al. "Parametric Optimization of Powder-Mixed EDM of AA2014/Si3N4/Mg/Cenosphere Hybrid Composites Using Fuzzy Logic: Analysis of Mechanical, Machining, Microstructural, and Morphological Characterizations." Journal of Composites Science 7, no. 9 (2023): 380. http://dx.doi.org/10.3390/jcs7090380.

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This research focuses on a comprehensive exploration of the experimental and mechanical aspects of the electrical discharge machining (EDM) process, specifically targeting the machining characteristics of AA2014/Si3N4/Mg/cenosphere hybrid composites. The aim is to optimize the process parameters for enhanced machining performance through a combination of testing, optimization, and modelling methodologies. The study examines the effects of key EDM variables—peak current, pulse on time, and pulse off time—on critical output responses: surface roughness (Ra), electrode wear rate (EWR), and materi

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Yordanova, Snejana. "Industrial Design of Type-1 and Interval Type-2 Fuzzy Logic Control." Jordan Journal of Electrical Engineering 11, no. 1 (2025): 1. http://dx.doi.org/10.5455/jjee.204-1720610452.

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This paper focuses on the design of type-1 and interval type-2 (IT2) PID fuzzy logic controllers (FLC) for ensuring - by a programmable logic controller (PLC) - a high-performance real-time liquid level control in a carbonization column (CCl) for soda production. Firstly, Takagi-Sugeno-Kang models - derived via genetic algorithms parameter optimizations, experimental data and simulations for the basic and the worst CCl loads - are studied at different operation points, and the worst Ziegler-Nichols (ZN) model is assessed. Next, two-input fuzzy units are designed - assuming various membership f

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