Dissertationen zum Thema „Interconnexions (Technologie des circuits intégrés)“
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Delorme, Nicolas. „Influence des interconnexions sur les performances des circuits intégrés silicium en technologie largement submicronique“. Grenoble INPG, 1997. http://www.theses.fr/1997INPG0173.
Der volle Inhalt der QuelleDoyen, Lise. „Caractérisation électrique de l'endommagement par électromigration des interconnexions en cuivre pour les technologies avancées de la microélectronique“. Grenoble 1, 2009. http://www.theses.fr/2009GRE10036.
Der volle Inhalt der QuelleCopper interconnect degradation due to electromigration is one of the major concern of integrated circuit reliability. New characterization techniques are needed in addition to the standard lifetime tests, in order to increase our knowledge on this degradation phenomenon. In this study, the growth of electromigration induced voids is followed by analyzing evolution of interconnect resistance with time. Effects of, first, the line cross-section and the temperature and, second, of the current density and the line length, have been investigated. It has thus been shown that resistance evolution analysis is a pertinent method to study degradation kinetics and extract characteristic parameters such as the activation energy of mechanism. Moreover, we have highlighted the influence of the void size and shape on the failure time, particularly important on short lines
Yu, Raofeng. „Estimation de haut niveau de placement et des interconnexions de circuits VLSI submicroniques“. Rennes 1, 2002. http://www.theses.fr/2001REN10032.
Der volle Inhalt der QuelleArnal, Vincent. „Intégration et caractérisation des performances de l'isolation par cavités des interconnexions en cuivre pour les technologies CMOS sub 90 nm“. Chambéry, 2002. http://www.theses.fr/2002CHAMS010.
Der volle Inhalt der QuelleSignal transmission along interconnects become critical in integrated circuits due to the increase of components density and clock frequency. Indeed, signal propagation time and crosstalk between adjacent lines are drivung performances and may generate logical faults. To overcome these limitations, copper interconnects have to be isolated by low permittivity dielectrics, known as "low k", instead of silicon oxide which relative dielectric constant is 4,2. In this study, we have developed a new approach where conventional dielectrics, for instance silicon oxide, continue to be integrated. But in this case, the non-conformal PECVD deposition process is taken into advantage to create cavities where they are really needed ie : between lines which are the most close. The major goal of the technique is to obtain an equivalent dielectric insulation with a permittivity below 2 by creating cavities between metal lines. This method is feasible if a selective and local integration of cavities is applied, making the deposition process uniform whatever dimensions of the circuit are. For that, a specific lithographiy mask is used, it defines placement of cavities in respect with design rules preliminary defined. The integration is carried out in a copper damascene architecture with several levels in order to check electrical parameters and reliability of interconnects. To characterize performances of a such insulation technique, coupling capacitances between lines are simulated and measured in order to extract an equivalent permittivity. Characterization continues by the study of signal propagation in isolated and coupled transmission lines in frequency domain up to 40 GHz. Insulation by cavity impacts significantly the reduction of crosstalk and crosstalk induced delay in comparison with homogeneous dielectrics. These results demonstrate the great potential of the technique to achieve required performances for sub 90 nm CMOS technologies
Jani, Imed. „Test et caractérisation des interconnexions 3D haute densité“. Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT094.
Der volle Inhalt der QuelleThe integration of multiple chips in a 3D stack serves as another path to move forward in the more-than-Moore domain. 3D integration technology consists in interconnecting the integrated circuits in three dimensions using inter-die interconnects (μ-bumps or Cu-Cu interconnects) and Through Silicon Vias (TSV). This changeover from horizontal to vertical interconnection is very promising in terms of speed and overall performances (RC delay, power consumption and form factor). On the other side, for technology development of 3D integration before the production of the 300 mm wafers with all FEOL and BEOL layers, several short-loops must been carried out to enable incremental characterization and structural test of 3D interconnects in order to evaluate the electrical performances (R, L, C …). In the other hand, the test of application circuits consists in adding testability features (Boundary-Scan-Cells (BSCs), Built-In-Self-Test (BIST) and scan chains …) for functional test of the hardware product design (including the different stacked dies and the 3D interconnections) . The added Design-For-Test (DFT) architecture make it easier to develop and apply manufacturing tests to the designed hardware. Compared to μ-bumps, Cu-Cu hybrid bonding provides an alternative for future scaling below 10μm pitch with improved physical properties but that generates new challenges for test and characterization; the smaller the Cu pad size, the more the fabrication and bonding defects have an important impact on yield and performance. Defects such as bonding misalignment, micro-voids and contact defects at the copper surface, can affect the electrical characteristics and the life time of 3D-IC considerably. Moreover, test infrastructure insertion for HD 3D-ICs presents new challenges because of the high interconnects density and the area cost for test features. Hence, in this thesis work, an innovative misalignment test structure has been developed and implemented in short-loop way. The proposed approach allows to measure accurately bonding misalignment, know the misalignment direction and estimate the contact resistance. Afterwards, a theoretical study has been performed to define the most optimized DFT infrastructure depending on the minimum acceptable pitch value for a given technology node to ensure the testability of high-density 3D-ICs. Furthermore, an optimized DFT architecture allowing pre-bond and post-bond for high-bandwidth and high-density 3D-IC application (SRAM-on-Logic) has been proposed. Finally, to assess performance of HD 3D-ICs, two complementary BISTs has been implemented in an application circuit using the same misalignment test structure developed above and a daisy chain of Cu-Cu interconnects. Using test results, on the one hand, the impact of misalignment defect on the propagation delay has been studied and on the other hand full open and μ-voids defects at the contact surface level has been detected
Bouazzati, Karim El. „Contribution à la modélisation électrique des interconnexions "cuivre" dans les circuits intégrés ULSI : application aux technologies 0.25, 0.13 microns et 70 nanomètres“. Lille 1, 2005. https://pepite-depot.univ-lille.fr/RESTREINT/Th_Num/2005/50376-2005-87.pdf.
Der volle Inhalt der QuelleTlili, Malika. „Modules intégrés en technologie LTCC pour des applications en bande D (110 - 170 GHz)“. Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2020. http://www.theses.fr/2020IMTA0165.
Der volle Inhalt der QuelleThis thesis has as objective to realize low cost front-end TRX modules, in D-band (110-170 GHz), using MMIC chips integrated on an LTCC substrate. The applications at these frequencies are various: imaging (security) by deploying high-resolution scanners, automotive assistance radars, radiometry or the backhaul of the 5G telephony network. At very high frequencies, the packaging is generally made of metal structures, which makes it expensive, bulky and relatively long to manufacture. Packaging solutions based on LTCC technology have been proposed and developped during the thesis with the objective of maintaining the intrinsic performance of chips before integration. To integrate the MMIC chips on th LTCC support, various aspects have been studied and validated experimentally, with the difficulties in measurement inherent to these very high operating frequencies. These are in particular interconnection techniques for connecting the RF access pads of the chip to the pads on the subtrate and the thermal solution to limit the heating of certain chips, such as the power amplifier, which can cause a malfunction of even failure of the module. The establishement of th DC blasing networks of active chips is also a crucial point in the design of the packaging since they must not interferer with the RF accesses
Vayrette, Renaud. „Analyse des contraintes mecaniques et de la resistivite des interconnexions de cuivre des circuits integres : role de la microstructure et du confinement geometrique“. Thesis, Saint-Etienne, EMSE, 2011. http://www.theses.fr/2011EMSE0599/document.
Der volle Inhalt der QuelleThe evolution of the microelectronic technology leads to a transistors integration density always stronger. The Damascene copper interconnections structures follow this tendency and must be controlled in terms of manufacturing, performance and robustness, these different aspects being intimately related to the residual stresses and resistivity. This thesis aims to understand the mechanisms of the residual stresses generation and identify the different contributions to the resistivity of these objects as a function of annealing conditions and dimensions (from about a hundred of nm to several µm). In order to do this, the respective effects of the microstructure and dimensions of electroplated copper films and lines were separated on the basis of analytical models integrating microstructural and geometrical parameters. The microstructure was principally analysed from mappings of crystalline orientations achieved by EBSD. For the copper lines of width 0.2 and 1 µm, the residual stresses were deduced from the exploitation of nano-rotating sensors specially elaborated. The results obtained show that independently of the annealing temperature, the resistivity and residual stresses increase observed toward the small dimensions arises from the diminution of the average crystallites size and the geometrical confinement more pronounced. Furthermore, the resistivity increase results also of the electrons reflection probability growth at grains boundaries. This last point was associated to the reduction of the proportion of special grains boundaries having a high atomic coherency
Sanseau, Pierre. „Etude de polymères thermostables pour l'isolation des interconnexions dans les circuits intégrés“. Grenoble 1, 1988. http://www.theses.fr/1988GRE10021.
Der volle Inhalt der QuelleOrtiz, Salvador. „Modélisation physique des effets électromagnetiques pour les interconnexions dans les circuits intégrés“. Phd thesis, Grenoble 1, 2007. http://www.theses.fr/2007GRE10103.
Der volle Inhalt der QuelleThree problems dealing with the modeling of wires in integrated circuits are considered: (i) fast and efficient calculation for mutual inductance, using the dipole approximation; (ii) compact expansion of non-uniform currents in conductors at high frequencies, in terms of conduction modes; and (iii) accurate representation of frequency dependent resistance-inductance behavior with constant circuit parameters, in the form of Foster pairs. We propose and implement solutions and optimizations for these problems based on simple physical arguments. All three problems are integrated within Mentor Graphic's extraction tools
Ortiz, Salvador. „Modélisation physique des effets électromagnetiques pour les interconnexions dans les circuits intégrés“. Phd thesis, Université Joseph Fourier (Grenoble), 2007. http://tel.archives-ouvertes.fr/tel-00165969.
Der volle Inhalt der QuelleServel, Grégory. „Effets parasites dus aux interconnexions“. Montpellier 2, 2001. http://www.theses.fr/2001MON20037.
Der volle Inhalt der QuelleBaratte, Hervé. „Technologie bipolaire hétérojonction AlGaAs/GaAs pour circuits intégrés“. Paris 11, 1985. http://www.theses.fr/1985PA112012.
Der volle Inhalt der QuelleThe good injection properties of the heterojunction bipolar transistor allow predicting very high frequency performance of the device. An ion-implanted double hétérostructure with graded junctions is well adapted for integrated circuits application. An analytic model, close to reality, helps calibrate an optimized structure. It is also a convenient tool to correlate observed performance to the device internal structure. The epitaxial growth sequence is rather complicated because of the presence of two different heterojunctions (AlGaAs/GaAs and GaAs/AlGaAs) and of two types of dopants (Silicium for n-type and Beryllium for p-type). Thanks to a GaAs none intentionally doped interfacial layer, recombination effects in the junctions are greatly reduced. Then, a rapid thermal annealing treatment of the implanted devices proves to be a suitable method to achieve good activation efficiency while limiting dopants diffusion inside the structure. Further integration of such a device is then analyzed. Very high speed and high density of integration are predicted for future I²L or ELC bipolar heterostructures. The HBT (Heterojunction Bipolar Transistor) is also well adapted for linear application
David, Lauréline. „Modélisation des effets inductifs parasites dans les interconnexions des circuits numériques avancés“. Brest, 2006. http://www.theses.fr/2006BRES2038.
Der volle Inhalt der QuelleWith the increase of digital design complexity and operating frequency, on-chip interconnect parasitics become critical for efficient design. Today, only parasitic RC are extracted and analyzed in automated design flows. Nevertheless, the effect of inductance on propagation delays is no more negligible as the clock frequeney goes beyond one gigahertz. The purpose of this work is the understanding and modeling of parasitic inductances to provide concrete and relevant means to take them in account. Thus, various approaches for inductance extraction are compared and the evaluation of the CAD tools that can be used for interconnect extraction or modeling is drawn up. As a consequence, it appears that new general models are required. Models are therefore developed on the basis of several assumptions which are systematically validated. Frequency effects (skin and proximity effect) and current retum path issues are particularly detailed. This modeling process leads to pre-layout corner models allowing the estimation of minimal and maximal inductance values, in very early stages of the design flow. The suggested models are correlated with experiments, thanks to an original ring-oscillator test-structure. Finally, these models are applied to practical examples, and solutions to consider inductive effects in digital design flows are discussed. During this study, simple and efficient models have been developed and validated to consider inductive effects in the complex environment of a digital circuit
Telescu, Mihai. „Modélisation d'ordre réduit des interconnexions de circuits VLSI“. Brest, 2007. http://www.theses.fr/2007BRES2038.
Der volle Inhalt der QuelleLntegrated circuit designers are showing a growing interest in the effects of interconnect structures. Taking these effects into consideration during simulations has become a major goal. The main objective of this PhD was the development new model order reduction mathematical tools. VLSI interconnect applications were our main priority. Our model order reduction strategy supposes an initial modeling of the origjnal system using either a Laguerre or a Kautz representation. This manuscript contains a synthetic presentation 0f these orthogonal function bases. The five order reduction methods studied during this PhD are then presented. We make available several examples of application of methods to interconnect lines. Weillçistate, among other aspects, the possibility of obtaining Iow complexity equivalent circuits from our models and the possibility of performing reduced order modeling directly from data provided by full-wave simulation
Sellaye, Sellambaye Jean-Marie. „Comparaison des interconnexions électriques et optoélectroniques au niveau intrapuce“. Toulouse, INSA, 2002. http://www.theses.fr/2002ISAT0031.
Der volle Inhalt der QuelleThis thesis aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects (EIs) at chip level in the next ten years. We first simulate the response of future electrical interconnects considering the reduction of the CMOS feature size (lambda) from 0. 7 to 0. 05 micron. We conclude that : 1) There is no intrinsic bandwidth limitation of long EIs. 2) Regarding the latency and the power consumption, it does not seem necessary in the future chips to consider the integration of optical interconnects (OIs) over distances shorter than 1000-2000 lambda. 3) The penetration of OIs over distances longer than 10000?lambda could be envisaged provided that news technological generations could develop low-threshold high-efficiency VCSELs and ultra-fast high-efficiency photodiodes. 4) The first possible application of onchip OIs is most likely for clock distribution
Farcy, Alexis. „Optimisation des performances électriques appliquée aux interconnexions des circuits intégrés en présence de variabilité“. Chambéry, 2009. http://www.theses.fr/2009CHAMS040.
Der volle Inhalt der QuelleThe contribution of interconnects to overal1 integrated circuit performance is increasing as lines and vias dimensions scale down. Designers' work is now impacted by technological constraints such as Cu resistivity increase or process variability, which affect electrical properties of interconnects. The development of innovative processes and materials in a limited time frame to ensure economical viability of each new generation is absolutely mandatory. This study aims at developing a methodology to predict the real impact of technological solutions on interconnect propagation performance in order to identify the most suitable solutions. After a review of the main innovations under development, the methodology proposed to predict the dependence of signal transmission on technological stack properties and process variability is presented. This approach is then applied to the case of the 32 nm technological node. The experimental results obtained based on the analysis of real circuits to define realistic simulation conditions lead to the extraction of analytic models suitable for statistical analysis. An optimisation of interconnect technological stack is then performed taking into account process variability to identify the most promising technological solutions to reach the required electrical specifications
Wei, Dong Bei. „Conception d'inductances actives en technologie monolithique microondes“. Châtenay-Malabry, Ecole centrale de Paris, 1993. http://www.theses.fr/1993ECAP0300.
Der volle Inhalt der QuelleVanier, Eric. „Caractérisation et optimisation temporelles des interconnexions dans les circuits sub-microniques CMOS“. Montpellier 2, 1998. http://www.theses.fr/1998MON20126.
Der volle Inhalt der QuelleDerème, Tristan. „Test en tension des courts-circuits en technologie CMOS“. Montpellier 2, 1995. http://www.theses.fr/1995MON20032.
Der volle Inhalt der QuelleBermond, Cédric. „Caractérisation et modélisation des effets parasites liés aux interconnexions sur les performances électriques des circuits intégrés ultra-rapides“. Chambéry, 2001. http://www.theses.fr/2001CHAMS023.
Der volle Inhalt der QuellePutot, Sylvie. „Calcul des capacités parasites dans les interconnexions des circuits intégrés par une méthode de domaines fictifs“. Phd thesis, Université Joseph Fourier (Grenoble ; 1971-2015), 2001. http://www.theses.fr/2001GRE10015.
Der volle Inhalt der QuelleTriantafyllou, Anna. „Etude, réalisation et caractérisation d'interconnexions radiofréquences pour les circuits intégrés silicium des générations à venir“. Université Joseph Fourier (Grenoble), 2006. http://www.theses.fr/2006GRE10049.
Der volle Inhalt der QuelleThe evolution that principally characterises the microelectronics sector is the reduction of integrated circuits dimensions. Semiconductors industry has not stopped to improve its products by increasing integration density and operation speed. However the reduced dimensions effects are not limited to a scaling factor as physical and technological limitations create new constraints. Between them, the limitations induced by the miniaturization of interconnects networks become a limiting factor for the performances of future generations integrated circuits. Signals propagation delay, power and surface consumption are the elements that drive to proposal of alternative interconnect systems above the copper and the low k materials. The feasibility of radio frequency interconnections is evaluated during this study as an alternative solution to the traditional interconnects limitations. The transmission of information via electromagnetic waves emitted and detected by integrated antennas, could solve the problem of signals propagation delay and allow to reduce the occupied surface and the consumed power. Integrated antenna performances are studied by theoretical and experimental means in the frequency range of 10 GHz to 40 GHz. Materials impact in transmitted power is analysed. Measurements realized in the prototypes of dipole antennas show an excellent transmission gain of approximately –10 dB
Aboudou, Abderraouf. „Application de la photodétection dans les circuits intégrés III-V pour le contrôle optique d'un circuit logique“. Lille 1, 1991. http://www.theses.fr/1991LIL10053.
Der volle Inhalt der QuelleCette étude préliminaire nous a permis de réaliser un deuxième diviseur où cette fois-ci l'emplacement et la structure géométrique du photoconducteur ont été optimisés, de sorte que la division par deux a pu être effectuée jusqu'à 1. 2GHz avec une puissance optique modulée minimale de l'ordre de 500 nW seulement. Dans le quatrième chapitre, nous remplaçons dans le circuit intégré, le photoconducteur par un MSM GaAlAs/GaAs/GaAs de structure géométrique semblable. Ici aussi la division par deux est effectuée jusqu'à 1. 2 GHz avec le même seuil de puissance optique. L'un des enseignements que l'on peut tirer de cette étude est le comportement quasi-identique des deux photodétecteurs en hautes fréquences. Dans le cinquième chapitre, nous démontrons expérimentalement, après l'avoir valider théoriquement, la faisabilité d'un MSM GaAs intégré monolithiquement à un guide optique diélectrique Si3N4/SiO2. Les résultats obtenus sont très encourageants et laissent envisager la possibilité de réaliser un circuit numérique commandé optiquement et dont la distribution du signal optique s'effectue à l'aide de guides diélectriques
Barbier, Frédéric. „Amélioration de la protection des circuits intégrés réalisés en technologie CMOS et BICMOS vis-à-vis des décharges électrostatiques“. Caen, 2005. http://www.theses.fr/2005CAEN2026.
Der volle Inhalt der QuelleKAZEMINEJAD, ABDOL AMIR. „Etude et conception des circuits de test en technologie bipolaire gaas“. Paris 7, 1989. http://www.theses.fr/1989PA077154.
Der volle Inhalt der QuelleLefebvre, Sidonie. „Etude expérimentale et simulation numérique du comportement mécanique de structures sub-micrométriques de cuivre : application aux interconnexions dans les circuits intégrés“. Châtenay-Malabry, Ecole centrale de Paris, 2006. http://www.theses.fr/2006ECAP1077.
Der volle Inhalt der QuelleDandache, Abbas. „Conception de PLA CMOS“. Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
Der volle Inhalt der QuelleBoret, Samuel. „Circuits intégrés monolithiques en technologie coplanaire pour applications de réception jusque 110 GHz“. Lille 1, 1999. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/1999/50376-1999-213.pdf.
Der volle Inhalt der QuelleAprès la réalisation technologique d'une bibliothèque complète d'éléments passifs coplanaires, nous proposons des modèles analytiques paramétrables, valables jusque dans le domaine millimétrique, pour les principales discontinuités coplanaires. Ces modèles sont validés par comparaison avec des résultats expérimentaux (mesure de paramètres s jusque 110 GHz) ainsi que par des résultats de simulations électromagnétiques 3D. Deux circuits amplificateurs faible bruit à 60 GHz et 94 GHz basés sur une technologie 0. 1 µm LM-HEMT sur InP sont présentés. Ces circuits, réalisés dans la centrale de technologie du laboratoire, constituent l'une des premières réalisations de LNA millimétriques en technologie coplanaire sur InP. En très bon accord avec les prédictions, les meilleures performances mesurées sont des facteurs de bruit/gains associés de 4 dB/14. 4 dB à 60 GHz et 3. 3 dB/11. 9 dB à 94 GHz. Ces résultats valident et montrent l'efficacité des modèles développés dans ce mémoire pour la conception de circuits intégrés jusque 110 GHz
Puyal, Vincent. „Conception de circuits intégrés pour les télécommunications optiques en technologie TBdH InP“. Montpellier 2, 2007. http://www.theses.fr/2007MON20164.
Der volle Inhalt der QuelleThis work presents various high-speed design results in the InP DHBT technology of the III-V Alcatel Thales laboratory. The main goal is an IC speed improvement to develop optical network capacity and also to reduce (or to control) their cost. This maximum high operation frequency search is based on an improvement of design techniques and on several design innovations for electric diagram to layout. In the first time, basic cells have been realized: a 60-GHz static divider, a 120-GHz frequency doubler and a 40-Gb/s XOR. In the second time, it was capital to validate more complex digital functions, with the aim of transceiver reduced-scale integration. So, in order to implement a CDR, a digital phase detector have been designed and validated at 40 Gb/s. The different designed and measured circuits show state-of-the-art circuit performances. They could be use in 40-Gb/s future optical networks
Kenmei, Nganguem II Louis Bertrand. „Mise en oeuvre d'une méthode d'éléments finis à éléments d'arêtes en deux et trois dimensions : applications aux lignes de topologies complexes pour circuits intégrés monolithiques micro-ondes et aux interconnexions sur circuit silicium“. Lille 1, 1999. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/1999/50376-1999-215.pdf.
Der volle Inhalt der QuellePorcher, Arnaud. „Silicium poreux pour capteurs et MEMS résonants intégrés“. Lyon, INSA, 2009. http://theses.insa-lyon.fr/publication/2009ISAL0019/these.pdf.
Der volle Inhalt der QuelleOur work takes part in the integration of new functionalities on the elementary miniaturized devices built using silicon micro technologies and designed to enable sensor or actuator abilities. The well-known dielectric properties of the meso-porous silicon (SiP), which can be integrated in thick layers (up to 400 µm), make this material a good candidate to enhance the electric insulation of the device in the RF regime. Among the main results of this work, an original method to electrically characterize the SiP has been performed by a coupling between experimental measurements and numerical simulations with finite elements. By this way, the frequency variation of the electrical conductivity of the SiP has been highlighted and quantified in a range coming from 100 MHz to 1 GHz. Many ways to optimize micro-resonator devices have been thus demonstrated using the oxidation of SiP, its combination with a SiO2 layer, or a double-sided architecture. The realization of sensitive porous membranes allowed us to mechanically characterize the low stiffness of the SiP which has been evaluated for the first time with the direct method of the bulge-test. A Young's modulus of 5 GPa for a porosity of 73% has been measured, what is in good agreements with the analytical models previously developed by members of our team. The integration of inductive elements on composite membranes brings us to obtain two kinds of actuation of the membranes depending on the frequency range: Electro thermal actuation at few Hz and electromagnetic one around 10 kHz. The integration of porosified zones in such structures open important perspectives to enhance their capabilities in term of sensitivity and energetic budget
Abdeslam, Saad. „Etude des effets thermiques, structuraux et mécaniques sur la fiabilité des interconnexions des circuits intégrés par simulation numérique“. Lyon, INSA, 1993. http://www.theses.fr/1993ISAL0001.
Der volle Inhalt der QuelleAs the complexity of integrated circuits and their size shrinking increase, the VLSI reliability become impacted by interconnections. The physical process leading to damage is electro migration or mass transport induces by direct current. Inhomogeneities in the microstructure, geometry, or thermal of flux lead to hillocks and void formation and increase of the electrical resistance. The lifetime measurments are performed under accelerated test conditions and it is necessary to be able to extrapolate the lifetime values down to standard device operating conditions. Simulations of interconnection failure, principal topic of our study, allow to separate structural and mechanical effects by balancing in each section of the conductor line the relevant mass flow with thickness variation. The thermal study give essential rules to respect during the analysis of electromigration data. The structural study minus fairly well the experimental scattering of lifetime data and allows us to attribute this dispersion to microstructure inhomogeneities. Finally, the mechanical study reproduces the beneficial effect of passivation layers. Passivation layers lead to an increase in the lifetime and a decrease in the time to failure standard deviation
Remiat, Bruno. „Couches minces diélectriques à faible et très faible permittivité destinées aux interconnexions des circuits intégrés : élaboration - caractérisation - intégration“. Montpellier 2, 2003. http://www.theses.fr/2003MON20121.
Der volle Inhalt der QuelleMieyeville, Fabien. „Modélisation de liaisons optiques inter- et intra-puces à haut débit“. Ecully, Ecole centrale de Lyon, 2001. http://www.theses.fr/2001ECDL0018.
Der volle Inhalt der QuelleOuattara, Boukary. „Prévision des effets de vieillissement par électromigration dans les circuits intégrés CMOS en noeuds technologiques submicroniques“. Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066253/document.
Der volle Inhalt der QuelleElectromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the reduction of interconnect dimensions in particular. It is identified as one of the critical reliability phenomenon for integrated circuits designed in submicron technologies. The methods of checking this phenomenon at design level are mostly based on current density rules and temperature. These rules are becoming difficult to implement due to increasing current density in interconnection network. This thesis is based on researching for ways to improve detection of electromigration risks at design level. The goal is to establish a relation between electrical rules and interconnect degradation mechanism. Results obtained from ageing tests permit us to relax current limit without altered circuit lifetimes. Finally, this project has been instrumental to define design rules based on optimization of clock tree cells placement in integrated circuit power grid. The application of solution proposed during this work permit to design robust circuits toward EMG
Desèvedavy, Jennifer. „Conception de circuits intégrés radiofréquences reconfigurables en technologie FD-SOI pour application IoT“. Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0177/document.
Der volle Inhalt der QuelleCommunicating objects are inviting themselves into daily life leading to digitization of the physical world. This explosion of multimedia wireless applications for consumer electronics makes the power consumption a key metric in the design of multi-mode wireless portable devices. Conventional transceivers have fixed performances and are designed to meet high performances in all wireless link conditions. However, most of the time, the channel of communication is not at worst case and these transceivers are therefore over specified. Being aware of the channel link conditions would allow such devices to adapt themselves and to reduce significantly their power consumption. Therefore, the challenge is to propose a QoS (Quality of Service) in terms of communication range, response time as instance, equivalent to industrial modules with a reduced overall power consumption.To address this purpose, this thesis proposes a design strategy for the implementation of adaptive radio-frequency receiver (Rx) modules. Hence the Rx front end achieves the correct QoS for various scenarii of communications with a minimum of power consumption.As a proof of concept, the adaptive approach is demonstrated with the design of a tunable LNA (Low Noise Amplifier). As the first element of the receiver chain, the LNA limits the receiver in terms of sensitivity and is therefore a good candidate to perform reconfiguration. The body biasing of the FD-SOI (Fully Depleted Silicon-On-Insulator) technology is first exploited to reduce the power consumption of a circuit and then as an opportunity to perform circuit tunability
Fang, Cheng. „Croisssance électrolytique du cuivre appliquée à la technologie "system-in-package"“. Rennes, INSA, 2011. http://www.theses.fr/2011ISAR0003.
Der volle Inhalt der QuelleThis thesis consists of developing a copper electroplating process (ECD) in order to realize the through-silicon-vias (TSVs) inside a “System-in-Package” developed by NXP Semiconductors. The ECD process was performed onto 6-inch wafers coated by a copper seed layer in an industrial tool. The electrolyte is composed of the copper sulfate, the acid sulfuric, the acid chloride and three specific additives (JBG, SPS and PEG). The plating current parameters were first assessed. We have found that the pulsed current is more suitable for the microvias filling than the direct current. Other influential parameters especially such as hydrodynamic environment were evaluated as well. We have found that the perpendicular electrolyte flow is crucial to enhance the microvias filling
Jeannot, Simon. „Développement de matériaux déposés par PECVD pour les interconnexions optiques dans les circuits intégrés par une approche "back-end"“. Lyon, INSA, 2006. http://theses.insa-lyon.fr/publication/2006ISAL0042/these.pdf.
Der volle Inhalt der QuelleIn this thesis, we are interested in the use of a generalized cylinder state model for semi-automatic analysis of three-dimensional vascular images. This model is used on two levels: for image segmentation and quantification of the stenosis degree. The model is introduced in a vessel tracking strategy based on the Kalman state estimator, associated with the segmentation of plane contours by the level sets algorithm known as ``fast marching''. The interpretation of the model as a continuous geometrical object grants access to the analytical formulas used for stenosis quantification such as diameters and transversal areas. The algorithm was evaluated on a basis of 6 physical phantoms imaged in computed tomography angiography and in magnetic resonance angiography
Ouattara, Boukary. „Prévision des effets de vieillissement par électromigration dans les circuits intégrés CMOS en noeuds technologiques submicroniques“. Electronic Thesis or Diss., Paris 6, 2014. http://www.theses.fr/2014PA066253.
Der volle Inhalt der QuelleElectromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the reduction of interconnect dimensions in particular. It is identified as one of the critical reliability phenomenon for integrated circuits designed in submicron technologies. The methods of checking this phenomenon at design level are mostly based on current density rules and temperature. These rules are becoming difficult to implement due to increasing current density in interconnection network. This thesis is based on researching for ways to improve detection of electromigration risks at design level. The goal is to establish a relation between electrical rules and interconnect degradation mechanism. Results obtained from ageing tests permit us to relax current limit without altered circuit lifetimes. Finally, this project has been instrumental to define design rules based on optimization of clock tree cells placement in integrated circuit power grid. The application of solution proposed during this work permit to design robust circuits toward EMG
Roux, Sylvie. „Isolation diélectrique des circuits intégrés de puissance par recristallisation en phase liquide“. Toulouse, INSA, 2001. http://www.theses.fr/2001ISAT0039.
Der volle Inhalt der QuelleThis work takes part of the integration of power devices. Indeed, the main concern within the power electronics is the co-existence in the same substrate of devices using high currents and/or high voltages and of small signal devices. This study meets the need of dimensions shrinking, number of chips reduction, connectivity shrinking and cost reduction. To perform this integration we have chosen to study a silicon on insulator (SOI) substrate, which, due to this buried oxyde layer, allows to obtain a silicon area insulated from the bulk silicon. The method chosen to realize the SOI substrate has the advantage to perform a localized SOI layer. This means that the wafer surface is covered by alternately SOI layer and bulk silicon. To realize this localized SOI substrate, we are using a technique called LEGO for Lateral Epitaxial Growth over Oxide, which consists in the recrystallization in liquid phase of a polycrystalline silicon layer over oxyde beginning from monocystalline seed area. After the state of the art about the different SOI techniques, we present the description of the process for realizing SOI layers. Then, the technological part of the process is explained, whose development took place in the LAAS/CNRS clean room, in addition we present the realization of devices in SOI substrate. Some results of physical and electrical characterizations of the SOI substrate realized by LEGO are exposed and analysed
Gonçalves, Dos Santos Junior Gutemberg. „Conception robuste de circuits numériques à technologie nanométrique“. Electronic Thesis or Diss., Paris, ENST, 2012. http://www.theses.fr/2012ENST0039.
Der volle Inhalt der QuelleThe design of circuits to operate at critical environments, such as those used in control-command systems at nuclear power plants, is becoming a great challenge with the technology scaling. These circuits have to pass through a number of tests and analysis procedures in order to be qualified to operate. In case of nuclear power plants, safety is considered as a very high priority constraint, and circuits designed to operate under such critical environment must be in accordance with several technical standards such as the IEC 62566, the IEC 60987, and the IEC 61513. In such standards, reliability is treated as a main consideration, and methods to analyze and improve the circuit reliability are highly required. The present dissertation introduces some methods to analyze and to improve the reliability of circuits in order to facilitate their qualification according to the aforementioned technical standards. Concerning reliability analysis, we first present a fault-injection based tool used to assess the reliability of digital circuits. Next, we introduce a method to evaluate the reliability of circuits taking into account the ability of a given application to tolerate errors. Concerning reliability improvement techniques, first two different strategies to selectively harden a circuit are proposed. Finally, a method to automatically partition a TMR design based on a given reliability requirement is introduced
Hazebrouck, Sabine. „Planarisation de structures multicouches en technologie bipolaire de circuits intégrés à haute densité d'intégration“. Lille 1, 1991. http://www.theses.fr/1991LIL10056.
Der volle Inhalt der QuelleDzahini, Kwami. „Contribution au développement d'un capteur intégré de type ISFET à partir d'une filière ASIC en technologie CMOS“. Ecully, Ecole centrale de Lyon, 1991. http://www.theses.fr/1991ECDLA009.
Der volle Inhalt der QuelleChhun, Sonarith. „Etude des propriétés et de l'intégration de barrières auto-positionnées sur cuivre formées par des procédés de siliciuration et de dépôts auto-catalytiques dans les interconnexions des circuits intégrés microélectroniques des générations 45 nm“. Lyon, INSA, 2006. http://theses.insa-lyon.fr/publication/2006ISAL0083/these.pdf.
Der volle Inhalt der QuelleThe contribution of standard dielectric barriers to signal propagation and reliability performance degradation speeds up as interconnects dimensions scale down. Self-aligned barriers, in replacement of standard dielectric barriers avoid the contribution of dielectric barriers to the lateral coupling capacitance and enhance adhesion between copper and its capping material, which interface is known to limit interconnect lifetime. In this study, two self-aligned processes are investigated : CuSiN processes, which consist in incorporating silicon and nitrogen atoms into copper to form a CuSiN layer, and CoWP/B processes, based on electroless growth of CoWP/B alloy localized above copper. We evidenced that contrary to CuSiN material, CoWP/B is not a barrier against copper diffusion and against oxydation. Therefore, only CuSiN is suitable for self-aligned barrier formation. Although CuSiN processes are fully compatible with integration processes and materials used in this study, etch and post-etch cleaning steps are critical for CoWP/B integration. However, we succeed in integrating and preserving CoWP/B integrity without degrading electrical performances. In a 65nm technology node, CuSiN processes improve interconnect lifetime up to a factor of 10 whereas the gain using CoWP/B is higher than 70 X. CuSiN processes integration within the 45nm node would help to reach rapidly its reliability criterion. Interconnects with CoWP/B cap which exhibit better resistance against very high current densities, are suitable for the most advanced technology nodes to fulfil their reliability criteria
Gonçalves, Dos Santos Junior Gutemberg. „Conception robuste de circuits numériques à technologie nanométrique“. Thesis, Paris, ENST, 2012. http://www.theses.fr/2012ENST0039/document.
Der volle Inhalt der QuelleThe design of circuits to operate at critical environments, such as those used in control-command systems at nuclear power plants, is becoming a great challenge with the technology scaling. These circuits have to pass through a number of tests and analysis procedures in order to be qualified to operate. In case of nuclear power plants, safety is considered as a very high priority constraint, and circuits designed to operate under such critical environment must be in accordance with several technical standards such as the IEC 62566, the IEC 60987, and the IEC 61513. In such standards, reliability is treated as a main consideration, and methods to analyze and improve the circuit reliability are highly required. The present dissertation introduces some methods to analyze and to improve the reliability of circuits in order to facilitate their qualification according to the aforementioned technical standards. Concerning reliability analysis, we first present a fault-injection based tool used to assess the reliability of digital circuits. Next, we introduce a method to evaluate the reliability of circuits taking into account the ability of a given application to tolerate errors. Concerning reliability improvement techniques, first two different strategies to selectively harden a circuit are proposed. Finally, a method to automatically partition a TMR design based on a given reliability requirement is introduced
Tosik, Grzegorz. „Conception et modélisation de la répartition de l'horloge des systèmes intégrés par voie otpique“. Ecully, Ecole centrale de Lyon, 2004. http://bibli.ec-lyon.fr/exl-doc/gtosik.pdf.
Der volle Inhalt der QuelleThe purpose of this thesis is to provide an unambiguous comparison in terms of dissipated power between optical and electrical clock distribution networks (CDN). A new optical H-tree clock distribution architecture, in which optical waveguides are used as the signal paths are proposed. For this structure, detailed comparative simulations in terms of power dissipation of both optical and electrical H-tree clock networks for future technology generation parameters have been performed. It is shown that the power consumption in optical H-tree allows the distribution of high local frequency signals across the chip, with significantly lower power dissipation than the electrical system
Val, Alexandre. „Étude de la technologie d'interconnexion verticale "MCM-V" appliquée aux microsystèmes“. Toulouse 3, 1996. http://www.theses.fr/1996TOU30233.
Der volle Inhalt der QuelleLe, coz Julien. „Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée“. Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00764400.
Der volle Inhalt der QuelleLe, Coz Julien. „Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée“. Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENT076/document.
Der volle Inhalt der QuellePartially depleted SOI technologies (PD-SOI), offer advantages in terms of speed and dynamic power consumption compared to bulk technologies. The main drawback of the PD-SOI technology is its static power consumption, which is higher than bulk one. It is due to the floating body of its transistors. This work presents a new static power consumption design technique based on power switches. A new factor of merit is introduced selecting the power switch with the best trade-off in terms of leakage current, speed and area. A new power switch brings, in comparison to a reference solution, a reduction of 20% of the ON mode equivalent resistance for the same OFF mode leakage current PD-SOI Silicon validation test chips include LDPC bloc supplied by the proposed solution. Comparing to the bulk technology, a speed gain of 20% is measured for the same voltage supply and a dynamic power consumption reduction of 30% at same speed is achieved. This solution allows reducing by 2 the static power consumption. Finally, a retention flip-flop associated to the implementation of power switches and optimized in PD-SOI is proposed. This flip-flop is designed to be robust with a low leakage current