Zeitschriftenartikel zum Thema „Integrated circuits Very large scale integration“
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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M und Rahul S.G. „Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits“. ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
Patel, Ambresh, und Ritesh Sadiwala. „Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits“. SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, Nr. 01 (30.01.2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
Iwai, Hiroshi, Kuniyuki Kakushima und Hei Wong. „CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING“. International Journal of High Speed Electronics and Systems 16, Nr. 01 (März 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.
Madhura, S. „A Review on Low Power VLSI Design Models in Various Circuits“. Journal of Electronics and Informatics 4, Nr. 2 (08.07.2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
Im, James S., und Robert S. Sposili. „Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays“. MRS Bulletin 21, Nr. 3 (März 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
Beck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit und Andreas Richter. „Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration“. Micromachines 11, Nr. 5 (02.05.2020): 479. http://dx.doi.org/10.3390/mi11050479.
Li, Jian, Robert Blewer und J. W. Mayer. „Copper-Based Metallization for ULSI Applications“. MRS Bulletin 18, Nr. 6 (Juni 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
Dove, Lewis. „Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS“. Journal of Microelectronics and Electronic Packaging 6, Nr. 1 (01.01.2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
Wong, C. P. „An Overview of Integrated Circuit Device Encapsulants“. Journal of Electronic Packaging 111, Nr. 2 (01.06.1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky und Pavel Nekrasov. „Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices“. Facta universitatis - series: Electronics and Energetics 28, Nr. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, HUADONG GAN, KATSUYA MIURA, KOTARO MIZUNUMA, SHUN KANAI et al. „RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI“. SPIN 02, Nr. 03 (September 2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
Sun, Chongjun, und Chao Ding. „Study on Calibration Method for Testing During Burn In equipment of integrated circuits“. Journal of Physics: Conference Series 2029, Nr. 1 (01.09.2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.
Rajaei, Ramin. „A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics“. Journal of Circuits, Systems and Computers 27, Nr. 13 (03.08.2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
Murarka, S. P., J. Steigerwald und R. J. Gutmann. „Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing“. MRS Bulletin 18, Nr. 6 (Juni 1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.
Chen, Xiangyu, Takeaki Yajima, Isao H. Inoue und Tetsuya Iizuka. „An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks“. Japanese Journal of Applied Physics 61, SC (18.02.2022): SC1051. http://dx.doi.org/10.35848/1347-4065/ac43e4.
Chowdary, M. Kalpana, Rajasekhar Turaka, Bayan Alabduallah, Mudassir Khan, J. Chinna Babu und Ajmeera Kiran. „Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques“. Processes 11, Nr. 8 (08.08.2023): 2389. http://dx.doi.org/10.3390/pr11082389.
Zhang, Ai Rong. „The Integration on Electrical Control Systems Based on Optimized Method“. Advanced Materials Research 490-495 (März 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
Luo, Guozheng, Xiang Chen und Shanshan Nong. „Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning“. Journal of Physics: Conference Series 2245, Nr. 1 (01.04.2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.
Jayakumar, Ganesh, Per-Erik Hellström und Mikael Östling. „Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application“. Micromachines 9, Nr. 11 (25.10.2018): 544. http://dx.doi.org/10.3390/mi9110544.
Li, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng und Kai Huang. „Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology“. Applied Sciences 13, Nr. 6 (08.03.2023): 3471. http://dx.doi.org/10.3390/app13063471.
Nagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar und Swathi K. „Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module“. International Journal of Electrical and Electronics Research 10, Nr. 4 (30.12.2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.
Zhu, Ziran, Zhipeng Huang, Jianli Chen und Longkun Guo. „Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles“. Complexity 2021 (14.04.2021): 1–12. http://dx.doi.org/10.1155/2021/8843271.
MOHANA KANNAN, LOGANATHAN, und DHANASKODI DEEPA. „LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION“. DYNA 96, Nr. 5 (01.09.2021): 505–11. http://dx.doi.org/10.6036/10214.
N., Alivelu Manga. „Design of High-Speed Low Power Computational Blocks for DSP Processors“. Revista Gestão Inovação e Tecnologias 11, Nr. 2 (05.06.2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
Cheng, Yi Lung, Yi Shiung Lu und Tai Jung Chiu. „Comparative Study of Low Dielectric Constant Material Deposited Using Different Precursors“. Advanced Materials Research 233-235 (Mai 2011): 2480–85. http://dx.doi.org/10.4028/www.scientific.net/amr.233-235.2480.
Ahmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi und Medhat Awadalla. „ASIC vs FPGA based Implementations of Built-In Self-Test“. International Journal of Advanced Natural Sciences and Engineering Researches 7, Nr. 6 (13.07.2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
Rasheed, Israa Mohammed, und Hassan Jasim Motlak. „Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms“. Bulletin of Electrical Engineering and Informatics 12, Nr. 1 (01.02.2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.
NIRANJAN, VANDANA, ASHWANI KUMAR und SHAIL BALA JAIN. „COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS“. Journal of Circuits, Systems and Computers 23, Nr. 08 (18.06.2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
Sun, Ben. „Interpretable machine learning in VLSI physical design“. Applied and Computational Engineering 4, Nr. 1 (14.06.2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.
Eppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil und R. Rajesh. „VLSI implementation of Kogge-Stone Adder for low-power applications“. i-manager's Journal on Digital Signal Processing 11, Nr. 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.
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NAKADA, KAZUKI, TETSUYA ASAI und HATSUO HAYASHI. „ANALOG VLSI IMPLEMENTATION OF RESONATE-AND-FIRE NEURON“. International Journal of Neural Systems 16, Nr. 06 (Dezember 2006): 445–56. http://dx.doi.org/10.1142/s0129065706000846.
Shanavas, I. Hameem, und R. K. Gnanamurthy. „Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm“. Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.
Sanadhya, Minakshi, Devendra Kumar Sharma und Alfilh Raed Hameed Chyad. „Adiabatic technique based low power synchronous counter design“. International Journal of Electrical and Computer Engineering (IJECE) 13, Nr. 4 (01.08.2023): 3770. http://dx.doi.org/10.11591/ijece.v13i4.pp3770-3777.
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Balodi, Deepak, und Rahul Misra. „Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process“. SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, Nr. 01 (25.07.2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.
Yeh, Chung-Huang, und Jwu-E. Chen. „Unbalanced-Tests to the Improvement of Yield and Quality“. Electronics 10, Nr. 23 (04.12.2021): 3032. http://dx.doi.org/10.3390/electronics10233032.
Laudis, Lalin L., und N. Ramadass. „A Lion’s Pride Inspired Algorithm for VLSI Floorplanning“. Journal of Circuits, Systems and Computers 29, Nr. 01 (15.03.2019): 2050003. http://dx.doi.org/10.1142/s0218126620500036.
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Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi und V. Geetha Sri. „Verilog HDL using LTE Implementation MAP Algorithm“. International Journal of Innovative Research in Computer Science and Technology 10, Nr. 2 (30.03.2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.
Qiao, Zhitong, Yan Han, Xiaoxia Han, Han Xu, Will X. Y. Li, Dong Song, Theodore W. Berger und Ray C. C. Cheung. „ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis“. Neural Computation 30, Nr. 9 (September 2018): 2472–99. http://dx.doi.org/10.1162/neco_a_01107.
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Sidorenko, V. P., V. D. Zhora, O. I. Radkevich, V. P. Grunyanska, Yu V. Prokofiev, Yu V. Tayakin und T. M. Virozub. „Assembly technology and design features of microelectronic coordinate-sensitive detectors“. Технология и конструирование в электронной аппаратуре, Nr. 1 (2018): 21–27. http://dx.doi.org/10.15222/tkea2018.1.21.
Satria, Brama Yoga, Munawar Agus Riyadi und Muhammad Arfan. „PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC“. TRANSIENT 6, Nr. 3 (09.11.2017): 476. http://dx.doi.org/10.14710/transient.6.3.476-482.
Dong, Chen, Jinghui Chen, Wenzhong Guo und Jian Zou. „A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things“. International Journal of Distributed Sensor Networks 15, Nr. 12 (Dezember 2019): 155014771988809. http://dx.doi.org/10.1177/1550147719888098.
Manjunath, T. C., Deekshitha P., Pavithra G., Sindhu Sree M., Suhasini V.K. und K. N. Vijaykumar. „A Survey of the Different Intelligent Algorithms for the VLSI-Based Design Flows for Various Embedded Applications in Electronics Engineering“. Journal of Embedded Systems and Processing 7, Nr. 3 (03.11.2022): 14–17. http://dx.doi.org/10.46610/joesp.2022.v07i03.003.
Mai, Christian, Steffen Marschmeyer, Anna Peczek, Aleksandra Kroh, Josmy Jose, Sebastian Reiter, Inga Fischer, Christian Wenger und Andreas Mai. „Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology“. ECS Meeting Abstracts MA2022-02, Nr. 32 (09.10.2022): 1174. http://dx.doi.org/10.1149/ma2022-02321174mtgabs.
Deekshitha P, Pavithra G, Sindhu Sree M und T.C.Manjunath. „AI/ML/DL Algorithms and Applications in VLSI Design Technology Process Flow – A Brief Review“. international journal of engineering technology and management sciences 6, Nr. 6 (28.11.2022): 329–32. http://dx.doi.org/10.46647/ijetms.2022.v06i06.057.
Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth und Carrie Schmidt. „Photosensitive Glass-Ceramics for Heterogeneous Integration“. Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (01.01.2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.
Sharma, Himanshu, und Karmjit Singh Sandha. „Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects“. Journal of Circuits, Systems and Computers 29, Nr. 12 (05.02.2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.