Dissertationen zum Thema „Integrated circuits Very large scale integration“
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Hong, Won-kook. „Single layer routing : mapping topological to geometric solutions“. Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66030.
Matsumori, Barry Alan. „QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS“. Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.
Jafar, Mutaz 1960. „THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING“. Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.
Voranantakul, Suwan 1962. „CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES“. Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.
Dagenais, Michel R. „Timing analysis for MOSFETS, an integrated approach“. Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75459.
The classical simulation approach cannot be used to insure the timing and electrical correctness of the large circuits that are now being designed. The huge number of possible states in large circuits renders this method impractical. Worst-case analysis tools alleviate the problem by restricting the analysis to a limited set of states which correspond to the worst-case operating conditions. However, existing worst-case analysis tools for MOS circuits present several problems. Their accuracy is inherently limited since they use a switch-level model. Also, these procedures have a high computational complexity because they resort to path enumeration to find the latest path in each transistor group. Finally, they lack the ability to analyze circuits with arbitrarily complex clocking schemes.
In this text, a new procedure for circuit-level timing analysis is presented. Because it works at electronic circuit level, the procedure can detect electrical errors, and attains an accuracy that is impossible to attain by other means. Efficient algorithms, based on graph theory, have been developed to partition the circuits in a novel way, and to recognize series and parallel combinations. This enables the efficient computation of worst-case, earliest and latest, waveforms in the circuit, using specially designed algorithms. The new procedure extracts automatically the timing requirements from these waveforms and can compute the clocking parameters, including the maximum clock frequency, for arbitrarily complex clocking schemes.
A computer program was written to demonstrate the effectiveness of the new procedure and algorithms developed. It has been used to determine the clocking parameters of circuits using different clocking schemes. The accuracy obtained on these parameters is around 5 to 10% when compared with circuit-level simulations. The analysis time grows linearly with the circuit size and is approximately 0.5s per transistor, on a microVAX II computer. This makes the program suitable for VLSI circuits.
Liu, Yansong. „Passivity checking and enforcement in VLSI model reduction exercise“. Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.
Hong, Seong-Kwan. „Performance driven analog layout compiler“. Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.
Davis, Jeffrey Alan. „A hierarchy of interconnect limits and opportunities for gigascale integration (GSI)“. Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15803.
Anbalagan, Pranav. „Limitations and opportunities for wire length prediction in gigascale integration“. Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.
Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.
Ivanov, André. „Dynamic testibility measures and their use in ATPG“. Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.
Zhao, Wenhui, und 趙文慧. „Efficient circuit simulation via adaptive moment matching and matrix exponential techniques“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/197488.
published_or_final_version
Electrical and Electronic Engineering
Master
Master of Philosophy
Hum, Herbert Hing-Jing. „A linear unification processor /“. Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63790.
Chu, Chung-kwan, und 朱頌君. „Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B38719551.
Venkatesan, Raguraman. „Multilevel interconnect architectures for gigascale integration (GSI)“. Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.
Narayanan, Prakash. „Analytical modeling and simulation of bicmos for VLSI circuits“. Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.
Master of Science
張永泰 und Wing-tai Cheung. „Geometric programming and signal flow graph assisted design of interconnect and analog circuits“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
Wilson, Denise M. „Analog VLSI architecture for chemical sensing microsystems“. Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.
Peckel, Marcos David. „A MOS delay model for switch-level simulation /“. Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65990.
Panda, Uma R. „An efficient single-latch scan-design scheme/“. Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.
KRISHT, MUHAMMED HUSSEIN, und MUHAMMED HUSSEIN KRISHT. „LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS“. Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/187983.
Karunaratne, Maddumage Don Gamini. „An intelligent function level backward state justification search for ATPG“. Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184921.
Howells, Michael C. „A cluster-proof approach to yield enhancement of large area binary tree architectures /“. Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66194.
Geller, Ronnie Dee. „A VLSI architecture for a neurocomputer using higher-order predicates“. Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,137.
Al-Mahmood, Saiyid Jami Islah Ahmad. „A distributed design rule checker for VLSI layouts“. Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.
Tyagi, Dhawal. „TENOR : an ATPG for transition faults in combinational circuits /“. Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06302009-040525/.
Kelley, Brian T. „VLSI computing architectures for high speed seismc migration“. Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13919.
Bragg, Julian Alexander. „A biomorphic analog VLSI implementation of a mammalian motor unit“. Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20693.
Tan, Chong Guan. „Another approach to PLA folding“. Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.
高雲龍 und Wan-lung Ko. „A new optimization model for VLSI placement“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.
Rasafar, Hamid 1954. „THE HIGH FREQUENCY AND TEMPERATURE DEPENDENCE OF DIELECTRIC PROPERTIES OF PRINTED CIRCUIT BOARD MATERIALS“. Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276509.
Chen, Ing-yi 1962. „Efficient reconfiguration by degradation in defect-tolerant VLSI arrays“. Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.
Holland, Kenneth Chris. „Probability of latching single event upset errors in VLSI circuits“. Thesis, Virginia Tech, 1991. http://hdl.handle.net/10919/41980.
Most of the research to date has concentrated on the effect of transient faults on flip-flops rather than combinational logic. This is due to several reasons. First, transient faults, also known as Single Event Upsets (SEU), were first observed in memory circuits located on board satellites. Second, an SEU can leave a lasting effect on a circuit if it occurs in a flip-flop, and third, SEUs can cause the output of a flip-flop to change state more easily if it occurs directly in the flip-flop rather than in the combinational logic.
In combinational logic, the node struck by the radiation is completely disjoint from the flip-flops output node. This in effect causes the SEU to satisfy more criteria in order to change the flip-flops output state. The criteria that the SEU must satisfy tend to be complex, and this complexity has caused many researchers to believe that SEUs that occur in combinational logic cause negligible errors in the state of flip-flops.
Thus, in this thesis, the criteria for latching a SEU are
discussed, and original methods are presented that can be used
to determine the probability of an SEU occurring at any node
in a circuit will cause a change in the output state of a
flip-flop. The methods are then incorporated into a program,
named SUPER II, that is able to evaluate the circuit to
determine the nodes with the highest probability of having a
SEU error latched. The results from the program show that
SEUs that occur in combinational logic can have a significant
probability of becoming latched.
Master of Science
Lee, Hoi-Ming Bonny 1961. „The evaluation of the PODEM algorithm as a mechanism to generate goal states for a sequential circuit test search“. Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276730.
Tang, Maolin. „Intelligent approaches to VLSI routing“. Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.
Liu, Yansong, und 劉岩松. „Passivity checking and enforcement in VLSI model reduction exercise“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.
Khordoc, Karim. „A MOS switch-level simulator with delay calculation /“. Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65461.
Whipple, Thomas Driggs 1961. „Design and implementation of an integrated VLSI packaging support software environment“. Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.
Bishop, Gregory Raymond H. „"On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems" /“. Title page, contents and abstract only, 1993. http://web4.library.adelaide.edu.au/theses/09PH/09phb6222.pdf.
Kosaraju, Chakravarthy S. „A set of behavioral modeling primitives“. Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41989.
Modeling is an essential step in the design of digital circuits [71. The coding of behavioral models for complex devices is a labor intensive task. Even with the use of a to01like the "Modeler's Assistant" [4}, the development of behavioral models is time consuming and labor intensive. The use of re-usable code along with a tool like the Modeler's Assistant can speed up model development. This thesis defines a set of higher level primitives which can be used for this purpose. These primitives are built as a macro library into the tool. The Modeler's Assistant together with the modeling primitives provides us with a tool that can simplify the process of model development.
Master of Science
Cho, Chang H. „A formal model for behavioral test generation“. Diss., This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06062008-170406/.
Deng, Chaodan. „Process development for si-based nanostructures using pulsed UV laser induced epitaxy“. Full text open access at:, 1995. http://content.ohsu.edu/u?/etd,206.
Moini, Alireza. „Synthesis of biological vision models using analog VLSI /“. Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm712.pdf.
Tan, Wei-Siong. „A VLSI parallel processor structure for scientific computing“. Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/13455.
Patel, Girish N. „A neuromorphic architecture for modeling intersegmental coordination“. Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13528.
Gordon, Christal. „An adaptive floating-gate network using action-potential signaling“. Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15683.
Măndoiu, Ion I. „Approximation algorithms for VLSI routing“. Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.
梁迅中 und Shun-chung Leung. „Silicon compiler for bit-serial signal processing architecture with automatic time alignment“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1987. http://hub.hku.hk/bib/B31207741.
袁志勤 und Chi-kan Yuen. „A double-track greedy algorithm for VLSI channel routing“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.
Ma, Min. „Model order reduction for efficient modeling and simulation of interconnect networks“. Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103269.
In this thesis, a number of new reduction techniques were developed in order to address the key shortcomings of current model order reduction methods. Specifically a new approach for handling macromodels with a very large number of ports was developed, a multi-level reduction and sprasification method was proposed for regular as well as parametric macromodels, and finally a new time domain reduction method was presented for the macromodeling of nonlinear parametric systems. Using these approaches, CPU speedups of 1 to 2 orders of magnitude were obtained.
Shope, David Allen 1958. „Thermal characterization of VLSI packaging“. Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276686.