Auswahl der wissenschaftlichen Literatur zum Thema „Integrated circuits Very large scale integration“
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Zeitschriftenartikel zum Thema "Integrated circuits Very large scale integration":
M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M und Rahul S.G. „Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits“. ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
Patel, Ambresh, und Ritesh Sadiwala. „Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits“. SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, Nr. 01 (30.01.2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
Iwai, Hiroshi, Kuniyuki Kakushima und Hei Wong. „CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING“. International Journal of High Speed Electronics and Systems 16, Nr. 01 (März 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.
Madhura, S. „A Review on Low Power VLSI Design Models in Various Circuits“. Journal of Electronics and Informatics 4, Nr. 2 (08.07.2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
Im, James S., und Robert S. Sposili. „Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays“. MRS Bulletin 21, Nr. 3 (März 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
Beck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit und Andreas Richter. „Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration“. Micromachines 11, Nr. 5 (02.05.2020): 479. http://dx.doi.org/10.3390/mi11050479.
Li, Jian, Robert Blewer und J. W. Mayer. „Copper-Based Metallization for ULSI Applications“. MRS Bulletin 18, Nr. 6 (Juni 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
Dove, Lewis. „Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS“. Journal of Microelectronics and Electronic Packaging 6, Nr. 1 (01.01.2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
Wong, C. P. „An Overview of Integrated Circuit Device Encapsulants“. Journal of Electronic Packaging 111, Nr. 2 (01.06.1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky und Pavel Nekrasov. „Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices“. Facta universitatis - series: Electronics and Energetics 28, Nr. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
Dissertationen zum Thema "Integrated circuits Very large scale integration":
Hong, Won-kook. „Single layer routing : mapping topological to geometric solutions“. Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66030.
Matsumori, Barry Alan. „QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS“. Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.
Jafar, Mutaz 1960. „THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING“. Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.
Voranantakul, Suwan 1962. „CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES“. Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.
Dagenais, Michel R. „Timing analysis for MOSFETS, an integrated approach“. Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75459.
The classical simulation approach cannot be used to insure the timing and electrical correctness of the large circuits that are now being designed. The huge number of possible states in large circuits renders this method impractical. Worst-case analysis tools alleviate the problem by restricting the analysis to a limited set of states which correspond to the worst-case operating conditions. However, existing worst-case analysis tools for MOS circuits present several problems. Their accuracy is inherently limited since they use a switch-level model. Also, these procedures have a high computational complexity because they resort to path enumeration to find the latest path in each transistor group. Finally, they lack the ability to analyze circuits with arbitrarily complex clocking schemes.
In this text, a new procedure for circuit-level timing analysis is presented. Because it works at electronic circuit level, the procedure can detect electrical errors, and attains an accuracy that is impossible to attain by other means. Efficient algorithms, based on graph theory, have been developed to partition the circuits in a novel way, and to recognize series and parallel combinations. This enables the efficient computation of worst-case, earliest and latest, waveforms in the circuit, using specially designed algorithms. The new procedure extracts automatically the timing requirements from these waveforms and can compute the clocking parameters, including the maximum clock frequency, for arbitrarily complex clocking schemes.
A computer program was written to demonstrate the effectiveness of the new procedure and algorithms developed. It has been used to determine the clocking parameters of circuits using different clocking schemes. The accuracy obtained on these parameters is around 5 to 10% when compared with circuit-level simulations. The analysis time grows linearly with the circuit size and is approximately 0.5s per transistor, on a microVAX II computer. This makes the program suitable for VLSI circuits.
Liu, Yansong. „Passivity checking and enforcement in VLSI model reduction exercise“. Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.
Hong, Seong-Kwan. „Performance driven analog layout compiler“. Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.
Davis, Jeffrey Alan. „A hierarchy of interconnect limits and opportunities for gigascale integration (GSI)“. Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15803.
Anbalagan, Pranav. „Limitations and opportunities for wire length prediction in gigascale integration“. Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.
Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.
Ivanov, André. „Dynamic testibility measures and their use in ATPG“. Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.
Bücher zum Thema "Integrated circuits Very large scale integration":
Chapel Hill Conference on Very Large Scale Integration (1985). 1985 Chapel Hill Conference on Very Large Scale Integration. [Rockville, Md.]: Computer Science Press, 1985.
Song, Hongjiang. VLSI analog signal processing circuits: Algorithm, architecture, modeling, and circuit implementation. [United States]: Xlibris Corp, 2009.
Uyemura, John P. Introduction to VLSI circuits and systems. New York: J. Wiley, 2002.
Wanhammar, Lars. DSP integrated circuits. San Diego, Calif: Academic, 1998.
1936-, Chen Wai-Kai, Hrsg. The VLSI handbook. 2. Aufl. Boca Raton, FL: CRC/Taylor & Francis, 2007.
name, No. VLSI circuits and systems: 19-21 May 2003, Maspalomas, Gran Canaria, Spain. Bellingham, WA: SPIE, 2003.
Wolf, Wayne. Modern VLSI design: A systems approach. Englewood Cliffs, N.J: Prentice-Hall International, 1994.
Wolf, Wayne. Modern VLSI design: IP-based design. 4. Aufl. Upper Saddle River, N.J: Prentice Hall, 2008.
Parhi, Keshab K. VLSI digital signal processing systems: Design and implementation. New York: Wiley, 1999.
1936-, Chen Wai-Kai, Hrsg. The VLSI handbook. Boca Raton, Fla: CRC Press, 1999.
Buchteile zum Thema "Integrated circuits Very large scale integration":
Maly, Wojciech. „Feasibility of Large Area Integrated Circuits“. In Wafer Scale Integration, 31–56. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4613-1621-3_2.
Ghate, P. B. „Metallization for Very Large-Scale Integrated Circuits“. In Handbook of Advanced Semiconductor Technology and Computer Systems, 181–228. Dordrecht: Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-011-7056-7_6.
Rachmuth, Guy, und Chi-Sang Poon. „In-Silico Model of NMDA and Non-NMDA Receptor Activities Using Analog Very-Large-Scale Integrated Circuits“. In Advances in Experimental Medicine and Biology, 171–75. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/0-387-27023-x_26.
Gebregiorgis, Anteneh, Rajendra Bishnoi und Mehdi B. Tahoori. „Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches“. In Dependable Embedded Systems, 303–34. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_13.
Capmany, José, und Daniel Pérez. „Practical Implementation of Programmable Photonic Circuits“. In Programmable Integrated Photonics, 178–226. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0006.
Lee, Chang Yeol. „Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies“. In Very-Large-Scale Integration. InTech, 2018. http://dx.doi.org/10.5772/intechopen.68825.
Zaidi, Muhaned, Ian Grout und Abu Khari A’ain. „Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices“. In Very-Large-Scale Integration. InTech, 2018. http://dx.doi.org/10.5772/intechopen.68815.
Kiran B., Raghu N. und Manjunatha K. N. „VLSI Implementation of a High-Speed Pipeline A/D Converter“. In Role of 6G Wireless Networks in AI and Blockchain-Based Applications, 112–30. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-5376-6.ch005.
Lee, Joseph Ya-min, und Benjamin Chihming Lai. „The electrical properties of high-dielectric-constant and ferroelectric thin films for very large scale integration circuits“. In Handbook of Thin Films, 1–98. Elsevier, 2002. http://dx.doi.org/10.1016/b978-012512908-4/50037-0.
Nagarajan, Ashok Kumar, Kavitha Thandapani, Neelima K., Bharathi M., Dhamodharan Srinivasan und SathishKumar Selvaperumal. „VLSI Implementation of Neural Systems“. In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 94–116. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-6596-7.ch004.
Konferenzberichte zum Thema "Integrated circuits Very large scale integration":
Gunti, Nagendra Babu, Aman Khatri und Karthikeyan Lingasubramanian. „Realizing a security aware triple modular redundancy scheme for robust integrated circuits“. In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004183.
Chusseau, Laurent, Rachid Omarouayache, Jeremy Raoult, Sylvie Jarrix, Philippe Maurine, Karim Tobich, Alexandre Bover et al. „Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)“. In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004189.
Michailidis, Anastasios, Thomas Noulis und Kostas Siozios. „Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking“. In 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-soc54400.2022.9939575.
Xiang, Dong, Gang Liu, Krishnendu Chakrabarty und Hideo Fujiwara. „Thermal-aware test scheduling for NOC-based 3D integrated circuits“. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2013. http://dx.doi.org/10.1109/vlsi-soc.2013.6673257.
Brik, Adil, Lioua Labrak, Laurent Carrel, Ian O'Connor und Ramy Iskander. „Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts“. In 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2019. http://dx.doi.org/10.1109/vlsi-soc.2019.8920305.
Livramento, Vinícius Dos Santos, und José Luís Güntzel. „Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits“. In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.
Ozaktas, Haldun M., Adolf W. Lohmann und Hakan Urey. „Scaling of diffractive and refractive lenses for optical computing and interconnections“. In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.mkk.3.
Krishnamoorthy, A. V., J. E. Ford, K. W. Goossen, J. A. Walker, A. L. Lentine, L. A. D’Asaro, S. P. Hui et al. „Implementation of a Photonic Page Buffer Based on GaAs MQW Modulators Bonded Directly over Active Silicon VLSI Circuits“. In Optical Computing. Washington, D.C.: Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.pd2.
Clymer, Bradley D. „Surface-relief grating structures for photodetectors for optical interconnects in VLSI“. In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.fx3.
Yano, Kazuo, Tomoaki Akitomi, Koji Ara, Junichiro Watanabe, Satomi Tsuji, Nobuo Sato, Miki Hayakawa und Norihiko Moriwaki. „Profiting from IoT: The key is very-large-scale happiness integration“. In 2015 Symposium on VLSI Circuits. IEEE, 2015. http://dx.doi.org/10.1109/vlsic.2015.7231287.
Berichte der Organisationen zum Thema "Integrated circuits Very large scale integration":
Clark, Kay E. VLSI/VHSIC (Very Large Scale Integrated/Very High Speed Integrated Circuits) Package Test Development. Fort Belvoir, VA: Defense Technical Information Center, Dezember 1986. http://dx.doi.org/10.21236/ada182360.
Cohen, Seymour. Quality Procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) Type Devices. Fort Belvoir, VA: Defense Technical Information Center, November 1985. http://dx.doi.org/10.21236/ada164885.
Collier, Wiehrs L. VLSI (Very Large Scale Integrated Circuits) Implementation of a Quantized Sinusoid Filter Algorithm and Its Use to Compute the Discrete Fourier Transform. Fort Belvoir, VA: Defense Technical Information Center, März 1986. http://dx.doi.org/10.21236/ada168605.
Hertel, Thomas, David Hummels, Maros Ivanic und Roman Keeney. How Confident Can We Be in CGE-Based Assessments of Free Trade Agreements? GTAP Working Paper, Juni 2003. http://dx.doi.org/10.21642/gtap.wp26.