Thematische Bibliographien / Gate oxide reliability

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Auswahl der wissenschaftlichen Literatur zum Thema „Gate oxide reliability“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

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Zeitschriftenartikel zum Thema "Gate oxide reliability"

Wan, Caiping, Yuanhao Zhang, Wenhao Lu, Niannian Ge, Tianchun Ye und Hengyu Xu. „Improving the reliability of MOS capacitor on 4H-SiC (0001) with phosphorus diffused polysilicon gate“. Semiconductor Science and Technology 37, Nr. 5 (07.04.2022): 055008. http://dx.doi.org/10.1088/1361-6641/ac606d.

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Abstract The interface states and reliability of 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with thermal gate oxides have been researched widely. Several reports have researched the gate oxide process itself, but the effects of subsequent processes should not be ignored. In this paper, the reliability of thermal gate oxide films followed by polysilicon gate (poly-gate) process, which are widely used in MOSFET manufacture, and Al gates were compared. The poly-gate samples markedly affected the performance measured by time-zero dielectric breakdown and time-dependent dielectric breakdown methods because the phosphorus content diffused during poly-gate formatting; this was especially advantageous in reducing leakage current and improving the charge-to-breakdown (Q BD). After electronic characteristics measurements, scanning electron microscopy cross-sections were also used to analyze the breakdown mechanism. We observed an intermediate layer between the Al gate and the oxide that may cause the barrier height to be smaller than that of the poly-gate. The Al work function and polysilicon Fermi level determine the gate leakage currents and the resultant gate oxide reliability, whereas the Al2O3 gate sample has a smaller work function offset (0.7 eV) than ideal Al gate and poly-gate samples. The results imply that the reliability of the Al gate samples may be an intrinsic problem.

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Monsieur, F., E. Vincent, D. Roy, S. Bruyère, G. Pananakakis und G. Ghibaudo. „Gate oxide Reliability assessment optimization“. Microelectronics Reliability 42, Nr. 9-11 (September 2002): 1505–8. http://dx.doi.org/10.1016/s0026-2714(02)00179-8.

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Fronheiser, Jody, Aveek Chatterjee, Ulrike Grossner, Kevin Matocha, Vinayak Tilak und Liang Chun Yu. „Evaluation of 4H-SiC Carbon Face Gate Oxide Reliability“. Materials Science Forum 679-680 (März 2011): 354–57. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.354.

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The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

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Lee, Seok-Woo. „Novel Dual Gate Oxide Process with Improved Gate Oxide Integrity Reliability“. Electrochemical and Solid-State Letters 3, Nr. 1 (1999): 56. http://dx.doi.org/10.1149/1.1390957.

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Moazzami, R., und C. Hu. „Projecting gate oxide reliability and optimizing reliability screens“. IEEE Transactions on Electron Devices 37, Nr. 7 (Juli 1990): 1643–50. http://dx.doi.org/10.1109/16.55751.

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Weir, B. E., M. A. Alam, P. J. Silverman, F. Baumann, D. Monroe, J. D. Bude, G. L. Timp et al. „Ultra-thin gate oxide reliability projections“. Solid-State Electronics 46, Nr. 3 (März 2002): 321–28. http://dx.doi.org/10.1016/s0038-1101(01)00103-4.

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Deivasigamani, Ravi, Gene Sheu, Aanand, Shao Wei Lu, Syed Sarwar Imam, Chiu-Chung Lai und Shao-Ming Yang. „Study of HCI Reliability for PLDMOS“. MATEC Web of Conferences 201 (2018): 02001. http://dx.doi.org/10.1051/matecconf/201820102001.

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In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.

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Senzaki, Junji, Atsushi Shimozato, Kozutoshi Kajima, Keiko Aryoshi, Takahito Kojima, Shinsuke Harada, Yasunori Tanaka, Hiroaki Himi und Hajime Okumura. „Electrical Properties of MOS Structures on 4H-SiC (11-20) Face“. Materials Science Forum 740-742 (Januar 2013): 621–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.621.

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Threshold voltage (VTH) instability, channel mobility and oxide reliability have been investigated for meta-oxide-semiconductor (MOS) structures on 4H-SiC (11-20) face using various gate oxidation procedures. Channel mobility of n-channel MOSFET with a gate oxide by pyrogenic oxidation is higher than that by dilute-DRY oxidation followed by a nitrous oxide (N2O) post-oxidation annealing (POA). On the other hand, oxide reliability for the pyrogenic oxides is poor compared with the dilute-DRY/N2O oxides. A Hydrogen POA is effective in an improvement of channel mobility for both oxides, but causes a harmful effect on VTH stability. Temperature dependence of VTH instability indicates that MOS structure grown by dilute-DRY followed by N2O POA is suitable for a practical use of SiC MOS power devices.

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Yamada, Keiichi, Osamu Ishiyama, Kentaro Tamura, Tamotsu Yamashita, Atsushi Shimozato, Tomohisa Kato, Junji Senzaki, Hirohumi Matsuhata und Makoto Kitabatake. „Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment“. Materials Science Forum 778-780 (Februar 2014): 545–48. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.545.

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This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

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Liang, Xiaowen, Jiangwei Cui, Jing Sun, Haonan Feng, Dan Zhang, Xiaojuan Pu, Xuefeng Yu und Qi Guo. „The Influence of 10 MeV Proton Irradiation on Silicon Carbide Power Metal-Oxide-Semiconductor Field-Effect Transistor“. Journal of Nanoelectronics and Optoelectronics 17, Nr. 5 (01.05.2022): 814–19. http://dx.doi.org/10.1166/jno.2022.3255.

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The effects of 10 MeV proton irradiation on the threshold voltage and gate oxide reliability of SiC MOSFET are investigated. The negative shift of the threshold voltage was observed after irradiation, and the magnitude of the shift is exclusively related to the fluence and not the drain voltage. Moreover, proton irradiation leads up to the degeneration of oxide reliability. Experiment and simulation results indicate that the shift of the threshold voltage is caused by the total ionizing dose effect. Due to the superior blocking capabilities of the SiC MOSFET, the electric field of gate oxide is almost unaffected by the voltage applied to the drain, so the drift of threshold voltage is only related to particle fluence. The single event effect is responsible for the degradation of gate oxide reliability. The single event effect induces a transient high electric field in the gate oxide, which generates defects and affects the reliability of the gate oxide.

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Dissertationen zum Thema "Gate oxide reliability"

Owens, Gethin Lloyd. „Design of a reliability methodology : modelling the influence of temperature on gate oxide reliability“. Thesis, Durham University, 2007. http://etheses.dur.ac.uk/2695/.

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An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models. Each model is based on a physics of failure approach and includes on the effects of temperature. At all stages the models are verified experimentally on modern deep sub-micron devices. The research provides the foundations of a tool which gives the user the opportunity to make appropriate trade-offs between performance and reliability, and that can be implemented in the early stages of product development.

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Zeng, Xu, und 曾旭. „Electrical reliability of N-Mos devices with N2O-based oxides as gate dielectrics“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1996. http://hub.hku.hk/bib/B31235475.

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Zeng, Xu. „Electrical reliability of N-Mos devices with N2O-based oxides as gate dielectrics /“. Hong Kong : University of Hong Kong, 1996. http://sunzi.lib.hku.hk/hkuto/record.jsp?B1966980X.

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Jayaraman, Rajsekhar. „Reliability and 1/f noise properties of MOSFETs with nitrided oxide gate dielectrics“. Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/41582.

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Yan, Liang. „Characterisation of gate oxide and high-k dielectric reliability in strained si and sige cmos transistors“. Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506541.

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Kutty, Karan. „CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY“. Master's thesis, University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2703.

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This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE

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MA, JUN. „STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES“. Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3547.

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In the modern semiconductor world, there is a significant scaling of the transistor dimensions--The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device--low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device--from device level to circuit level; Studying real voltage stress case--high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD

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Matsumoto, Takashi. „Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits“. 京都大学 (Kyoto University), 2015. http://hdl.handle.net/2433/199461.

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松本, 高士. „バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響“. Kyoto University, 2015. http://hdl.handle.net/2433/199558.

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Boyer, Ludovic. „Analyse des propriétés de l'oxyde de grille des composants semi-conducteurs de puissance soumis à des contraintes électro-thermiques cycliques : vers la définition de marqueurs de vieillissement“. Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20028/document.

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Les composants semi-conducteurs de puissance sont aujourd'hui au c?ur des systèmes de conversion d'énergie et sont de plus en plus employés dans le domaine des transports, notamment dans des applications critiques induites par l'émergence des véhicules hybrides et d'avions plus électriques. Durant l'exploitation des systèmes de conversion d'énergie, des contraintes significatives sont imposées aux composants semi-conducteurs de puissance, dégradant ainsi leur fonctionnement. Dans une application critique, ces dégradations peuvent activer la défaillance d'un système électrique et ainsi avoir des conséquences graves d'un point de vue économique et de sécurité. Il existe alors une forte demande concernant une compréhension des modes de défaillances et des mécanismes de vieillissement des composants semi-conducteurs de puissance. Il en est de même pour le développement de nouvelles techniques de caractérisations pour le suivi de leur vieillissement. Le suivi de l'évolution de paramètres de l'oxyde de grille de véhicules tests par le biais de la méthode Capacité-Tension ou C(V) - couramment employée en micro-électronique - et de la méthode de l'onde thermique ou MOT - développée au sein du Groupe Énergie et Matériaux de l'IES -, ainsi que leur adaptation à des composants semi-conducteurs de puissance, constituent l'essentiel du travail de cette thèse. Le couplage de la MOT à la C(V) a permis de localiser sommairement les charges injectées dans l'oxyde de grille des véhicules tests lorsqu'ils ont été soumis à des contraintes électriques similaires à celles subies dans les systèmes de conversion d'énergie
Power semi-conductor devices are increasingly used as key parts of embedded power conversion systems in critical applications such as aerospace industry and ground transport. In such critical applications, these devices are submitted to harsh electrical, thermal and mechanical environments stresses which may significantly alter their reliability. An embedded power conversion system failure due to a power semi-conductor device breakdown may induce catastrophic results in terms of human safety, as well as economical dimensions. There is, indeed, a continuous demand on an increasing knowledge concerning the failure modes and the ageing mechanisms of power semi-conductor devices, as well as for development of new characterization techniques for ageing monitoring. The greatest part of the present work is focused on the monitoring of gate oxide properties evolutions of samples structures using the Capacitance-Voltage method (C-V method) -mainly employed in microelectronics- and the Thermal Step Method (TSM) -developed in Energy and Materials Group of IES-, as well as applying them to power semi-conductor devices. Coupling TSM and C-V method has allowed to approximately locate injected charges in the gate oxide of sample devices when submitted to electrical stresses comparable to the ones submitted to power semi-conductor devices

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Bücher zum Thema "Gate oxide reliability"

Reiner, Joachim C. Latent gate oxide damage induced by ultra-fast electrostatic discharge. Konstanz: Hartung-Gorre, 1995.

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Meeting, Materials Research Society, und Symposium C, "CMOS Gate-Stack Scaling-- Materials, Interfaces and Reliability Implications" (2009 : San Francisco, Calif.), Hrsg. CMOS gate-stack scaling-- materials, interfaces and reliability implications: Symposium held April 14-16, 2009, San Francisco, california, U.S.A. Warrendale, Pa: Materials Research Society, 2009.

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C, Gupta D., Brown George A. 1937- und Conference on Gate Dielectric Integrity (1999 : San Jose, Calif.), Hrsg. Gate dielectric integrity: Material, process, and tool qualification. West Conshocken, Pa: ASTM, 2000.

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Bill, Taylor, Alexander A. Demkov, H. Rusty Harris, Jeffery W. Butterbaugh und Willy Rachmady. CMOS Gate-Stack Scaling Vol. 1155: Materials, Interfaces and Reliability Implications. University of Cambridge ESOL Examinations, 2014.

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(Editor), Dinesh C. Gupta, und George Albert Brown (Editor), Hrsg. Gate Dielectric Integrity: Material, Process, and Tool Qualification (Astm Special Technical Publication// Stp) (Astm Special Technical Publication// Stp). ASTM International, 2000.

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Buchteile zum Thema "Gate oxide reliability"

Ghetti, A. „Gate Oxide Reliability: Physical and Computational Models“. In Springer Series in MATERIALS SCIENCE, 201–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-662-09432-7_6.

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Voors, I. J., K. Osinski, F. H. A. Vollebregt und C. A. Seams. „Gate Oxide Reliability in a Sealed Interface Local Oxidation Scheme“. In ESSDERC ’89, 361–65. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_73.

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Tanimoto, Satoshi. „Impact of Dislocations on Gate Oxide in SiC MOS Devices and High Reliability ONO Dielectrics“. In Silicon Carbide and Related Materials 2005, 955–60. Stafa: Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-425-1.955.

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Fujihira, Keiko, Yoichiro Tarui, Ken Ichi Ohtsuka, Masayuki Imaizumi und Tetsuya Takami. „Effects of N₂O Anneal on Channel Mobility of 4H-SiC MOSFET and Gate Oxide Reliability“. In Materials Science Forum, 697–700. Stafa: Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-963-6.697.

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Hirose, M., W. Mizubayashi, K. Morino, M. Fukuda und S. Miyazaki. „Tunneling Transport and Reliability Evaluation in Extremely Thin Gate Oxides“. In Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, 315–24. Dordrecht: Springer Netherlands, 1998. http://dx.doi.org/10.1007/978-94-011-5008-8_22.

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SUÑE, JORDI, DAVID JIMENEZ und ENRIQUE MIRANDA. „BREAKDOWN MODES AND BREAKDOWN STATISTICS OF ULTRATHIN SiO2 GATE OXIDES“. In Oxide Reliability, 173–232. WORLD SCIENTIFIC, 2002. http://dx.doi.org/10.1142/9789812778062_0004.

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Yeo, Yee-Chia, Qiang Lu und Chenming Hu. „MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications“. In Oxide Reliability, 233–70. WORLD SCIENTIFIC, 2002. http://dx.doi.org/10.1142/9789812778062_0005.

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Kong, Moufu. „New Electronic Devices for Power Converters“. In Power Electronics, Radio Frequency and Microwave Engineering [Working Title]. IntechOpen, 2023. http://dx.doi.org/10.5772/intechopen.108467.

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Power electronic devices are crucial components of power converter systems. The evolution of power devices drives the development of power converters, including improvements in performance, reliability, and power capacity. In this chapter, the author expounds the structure, working principle, and static and dynamic characteristics of the conventional PN junction diode. And the silicon carbide (SiC) Schottky barrier diode (SBD), junction barrier Schottky (JBS) diode, trench JBS (T-JBS) diode, and sidewall-enhanced trench JBS (SET-JBS) diode are also discussed and compared. Also, the structures and properties of the gallium oxide (Ga2O3) SBD and heterojunction diode are also summarized. Next, the author gives a detailed analysis and discussion of the silicon power metal-oxide-semiconductor field-effect transistor (MOSFET), superjunction MOSFET, and the SiC MOSFET and JFET, and the Ga2O3 MOSFET. Then, the device structure and operating principle, switching characteristics, and current tailing mechanism of the insulated gate bipolar transistor (IGBT) are also analyzed and summarized in detail. Finally, the energy band structure, working principle, and switching characteristic of the gallium nitride (GaN) high-electron mobility transistor (HEMT), one of the hot devices in the current market, are also described. Finally, the summary and prospect of power electronic devices are also presented in this chapter.

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Chander, Sweta, und Sanjeet Kumar Sinha. „Performance Analysis of Electrical Characteristics of Hetero-junction LTFET at Different Temperatures for IoT Applications“. In Nanoelectronics Devices: Design, Materials, and Applications (Part I), 105–32. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815136623123010007.

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Scaling down the metal-oxide- semiconductor (MOS) technology in the nanometer regime has been performed to achieve high device performance, but reliability and power consumption are the main concern for the semiconductor industry. In the past few years, area-scaled tunneling field-effect transistors (TFETs) have been researched aggressively to enhance the tunneling cross-sectional area of devices. Although the area-scaled Tfet increases the device footprint for the same channel length when compared to the conventional TFET structure. This problem can be resolved by considering a nonplanar device structure. The LTFET structure enhances the on-state current and reduces the device footprint area. In the present study, a detailed analysis of the electrical characteristics of L-shaped TFET (LTFET) through 2-D TCAD simulations is presented. The proposed hetero-junction LTFET with 20 nm gate length exhibits a high ION of 1.08×10-4 A/µm, low IOFF of 1.57×10-14 A/µm, high ION/IOFF of 1010, and steep sub-threshold slope (SS) of 25 mV/dec at room temperature. The analysis has been carried out to encounter the effect of Gaussian traps at the channel–gate oxide interface at a wide range of temperatures from 250 K to 350 K. An extensive study on the influence of temperature variations on various DC analysis, AC analysis, linearity analysis, and electrical noise analysis has been carried out. The study reveals that the electrical parameters like ION, IOFF, and SS, on which all figures of merit (FOMs) of the device depend, show a small variation with increasing temperature. The drain current noise spectral density (SID) changes from 2.12×10-26 A 2 /Hz to 2.42×10-20 A2 /Hz, and voltage noise spectral density (SVG) changes from 1.79×10-11 V2 /Hz to 1.97×10-5 V2 /Hz on increasing temperature from 250 K to 350 K. The change in temperature does not impact the on-current of the device, while a small variation in the off-current occurs. The various FOMs of the device also show small variations in the results with increasing temperature. The only unfavorable factor where the evident change in the results has been observed is the electrical noise characteristics of the device. The reliability analysis clarifies that the proposed LTFET device performs well at a wide range of temperatures and can be well-suited for low-power applications.

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Su, H. P., S. M. Lin und H. C. Cheng. „Effects of BF2+-Implanted Polysilicon Structures on the Reliability of Gate Oxides“. In Ion Implantation Technology–92, 655–58. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89994-1.50140-x.

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Konferenzberichte zum Thema "Gate oxide reliability"

Park, S., J. Kang, B. So und D. Baek. „Gate oxide integrity by initial gate current“. In 2009 IEEE International Integrated Reliability Workshop (IRW). IEEE, 2009. http://dx.doi.org/10.1109/irws.2009.5383020.

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McPherson, J. W., und D. A. Baglee. „Acceleration Factors for Thin Gate Oxide Stressing“. In 23rd International Reliability Physics Symposium. IEEE, 1985. http://dx.doi.org/10.1109/irps.1985.362066.

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Arabi, M., X. Federspiel, F. Cacho, M. Rafik, S. Blonkowski, X. Garros und G. Guibaudo. „Frequency dependant gate oxide TDDB model“. In 2022 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2022. http://dx.doi.org/10.1109/irps48227.2022.9764503.

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Gang Niu, Wei-Ting Kary Chien, Guan Zhang, Jianshu Yu, Xiaodong Zhao und Xiaobo Duan. „Gate oxide reliability improvement for UMOS technology“. In 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2015. http://dx.doi.org/10.1109/ipfa.2015.7224402.

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Hu, Chenming. „Reliability and Scaling of Thin Gate Oxide“. In 1997 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1997. http://dx.doi.org/10.7567/ssdm.1997.a-1-1.

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Yeoh, Teong-San, Nitin R. Kamat, Remesh S. Nair und Shze-Jer Hu. „Gate Oxide Breakdown Model in MOS Transistors“. In 33rd IEEE International Reliability Physics Symposium. IEEE, 1995. http://dx.doi.org/10.1109/irps.1995.363349.

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Ramey, S., und J. Hicks. „SILC and gate oxide breakdown characterization of 22nm tri-gate technology“. In 2014 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2014. http://dx.doi.org/10.1109/irps.2014.6860621.

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Ju, X., und D. S. Ang. „Gate-Oxide Trapping Enabled Synaptic Logic Transistor“. In 2020 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2020. http://dx.doi.org/10.1109/irps45951.2020.9129338.

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Teong-San Yeoh, N. R. Kamat, R. S. Nair und Shze-Jer Hu. „Gate oxide breakdown model in MOS transistors“. In Proceedings of 1995 IEEE International Reliability Physics Symposium. IEEE, 1995. http://dx.doi.org/10.1109/relphy.1995.513668.

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Nishida, Toshikazu, und Scott E. Thompson. „Oxide Field and Temperature Dependences of Gate Oxide Degradation by Substrate Hot Electron Injection“. In 29th International Reliability Physics Symposium. IEEE, 1991. http://dx.doi.org/10.1109/irps.1991.363250.

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