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Thematische Bibliographien / Functional verification of digital systems / Zeitschriftenartikel

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Zeitschriftenartikel zum Thema „Functional verification of digital systems“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 7. Februar 2022

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1

Franco, Ricardo Augusto Pereira, Karina Rocha Gomes Da Silva und Cássio Leonardo Rodrigues. „Genetic Algorithm applied to the Functional Verification in Digital Systems“. Journal of Integrated Circuits and Systems 13, Nr. 1 (24.08.2018): 1–9. http://dx.doi.org/10.29292/jics.v13i1.20.

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A critical stage of a hardware design is the hardware verification phase. The verification phase corresponds to the biggest bottleneck in a hardware design. The VeriSC methodology is a methodology to perform the hardware verification through of functional verification. In this work, we propose a novel improvement in VeriSC methodology data generation using Genetic Algorithms and feedback approach. The proposed algorithm will modify the data generation of this methodology, whose objective is to reduce the verification time and to improve the generated data. A DPCM and two modules of MPEG-DECODER are used as case studies. The results not only show that the proposed approach can achieve functional coverage with good performance, but also show that the execution time is better or similar to the former method used in VeriSC methodology. These results demonstrate the Genetic Algorithm approach explores the search space better than older approach. The data generation performed can also be used in other methodologies without any problem.

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Alekhin, V. A. „Designing Electronic Systems Using SystemC and SystemC–AMS“. Russian Technological Journal 8, Nr. 4 (06.08.2020): 79–95. http://dx.doi.org/10.32362/2500-316x-2020-8-4-79-95.

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Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

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Chen, Fu Long, Zhao Xia Zhu und Xiao Ya Fan. „FPGA-Based In-Circuit Verification of Digital Systems“. Advanced Materials Research 187 (Februar 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.

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Wang, Qian, Xiaoyu Song, Ming Gu und Jiaguang Sun. „Functional Verification of High Performance Adders in COQ“. Journal of Applied Mathematics 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/197252.

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Addition arithmetic design plays a crucial role in high performance digital systems. The paper proposes a systematic method to formalize and verify adders in a formal proof assistant COQ. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of interest in industry, in a faithful, scalable, and modularized way. The methodology can be extended to other adder architectures as well.

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Wei, Chi Pin, Zhao Lin Li, Hao Liu und Zhi Xiang Chen. „Design of a Random Test Platform for DSP Serials Used in Embedded Systems“. Advanced Materials Research 267 (Juni 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.

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Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.

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Huang, Hong Hsin, Chien Yuan Liu, Ming Chih Huang, I. Chun Ko und Jia Ming Lee. „Digital I/O Training Kit Development for Arduino Platforms“. Applied Mechanics and Materials 214 (November 2012): 649–53. http://dx.doi.org/10.4028/www.scientific.net/amm.214.649.

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In this paper, a DIO training kit developed for fundamental embedded system learning was presented. The jobs of the research comprised the developments of a microcontroller board, four DIO functional modules with multiplexing circuit, and some control software. At present, the DIO training kit was implemented on an experimental breadboard. The integration and verification of hardware and software were conducted successfully. The results showed that the DIO training kit for Arduino platform are extremely suitable to support the Arduino based embedded systems training.

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Novikov, Sergey V., und Andrey A. Sazonov. „Digital certification of aviation equipment on the basis of “Siemens PLM Software” technologies“. Econimics Journal 1, Nr. 1 (15.12.2019): 13–19. http://dx.doi.org/10.46502/issn.2711-2454/2019.1.02.

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The article is dedicated to the analysis of digital certification of aviation equipment on the basis of multifunctional “Siemens PLM Software” (PLM - Product Lifecycle Management) technologies and “Verification Management” solution. In the theoretical part of the article, the authors point out that during certification a project usually goes through two stages: validation and verification. The first stage involves checking the project requirements for correctness and completeness, while the second stage aims to confirm that the designed aircraft is fully consistent with the validated requirements for it. The article states that the implementation of modern systems engineering practices is based on various instrumental components, methodology, and professional competence and is implemented as part of the general PLM strategy of an enterprise using “Siemens Digital Industries Software” products. In the course of the research, the authors of the article came to the conclusion that “Verification Management” solution in the “Teamcenter Siemens PLM Software” system helps enterprises in the aerospace and defence industries to successfully implement projects on creation of innovative products within a given timeframe and budget. “Verification Management” solution forms a closed traceability cycle for all stages of the control process of project decisions aimed to confirm compliance of the design with specified requirements. “Verification Management Catalyst” module accelerates the enterprise’s transition to digital technology; therefore, this transition improves reliability and productivity while lowering the total cost of ownership. “Teamcenter” system supports verification of the implementation of product development programs, reduces the time and cost of project decisions, which ultimately improves the entire work of the enterprise. “Verification Management” solution is a fully functional lifecycle management solution that is able to transmit product requirements and their changes to all participants of the design process.

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Gao, Feng, Yun Wu und Shang Qiong Lu. „LabVIEW-Based Virtual Laboratory for Digital Signal Processing“. Advanced Materials Research 268-270 (Juli 2011): 2150–57. http://dx.doi.org/10.4028/www.scientific.net/amr.268-270.2150.

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Based on National Instruments LabVIEW 2009, a network-edition virtual laboratory for digital signal processing (DSP) has been developed. Which is composed of three functional modules, that is, virtual experiment table, information management, and network communication. Hereinto, virtual experiment table is composed of two sub-modules, i.e. resource & document and simulation experiment; information management module is composed of four sub-modules, i.e. database, user registration, security verification and system management; network communication module is implemented by LabVIEW Web Server. The DSP Virtual Laboratory is suit for experimental teaching of a range of subjects, such as Digital Signal Processing, Signals & Systems, etc. And the designed virtual laboratory can provide users with a remote virtual experimental platform without time and space constraints.

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Yan, Qun Min, und Juan Juan Zhu. „Design and Simulation Analysis of Aircraft Dynamic System“. Advanced Materials Research 314-316 (August 2011): 511–17. http://dx.doi.org/10.4028/www.scientific.net/amr.314-316.511.

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Aircraft dynamic systems digital simulation platform modeling was construct based on engineering needs and provide the basis of experimental data. Combined with dynamic system characteristics and saber software characteristics .In the Saber simulation software, used the schematic-based, based on functional requirements and the modeling method based on experimental data to establish a dynamic system of different parts of the device model, and according to different modeling methods established by the electrical load model and control model of power systems consisting of mixed-signal model. Finally, experimental verification of the whole system model, simulation results compared with the experimental results prove the accuracy of the system model, effective and practical.

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Szuster, Marcin, und Bartłomiej Kozioł. „Hidden Security Breaches in Automatic Control of Technological Processes“. Pomiary Automatyka Robotyka 25, Nr. 2 (30.06.2021): 31–39. http://dx.doi.org/10.14313/par_240/31.

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The progressing automation and robotization in the industrial plants as well as the increasing complexity of the control systems of integrated machines make it necessary to constantly improve the functional safety of machines through the correct validation of safety systems. Despite the validation process carried out, the potential software errors may reveal during the usage of the machine as hidden security breaches. The article presents examples of security breaches of real machine tools and attempts to implement solutions of automated mechanisms for detecting security problems. Another aspect of the article is the new approach for detecting hidden security breaches. Using the „digital twin” model of the machine, a program that generates a sequence of events for testing control systems, and the use of a virtual reality (visual verification of the safety programs), it is possible to maximize the functional safety functions of the machine.

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Vorobyov, Oleg V., und Alexey I. Rybakov. „Selection and Application of the Data Transfer Operating Protocol Software Architecture for the Software-Defined Radio“. Journal of the Russian Universities. Radioelectronics 22, Nr. 4 (01.10.2019): 18–30. http://dx.doi.org/10.32603/1993-8985-2019-22-4-18-30.

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Introduction. The demodulator structure is described and decoding algorithm for signal-code constructions development is presented. The structure and functional description of the developed software (SW), which is designed for the installation of the software-defined radio in the radio stations layout, are presented. The frame structures of the broadcast and half-duplex protocols, modulation/demodulation and subsequent digital signal processing in existing and prospect radio communication systems are considered.Objective. Investigation of modulation/demodulation methods and subsequent digital signal processing along with requirements imposed by them on the network stations equipment and system operation algorithms.Materials and methods. The software for the software-defined radio system layout is developed to demonstrate the reliability and operability of the proposed algorithm and transmission protocol. It can be used to receive and transmit information by using ionospheric reflections. Present design takes into account existing standards and amateur systems such as WinLink and information systems (digital and analog) for the "physical" and "channel" levels.Results. The structure and functional description of the developed software for the software-defined radio system layout are given. The possible realization of the software-defined radio channel for data receiving and transfer by using ionospheric reflections is presented. The results of technical solutions experimental testing are shown. The software can use hardware and software to control the transceiver module, which includes the SunSDR2 transceiver and antenna amplifier.Conclusion. The structure and functional description of the developed software are presented as a result of the software architecture selection and its application investigation. It is concluded that the reliability and operability justification of the proposed algorithm and transmission protocol is relevant in a field of the digital receivers development for communication systems of various purposes. The presented experimental studies data on verification of the proposed algorithm show the feasibility of present solutions on the qualitative utilization of the channel resource by using the described code structure. The present results allow to determine the most appropriate and efficient way of the software development allowing to create a technique that can meet the maximum number of possible assignments of radio access channels.

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Lukonina, Y. A. „Electronic proceedings in the courts of verification instances as one of the digital modifications of justice in civil cases“. Russian justice 1 (28.01.2021): 52–54. http://dx.doi.org/10.18572/0131-6761-2021-1-52-54.

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The article reveals the main features of the judicial system transformation as a result of the October procedural reform, when the appeal and cassation systems of general jurisdiction began to function in the Russian Federation. The author aims to conduct a comprehensive study of the possibilities of appellate and cassation instances digitalization. Dialectical, analytical, comparative and structural methods used in considering the most relevant legislative innovation help to demonstrate the conflict between digitalization and the creation of structurally independent courts. The author notes the complication of the implementation of the mechanism of the right to judicial protection in the conditions of positive dynamics of the functioning of new units. Analyzing the procedural features of the current procedure for initiating proceedings in the verification instances, the author comes to the conclusion that it is necessary to digitally modernize the administration of justice in courts of appeal and cassation courts. New approaches to the introduction of electronic communication are proposed by creating a modern functional for the implementation of the right of appeal and cassation by analogy with the existing mechanisms for the provision of public services. The results of the study can become a trigger for further reform of the judicial system in the light of the digitalization of justice in civil cases.

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Park, Chester Sungchung, Sunwoo Kim, Jooho Wang und Sungkyung Park. „Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation“. Electronics 10, Nr. 3 (20.01.2021): 231. http://dx.doi.org/10.3390/electronics10030231.

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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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Gassoumi, Ismail, Lamjed Touil, Bouraoui Ouni und Abdellatif Mtibaa. „An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology“. Journal of Electrical and Computer Engineering 2019 (02.10.2019): 1–11. http://dx.doi.org/10.1155/2019/9029526.

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Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential techniques in image and video compression systems, and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, quantum-dot cellular automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Furthermore, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption, and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool, is applied to estimate the power dissipation of the proposed circuit. The suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new window of opportunity for low power image processing systems.

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Bartoněk, Dalibor. „Solving Big GIS Projects on Desktop Computers“. Kartografija i geoinformacije 18, Nr. 32 (15.12.2019): 44–62. http://dx.doi.org/10.32909/kg.18.32.4.

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We are witnessing great developments in digital information technologies. The situation encroaches on spatial data, which contain both attributive and localization features, and this determines their position unequally within an obligatory coordinate system. These changes have resulted in the rapid growth of digital data, significantly supported by technical advances regarding the devices which produce them. As technology for making spatial data advances, methods and software for big data processing are falling behind. Paradoxically, only about 2% of the total volume of data is actually used. Big data processing often requires high computation performance hardware and software. Only a few users possess the appropriate information infrastructure. The proportion of processed data would improve if big data could be processed by ordinary users. In geographical information systems (GIS), these problems arise when solving projects related to extensive territory or considerable secondary complexity, which require big data processing. This paper focuses on the creation and verification of methods by which it would be possible to process effectively extensive projects in GIS supported by desktop hardware and software. It is a project regarding new quick methods for the functional reduction of the data volume, optimization of processing, edge detection in 3D and automated vectorization.

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Noorsal, Emilia, Saharul Arof, Saiful Zaimy Yahaya, Zakaria Hussain, Daniel Kho und Yusnita Mohd Ali. „Design of an FPGA-Based Fuzzy Feedback Controller for Closed-Loop FES in Knee Joint Model“. Micromachines 12, Nr. 8 (16.08.2021): 968. http://dx.doi.org/10.3390/mi12080968.

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Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the open-loop stimulation strategy. To reduce the early muscle fatigue phenomenon, a closed-loop FES system is proposed to track the angle of the limb’s movement and provide an accurate amount of charge according to the desired reference angle. Among the existing feedback controllers, fuzzy logic controller (FLC) has been found to exhibit good control performance in handling complex non-linear systems without developing any complex mathematical model. Recently, there has been considerable interest in the implementation of FLC in hardware embedded systems. Therefore, in this paper, a digital fuzzy feedback controller (FFC) embedded in a field-programmable gate array (FPGA) board was proposed. The digital FFC mainly consists of an analog-to-digital converter (ADC) Data Acquisition and FLC sub-modules. The FFC was designed to monitor and control the progress of knee extension movement by regulating the stimulus pulse width duration to meet the target angle. The knee is expected to extend to a maximum reference angle setting (70°, 40° or 30°) from its normal position of 0° once the stimulus charge is applied to the muscle by the FES device. Initially, the FLC was modelled using MATLAB Simulink. Then, the FLC was hardcoded into digital logic using hardware description language (HDL) Verilog codes. Thereafter, the performance of the digital FLC was tested with a knee extension model using the HDL co-simulation technique in MATLAB Simulink. Finally, for real-time verification, the designed digital FFC was downloaded to the Intel FPGA (DE2-115) board. The digital FFC utilized only 4% of the total FPGA (Cyclone IV E) logic elements (LEs) and required 238 µs to regulate stimulus pulse width data, including 3 µs for the FLC computation. The high processing speed of the digital FFC enables the stimulus pulse width duration to be updated every stimulation cycle. Furthermore, the implemented digital FFC has demonstrated good control performance in accurately controlling the stimulus pulse width duration to reach the desired reference angle with very small overshoot (1.4°) and steady-state error (0.4°). These promising results are very useful for a real-world closed-loop FES application.

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Kozlyuk, Iryna, und Yuliia Kovalenko. „Reliability of computer structures of integrated modular avionics for hardware configurations“. System research and information technologies, Nr. 2 (14.09.2021): 84–93. http://dx.doi.org/10.20535/srit.2308-8893.2021.2.07.

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The problem of designing advanced computing systems in the class of structures of integrated modular avionics is considered. The unified topology of the internal network of the computer on the basis of Space Wire exchange channels and variants of its execution for various onboard applications is offered. Equivalent reliability schemes of each of the specific structures are introduced and the probabilities of trouble-free operation of each structure are analyzed. Families of graphic dependencies are given. The analysis of the existing principles and algorithms for testing multiprocessor multimodal onboard digital computer systems is given; the new testing algorithm for the multiprocessor systems which follows the software design standards for products of integrated modular avionics is offered. The structure of the unified automated workplace for checking the functional modules of integrated modular avionics is considered. Specific requirements inherent in the workplaces for testing integrated avionics are identified: an increased level of control of the hardware component of products; the ability to simulate the failure state of individual components of avionics to check the mode of reconfiguration of the computer system; modular construction of software with the division of verification tests into components performed at the level of each CPM and the computer as a whole in single-task and multitasking modes; openness of architecture of a workplace, which provides an ability to change the level of control complexity of a product and control of one class of complexity; intra-project unification of both hardware and software of the workstation of the inspection.

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Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков und Б. И. Жилин. „DEVELOPMENT OF RECONFIGURABLE DEVICES BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS“. ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, Nr. 6 (10.01.2021): 90–97. http://dx.doi.org/10.36622/vstu.2020.16.6.013.

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Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Программируемые логические интегральные схемы (ПЛИС) представляют собой конфигурируемые интегральные схемы, логика работы которых определяется посредством их программирования. Применение ПЛИС для задач цифровой обработки сигналов позволяет получать устройства, способные менять конфигурацию, подстраиваться под определенную задачу за счет их гибко изменяемой, программируемой структуры. При разработке сложных устройств могут применяться в качестве компонентов для проектирования готовые блоки - IP-ядра или сложно-функциональные блоки (СФ-блоки). Использование программных СФ-блоков позволяет наиболее эффективно задействовать их в конечной структуре, в значительной степени сократить затраты на проектирование. Цель работы состоит в построении RTL модели СФ-блока цифровой обработки сигналов, его верификации как на логическом уровне, так и физическом Digital filtering of recognized signals is an indispensable procedure for the detection and recognition of messages. Filtering is understood as any transformation of signals in which certain relationships between different signal parameters are purposefully changed in the input sequence of the processed data. Systems that selectively change the shape of signals, eliminate or reduce interference, extract certain information from the signals, and so on, are called filters. Accordingly, filters with any purpose are a special case of signal conversion systems. Programmable logic integrated circuits (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs for digital signal processing tasks makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made blocks - IP-cores or complex-functional blocks (SF blocks) - can be used as components for design. The use of software SF-blocks allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. The purpose of the work is to build an RTL model of the SF-block for digital signal processing, its verification both at the logical and physical levels

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Dubrovskaya, S. A., und R. V. Ryakhov. „Landscape-ecological zoning of the Orenburg city based on geomorphometric, ecological and economic features of the territory“. Geoinformatika, Nr. 4 (2020): 63–70. http://dx.doi.org/10.47148/1609-364x-2020-4-63-70.

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The article is a complex of detailed studies of the natural landscape structure and the ecological and functional purpose of the urbanized territory. The relevance of the study is determined by the fact that it is necessary to introduce territorial planning documents (master plan) and landscape planning projects, with the allocation of specific sections of the natural-ecological framework of cities. The study was conducted with the aim of studying the natural-technical geosystem to optimize the interaction of nature transformed by human activities and the socio-economic needs of society. To achieve this goal, a typification scheme for landscape structures of urban space was developed for the first time, based on a digital terrain model and using the method of automated typological zoning of relief using its morphometric data using artificial neural networks. As a result of automated training of the neural network model and verification of the data obtained, 15 classes were obtained (taxa tracts) and established the correspondence of each type of landscape in space with an indication of geomorphometric characteristics. Based on the digitized model of the functional zoning of Orenburg and types of landscapes, for the first time, an integrated map of the landscape-ecological zoning of urban space was developed and classifications of types and types of landscape zones were presented: primary and mixed. Cartographic models of the natural-landscape component of Orenburg, which is the natural-ecological framework of the object of study – recreational zones and a hydrographic network are separately presented. The results obtained are important for maintaining the landscape functions of the urbanized area, forecasting changes, and minimizing the effects of anthropogenic impact. Key words: urban planning, natural-ecological framework, functional types of land use, technological systems, type of landscape purpose, landscape, geomorphometric features, neural network algorithm.

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Qin, Feng, Ying Lin und Diqiang Lu. „Hardware-in-the-loop simulation of high-speed maglev transportation five-segment propulsion system based on dSPACE“. Transportation Systems and Technology 4, Nr. 2 (13.09.2018): 62–72. http://dx.doi.org/10.17816/transsyst20184262-72.

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Aim: For exploring and testing the key technology of high-speed maglev transportation propulsion control system, this paper designs and establishes a hardware-in-the-loop (HIL) real-time simulation system of the high-speed maglev transportation five-segment propulsion system. Materials and methods of the studies: According to the route conditions and propulsion segment division of Shanghai maglev demonstration and operation line, the real-time simulation platform based on dSPACE multiprocessor systems is implemented. The simulation system can achieve the functional simulation of all the high-power related equipment in the 5-segment area, including 8 sets of high-power converter units, 2 sets of medium-power converter units, 2 sets of low-power converter units, five-segment trackside switch stations and long-stator linear synchronous motors. The mathematical models of linear motors and converters are built in MATLAB/Simulink and System Generator, after compiling, they can be downloaded and executed in Field Programmable Logic Array (FPGA). All the interfaces connecting the simulation system to the propulsion control system physical equipment use real physical components as in the field, such as analog I/O, digital I/O, optical signals and Profibus. Results: By using CPU+FPGA hardware configuration, the simulation steps are greatly shortened and the response speed and accuracy of real-time simulation system are improved. The simulation system can simulate multiple operating modes such as multi-segment, multi-vehicle, double-track, double-feeding, step-by-step stator section changeover, and so on. The simulation results show that the maximum speed of the simulation system can reach 500 km/h. Conclusion: This HIL system can provide detailed real-time on-line test and verification of high speed maglev propulsion control system.

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Zeller, Andreas, Nasser Jazdi und Michael Weyrich. „Functional verification of distributed automation systems“. International Journal of Advanced Manufacturing Technology 105, Nr. 9 (03.07.2019): 3991–4004. http://dx.doi.org/10.1007/s00170-019-03791-2.

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22

Radu, Mihaela E., und Shannon M. Sexton. „Integrating Extensive Functional Verification Into Digital Design Education“. IEEE Transactions on Education 51, Nr. 3 (August 2008): 385–93. http://dx.doi.org/10.1109/te.2008.919692.

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23

Bottacci, L. „Formal specification and verification of digital systems“. Microelectronics Journal 25, Nr. 5 (August 1994): 406. http://dx.doi.org/10.1016/0026-2692(94)90097-3.

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Sciuto, Donatella, und Fabrizio Lombardi. „Functional testing and verification of array systems“. Microprocessors and Microsystems 13, Nr. 6 (Juli 1989): 403–12. http://dx.doi.org/10.1016/0141-9331(89)90049-5.

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25

Brauer, E. J., und Sung-Mo Kang. „An algorithm for functional verification of digital ECL circuits“. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, Nr. 12 (1995): 1546–56. http://dx.doi.org/10.1109/43.476584.

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26

Brezocnik, Zmago, und Bogomir Horvat. „AUTOMATIC FORMAL VERIFICATION OF DIGITAL SYSTEMS USING PROLOG“. ACM SIGCHI Bulletin 19, Nr. 4 (April 1988): 13–14. http://dx.doi.org/10.1145/43950.1047330.

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Gong, Lingkan, und Oliver Diessel. „Simulation-based functional verification of dynamically reconfigurable systems“. ACM Transactions on Embedded Computing Systems 13, Nr. 4 (05.12.2014): 1–23. http://dx.doi.org/10.1145/2560042.

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Dotan, Yoheved, und Benjamin Arazi. „Design verification of digital systems based on logic programming“. Computers & Electrical Engineering 16, Nr. 3 (Januar 1990): 125–38. http://dx.doi.org/10.1016/0045-7906(90)90018-b.

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Shaik, Samdhani, und P. Balanagu. „Functional Verification Architecture Implementation for Power Optimized FIR Filter“. International Journal of Engineering & Technology 7, Nr. 2.20 (18.04.2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.

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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.

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Das, Dipankar, P. P. Chakrabarti und Rajeev Kumar. „Functional verification of task partitioning for multiprocessor embedded systems“. ACM Transactions on Design Automation of Electronic Systems 12, Nr. 4 (September 2007): 44. http://dx.doi.org/10.1145/1278349.1278357.

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31

Kutsak, N. Yu, und V. V. Podymov. „Formal Verification of Three-Valued Digital Waveforms“. Automatic Control and Computer Sciences 54, Nr. 7 (Dezember 2020): 630–44. http://dx.doi.org/10.3103/s0146411620070135.

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Amellal, S., und B. Kaminska. „Functional synthesis of digital systems with TASS“. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, Nr. 5 (Mai 1994): 537–52. http://dx.doi.org/10.1109/43.277628.

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Zhirabok, A. N., und O. V. Preobrazhenskaya. „Functional diagnosis of digital systems using duplicates“. Measurement Techniques 41, Nr. 7 (Juli 1998): 596–600. http://dx.doi.org/10.1007/bf02504881.

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34

Xiao, Da, Yue Fei Zhu, Sheng Li Liu, Dong Xia Wang und You Qiang Luo. „Digital Hardware Design Formal Verification Based on HOL System“. Applied Mechanics and Materials 716-717 (Dezember 2014): 1382–86. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1382.

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This article selects HOL theorem proving systems for hardware Trojan detection and gives the symbol and meaning of theorem proving systems, and then introduces the symbol table, item and the meaning of HOL theorem proving systems. In order to solve the theorem proving the application of the system in hardware Trojan detection requirements, this article analyses basic hardware Trojan detection methods which applies for theorem proving systems and introduces the implementation methods and process of theorem proving about hardware Trojan detection.

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Cox, Arlen, Sriram Sankaranarayanan und Bor-Yuh Evan Chang. „A bit too precise? Verification of quantized digital filters“. International Journal on Software Tools for Technology Transfer 16, Nr. 2 (23.06.2013): 175–90. http://dx.doi.org/10.1007/s10009-013-0279-9.

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Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan und Ahtisham Shaheen. „Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation“. Applied Mechanics and Materials 892 (Juni 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.

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To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust design. In this paper, we report our results of formal verifications of two simple hardware circuits designed in the formal description language VeriFormal. Using the VeriFormal simulator and the accompanied type checker tools, we prove reliability properties type safety, functional correctness and functional equivalence of the digital circuits.

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Chen, Hao, Fu Sheng Chen, Jie Xiang, Li Man Shen und E. Ying Li. „Research on the Digital Metering System and Verification Method of Digital Electrical Energy Meter“. Advanced Materials Research 718-720 (Juli 2013): 715–20. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.715.

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The digital energy metering system applied in the smart substation are quite different from the traditional meter system, so its nessary to do some research on the digital metering system. With comparing the digital metering systems to traditional metering system, the application structure and characteristics of digital metering system is discussed, the traceability model of the digital electrical energy meter based on IEC 61850 protocol is also given.In the next part,we designed the verification system for digital energy meter, besides the standard digital power source in the test device, calibration device and the general controller are expounded. The performance of the verification system designed in this article shows that the method could be an effective solution to the verification and traceability of digital energy meter.

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Kutsak, Nina Yu, und Vladislav V. Podymov. „Formal Verification of Three-Valued Digital Waveforms“. Modeling and Analysis of Information Systems 26, Nr. 3 (28.09.2019): 332–50. http://dx.doi.org/10.18255/1818-1015-2019-3-332-350.

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We investigate a formal verification problem (mathematically rigorous correctness checking) for digital waveforms used in practical development of digital microelectronic devices (digital circuits) at early design stages. According to modern methodologies, a digital circuit design starts at high abstraction levels provided by hardware description languages (HDLs). One of essential steps of an HDLbased circuit design is an HDL code debug, similar to the same step of program development in means and importance. A popular way of an HDL code debug is based on extraction and analysis of a waveform, which is a collection of plots for digital signals: functional descriptions of value changes related to selected circuit places in real time. We propose mathematical means for automation of correctness checking for such waveforms based on notions and methods of formal verification against temporal logic formulae, and focus on such typical featues of HDL-related digital signals and corresponding (informal) properties, such as real time, three-valuededness, and presence of signal edges. The three-valuededness means that at any given time, besides basic logical values 0 and 1, a signal may have a special undefined value: one of the values 0 and 1, but which one of them is either not known, or not important. An edge point of a signal is a time point at which the signal changes its value. The main results are mathematical notions, propositions, and algorithms which allow to formalize and solve a formal verification problem for considered waveforms, including: definitions for signals and waveforms which the mentioned typical digital signal features; a temporal logic suitable for formalization of waveform correctness properties, and a related verification problem statement; a solution technique for the verification problem, which is based on reduction to signal transfromation and analysis; a corresponding verification algorithm together with its correctness proof and “reasonable” complexity bounds.

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Wang, Li-C., Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir und Manish Pandey. „Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems“. Design Automation for Embedded Systems 8, Nr. 2/3 (Juni 2003): 173–88. http://dx.doi.org/10.1023/b:daem.0000003961.86651.2b.

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Ludden, J. M., W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B. L. Chu, M. L. Behm et al. „Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems“. IBM Journal of Research and Development 46, Nr. 1 (Januar 2002): 53–76. http://dx.doi.org/10.1147/rd.461.0053.

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Victor, D. W., J. M. Ludden, R. D. Peterson, B. S. Nelson, W. K. Sharp, J. K. Hsu, B. L. Chu et al. „Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems“. IBM Journal of Research and Development 49, Nr. 4.5 (Juli 2005): 541–53. http://dx.doi.org/10.1147/rd.494.0541.

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42

Jani, Lázár, und András Poppe. „Framework for thermal-aware verification of digital and mixed signal systems“. Microelectronics Reliability 79 (Dezember 2017): 499–508. http://dx.doi.org/10.1016/j.microrel.2017.03.023.

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43

Macii, E., B. Plessier und F. Somenzi. „Formal verification of digital systems by automatic reduction of data paths“. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, Nr. 10 (1997): 1136–56. http://dx.doi.org/10.1109/43.662676.

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44

Bessa, Iury, Hussama Ismail, Reinaldo Palhares, Lucas Cordeiro und Joa Edgar Chaves Filho. „Formal Non-Fragile Stability Verification of Digital Control Systems with Uncertainty“. IEEE Transactions on Computers 66, Nr. 3 (01.03.2017): 545–52. http://dx.doi.org/10.1109/tc.2016.2601328.

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45

Hanna, F. K., und N. Daeche. „Specification and verification of digital systems using higher-order predicate logic“. IEE Proceedings E Computers and Digital Techniques 133, Nr. 5 (1986): 242. http://dx.doi.org/10.1049/ip-e.1986.0031.

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46

Kushik, N. G., N. V. Evtushenko und S. N. Torgaev. „Mutation Testing for Effective Verification of Digital Components of Physical Systems“. Russian Physics Journal 58, Nr. 8 (Dezember 2015): 1128–33. http://dx.doi.org/10.1007/s11182-015-0622-6.

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47

Yun, Sangpil, Yongjin Seo, Bup-Ki Min und Hyeon Soo Kim. „Development of a Test Framework for Functional and Non-functional Verification of Distributed Systems“. Journal of Internet Computing and Services 15, Nr. 5 (31.10.2014): 107–21. http://dx.doi.org/10.7472/jksii.2014.15.5.107.

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48

Ahmad, Manzoor, Nicolas Belloir und Jean-Michel Bruel. „Modeling and verification of Functional and Non-Functional Requirements of ambient Self-Adaptive Systems“. Journal of Systems and Software 107 (September 2015): 50–70. http://dx.doi.org/10.1016/j.jss.2015.05.028.

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49

Kang, Sungjoo, Ingeol Chun und Hyeon-Soo Kim. „Design and Implementation of Runtime Verification Framework for Cyber-Physical Production Systems“. Journal of Engineering 2019 (13.11.2019): 1–11. http://dx.doi.org/10.1155/2019/2875236.

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Traditional factories are turning into smart factories with the advent of various ICT technologies, and various control decisions are derived by AI technologies. In this circumstance, runtime verification of a control command is important for zero-defect manufacturing processes but challengeable because factories of the future are highly complex and heterogeneous systems. In this paper, we propose DigTwinOps, a Digital Twin framework for Runtime Verification of Cyber-Physical Production Systems (CPPSs). DigTwinOps features a Digital Twin Execution Engine (DTEE) that manages a Digital Twin Model to synchronize states of a real CPPS object in a production environment. With a monitoring and simulation combination process, a human worker can observe the states of the CPPS object and verify the effectiveness of control commands before applying it to a real production environment. The proposed framework is applied to a CPPS prototype production system, and the results show that the framework can work effectively in the controllability verification of control commands.

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Skripnichenko, M. N., und I. A. Lipatov. „DESIGN AND VERIFICATION FLOW OF MULTI-STAGE SIGMA-DELTA ADC DIGITAL CORE“. Issues of radio electronics, Nr. 8 (20.08.2018): 56–63. http://dx.doi.org/10.21778/2218-5453-2018-8-56-63.

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There is a need for analog-to-digital converters with high signal-to-noise ratio and large signal bandwidth to solve a number of radiolocation problems. Developing such ADC is a challenge in the analog core, digital core and verification. The design flow of the digital core must take into account the possibility of changing the analog core specification at any design stage, provide the ability to quickly obtain the synthesizable RTL code of the device and conduct its functional verification. Automation tools were used to reduce the time spent on development and verification. This article describes the developed software package that generates the synthesizable RTL code and the verification environment configurations for each stage of development of the analog core of the multi-stage sigma-delta ADC.

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