Thematische Bibliographien / Functional verification of digital systems

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Auswahl der wissenschaftlichen Literatur zum Thema „Functional verification of digital systems“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 7. Februar 2022

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Zeitschriftenartikel zum Thema "Functional verification of digital systems"

Franco, Ricardo Augusto Pereira, Karina Rocha Gomes Da Silva und Cássio Leonardo Rodrigues. „Genetic Algorithm applied to the Functional Verification in Digital Systems“. Journal of Integrated Circuits and Systems 13, Nr. 1 (24.08.2018): 1–9. http://dx.doi.org/10.29292/jics.v13i1.20.

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A critical stage of a hardware design is the hardware verification phase. The verification phase corresponds to the biggest bottleneck in a hardware design. The VeriSC methodology is a methodology to perform the hardware verification through of functional verification. In this work, we propose a novel improvement in VeriSC methodology data generation using Genetic Algorithms and feedback approach. The proposed algorithm will modify the data generation of this methodology, whose objective is to reduce the verification time and to improve the generated data. A DPCM and two modules of MPEG-DECODER are used as case studies. The results not only show that the proposed approach can achieve functional coverage with good performance, but also show that the execution time is better or similar to the former method used in VeriSC methodology. These results demonstrate the Genetic Algorithm approach explores the search space better than older approach. The data generation performed can also be used in other methodologies without any problem.

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Alekhin, V. A. „Designing Electronic Systems Using SystemC and SystemC–AMS“. Russian Technological Journal 8, Nr. 4 (06.08.2020): 79–95. http://dx.doi.org/10.32362/2500-316x-2020-8-4-79-95.

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Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

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Chen, Fu Long, Zhao Xia Zhu und Xiao Ya Fan. „FPGA-Based In-Circuit Verification of Digital Systems“. Advanced Materials Research 187 (Februar 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.

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Wang, Qian, Xiaoyu Song, Ming Gu und Jiaguang Sun. „Functional Verification of High Performance Adders in COQ“. Journal of Applied Mathematics 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/197252.

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Addition arithmetic design plays a crucial role in high performance digital systems. The paper proposes a systematic method to formalize and verify adders in a formal proof assistant COQ. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of interest in industry, in a faithful, scalable, and modularized way. The methodology can be extended to other adder architectures as well.

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Wei, Chi Pin, Zhao Lin Li, Hao Liu und Zhi Xiang Chen. „Design of a Random Test Platform for DSP Serials Used in Embedded Systems“. Advanced Materials Research 267 (Juni 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.

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Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.

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Huang, Hong Hsin, Chien Yuan Liu, Ming Chih Huang, I. Chun Ko und Jia Ming Lee. „Digital I/O Training Kit Development for Arduino Platforms“. Applied Mechanics and Materials 214 (November 2012): 649–53. http://dx.doi.org/10.4028/www.scientific.net/amm.214.649.

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In this paper, a DIO training kit developed for fundamental embedded system learning was presented. The jobs of the research comprised the developments of a microcontroller board, four DIO functional modules with multiplexing circuit, and some control software. At present, the DIO training kit was implemented on an experimental breadboard. The integration and verification of hardware and software were conducted successfully. The results showed that the DIO training kit for Arduino platform are extremely suitable to support the Arduino based embedded systems training.

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Novikov, Sergey V., und Andrey A. Sazonov. „Digital certification of aviation equipment on the basis of “Siemens PLM Software” technologies“. Econimics Journal 1, Nr. 1 (15.12.2019): 13–19. http://dx.doi.org/10.46502/issn.2711-2454/2019.1.02.

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The article is dedicated to the analysis of digital certification of aviation equipment on the basis of multifunctional “Siemens PLM Software” (PLM - Product Lifecycle Management) technologies and “Verification Management” solution. In the theoretical part of the article, the authors point out that during certification a project usually goes through two stages: validation and verification. The first stage involves checking the project requirements for correctness and completeness, while the second stage aims to confirm that the designed aircraft is fully consistent with the validated requirements for it. The article states that the implementation of modern systems engineering practices is based on various instrumental components, methodology, and professional competence and is implemented as part of the general PLM strategy of an enterprise using “Siemens Digital Industries Software” products. In the course of the research, the authors of the article came to the conclusion that “Verification Management” solution in the “Teamcenter Siemens PLM Software” system helps enterprises in the aerospace and defence industries to successfully implement projects on creation of innovative products within a given timeframe and budget. “Verification Management” solution forms a closed traceability cycle for all stages of the control process of project decisions aimed to confirm compliance of the design with specified requirements. “Verification Management Catalyst” module accelerates the enterprise’s transition to digital technology; therefore, this transition improves reliability and productivity while lowering the total cost of ownership. “Teamcenter” system supports verification of the implementation of product development programs, reduces the time and cost of project decisions, which ultimately improves the entire work of the enterprise. “Verification Management” solution is a fully functional lifecycle management solution that is able to transmit product requirements and their changes to all participants of the design process.

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Gao, Feng, Yun Wu und Shang Qiong Lu. „LabVIEW-Based Virtual Laboratory for Digital Signal Processing“. Advanced Materials Research 268-270 (Juli 2011): 2150–57. http://dx.doi.org/10.4028/www.scientific.net/amr.268-270.2150.

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Based on National Instruments LabVIEW 2009, a network-edition virtual laboratory for digital signal processing (DSP) has been developed. Which is composed of three functional modules, that is, virtual experiment table, information management, and network communication. Hereinto, virtual experiment table is composed of two sub-modules, i.e. resource & document and simulation experiment; information management module is composed of four sub-modules, i.e. database, user registration, security verification and system management; network communication module is implemented by LabVIEW Web Server. The DSP Virtual Laboratory is suit for experimental teaching of a range of subjects, such as Digital Signal Processing, Signals & Systems, etc. And the designed virtual laboratory can provide users with a remote virtual experimental platform without time and space constraints.

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Yan, Qun Min, und Juan Juan Zhu. „Design and Simulation Analysis of Aircraft Dynamic System“. Advanced Materials Research 314-316 (August 2011): 511–17. http://dx.doi.org/10.4028/www.scientific.net/amr.314-316.511.

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Aircraft dynamic systems digital simulation platform modeling was construct based on engineering needs and provide the basis of experimental data. Combined with dynamic system characteristics and saber software characteristics .In the Saber simulation software, used the schematic-based, based on functional requirements and the modeling method based on experimental data to establish a dynamic system of different parts of the device model, and according to different modeling methods established by the electrical load model and control model of power systems consisting of mixed-signal model. Finally, experimental verification of the whole system model, simulation results compared with the experimental results prove the accuracy of the system model, effective and practical.

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Szuster, Marcin, und Bartłomiej Kozioł. „Hidden Security Breaches in Automatic Control of Technological Processes“. Pomiary Automatyka Robotyka 25, Nr. 2 (30.06.2021): 31–39. http://dx.doi.org/10.14313/par_240/31.

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The progressing automation and robotization in the industrial plants as well as the increasing complexity of the control systems of integrated machines make it necessary to constantly improve the functional safety of machines through the correct validation of safety systems. Despite the validation process carried out, the potential software errors may reveal during the usage of the machine as hidden security breaches. The article presents examples of security breaches of real machine tools and attempts to implement solutions of automated mechanisms for detecting security problems. Another aspect of the article is the new approach for detecting hidden security breaches. Using the „digital twin” model of the machine, a program that generates a sequence of events for testing control systems, and the use of a virtual reality (visual verification of the safety programs), it is possible to maximize the functional safety functions of the machine.

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Dissertationen zum Thema "Functional verification of digital systems"

Malkoc, Veysi. „Sequential alignment and position verification system for functional proton radiosurgery“. CSUSB ScholarWorks, 2004. https://scholarworks.lib.csusb.edu/etd-project/2535.

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The purpose of this project is to improve the existing version of the Sequential Alignment and Position Verification System (SAPVS) for functional proton radiosurgery and to evaluate its performance after improvement .

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Prado, Bruno Otávio Piedade. „IVM: uma metodologia de verificação funcional interoperável, iterativa e incremental“. reponame:Repositório Institucional da UFS, 2009. https://ri.ufs.br/handle/riufs/1672.

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A crescente demanda por produtos eletrônicos e a capacidade cada vez maior de integração criaram sistemas extremamente complexos em chips, conhecidos como Systemon-Chip ou SoC. Seguindo em sentido oposto a esta tendência, os prazos (time-to-market) para que estes sistemas sejam construídos vem continuamente sendo reduzidos, obrigando que muito mais funcionalidades sejam implementadas em períodos cada vez menores de tempo. A necessidade de um maior controle de qualidade do produto final demanda a atividade de Verificação Funcional que consiste em utilizar um conjuntos de técnicas para estimular o sistema em busca de falhas. Esta atividade é a extremamente dispendiosa e necessária, consumindo até cerca de 80% do custo final do produto. É neste contexto que se insere este trabalho, propondo uma metodologia de Verificação Funcional chamada IVM que irá fornecer todos os subsídios para garantir a entrega de sistemas de alta qualidade, e ainda atingindo as rígidas restrições temporais impostas pelo mercado. Sendo baseado em metodologias já bastante difundidas e acreditadas, como o OVM e o VeriSC, o IVM definiu uma organização arquitetural e um fluxo de atividades que incorporou as principais características de ambas as abordagens que antes estavam disjuntas. Esta integração de técnicas e conceitos resulta em um fluxo de verificação mais eficiente, permitindo que sistemas atinjam o custo, prazo e qualidade esperados._________________________________________________________________________________________ ABSTRACT: The growing demand for electronic devices and its even higher integration capability created extremely complex systems in chips, known as System-on-Chip or SoC. In a opposite way to this tendency, the time-to-market for these systems be built have been continually reduced, forcing much more functionalities be implemented in even shorten time periods. The final product quality control is assured by the Functional Verification activity that consists in a set of techniques to stimulate a system in order to find bugs. This activity is extremely expensive and necessary, responding to around 80% of final product cost. In this context this work is inserted on, proposing a Functional Verification methodology called IVM that will provide all conditions to deliver high quality systems, while keeping the hard time restrictions imposed by the market. Based in well known and trusted methodologies, as OVM and VeriSC, the IVM defined an architectural organization and an activity flow that incorporates features of both approaches that were separated from each other. This techniques and concepts integration resulted in a more efficient verification flow, allowing systems to meet the desired budget, schedule and quality.

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Vavro, Tomáš. „Periferie procesoru RISC-V“. Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.

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The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.

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Wang, Xuan. „Verification of digital controller implementations /“. Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd1073.pdf.

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Sobel, Ann E. Kelley. „Modular verification of concurrent systems /“. The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487267546983528.

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Antti, William. „Virtualized Functional Verification of Cross-Platform Software Applications“. Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-74599.

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With so many developers writing code, so many choose to become a developer every day, using tools to aid in the work process is needed. With all the testing being done for multiple different devices and sources there is a need to make it better and more efficient. In this thesis connecting the variety of different tools such as version control, project management, issue tracking and test systems is explored as a possible solution. A possible solution was implemented and then analyzed through a questionnaire that were answered by developers. For an example results as high as 75\% answering 5 if they liked the connection between the issue tracking system and the test results. 75\% also gave a 5 when asked about if they liked the way the test results were presented. The answers they gave about the implementation made it possible to conclude that it is possible to achieve a solution that can solve some of the presented problems. A better way to connect various tools to present and analyze the test results coming from multiple different sources.

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Ahmad, Manzoor. „Modeling and verification of functional and non functional requirements of ambient, self adaptative systems“. Phd thesis, Université Toulouse le Mirail - Toulouse II, 2013. http://tel.archives-ouvertes.fr/tel-00965934.

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The overall contribution of this thesis is to propose an integrated approach for modeling and verifying the requirements of Self Adaptive Systems using Model Driven Engineering techniques. Model Driven Engineering is primarily concerned with reducing the gap between problem and software implementation domains through the use of technologies that support systematic transformation of problem level abstractions to software implementations. By using these techniques, we have bridged this gap through the use of models that describe complex systems at multiple levels of abstraction and through automated support for transforming and analyzing these models. We take requirements as input and divide it into Functional and Non Functional Requirements. We then use a process to identify those requirements that are adaptable and those that cannot be changed. We then introduce the concepts of Goal Oriented Requirements Engineering for modeling the requirements of Self Adaptive Systems, where Non Functional Requirements are expressed in the form of goals which is much more rich and complete in defining relations between requirements. We have identified some problems in the conventional methods of requirements modeling and properties verification using existing techniques, which do not take into account the adaptability features associated with Self Adaptive Systems. Our proposed approach takes into account these adaptable requirements and we provide various tools and processes that we developed for the requirements modeling and verification of Self Adaptive Systems. We validate our proposed approach by applying it on two different case studies in the domain of Self Adaptive Systems.

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Karimibiuki, Mehdi. „Post-silicon code coverage for functional verification of systems-on-chip“. Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/42967.

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Post-silicon validation requires effective techniques to better evaluate the functional correctness of modern systems-on-chip. Coverage is the standard measure for validation effectiveness and is extensively used pre-silicon. However, there is little data evaluating the coverage of post-silicon validation efforts on industrial-scale designs. This thesis addresses this knowledge-gap. We employ code coverage, which is one of the most frequently used coverage technique in simulation, and apply it post-silicon. To show our coverage methodology in practice, we employ an industrial-size open source SoC that is based on the SPARC architecture and is synthesizable to FPGA. We instrument code coverage in a number of IP cores and boot Linux as our experiment to evaluate coverage --- booting an OS is a typical industrial post-silicon test. We also compare coverages between pre-silicon directed tests and the post-silicon Linux boot. Our results show that in some blocks, the pre-silicon and post-silicon tests can achieve markedly different coverage figures --- in one block we measured over 50 percentage point coverage difference between the pre- and post-silicon results, which signifies the importance of post-silicon coverage. Moreover, we calculate the area overhead imposed by the additional coverage circuitry on-chip. We apply state-of-the-art software analysis techniques to reduce the excessively large overhead yet preserve data accuracy. The results in this thesis are valuable data for guidance to future research in post-silicon coverage.

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Kriouile, Abderahman. „Formal methods for functional verification of cache-coherent systems-on-chip“. Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAM041/document.

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Les architectures des systèmes sur puce (System-on-Chip, SoC) actuelles intègrent de nombreux composants différents tels que les processeurs, les accélérateurs, les mémoires et les blocs d'entrée/sortie, certains pouvant contenir des caches. Vu que l'effort de validation basée sur la simulation, actuellement utilisée dans l'industrie, croît de façon exponentielle avec la complexité des SoCs, nous nous intéressons à des techniques de vérification formelle. Nous utilisons la boîte à outils CADP pour développer et valider un modèle formel d'un SoC générique conforme à la spécification AMBA 4 ACE récemment proposée par ARM dans le but de mettre en œuvre la cohérence de cache au niveau système. Nous utilisons une spécification orientée contraintes pour modéliser les exigences générales de cette spécification. Les propriétés du système sont vérifié à la fois sur le modèle avec contraintes et le modèle sans contraintes pour détecter les cas intéressants pour la cohérence de cache. La paramétrisation du modèle proposé a permis de produire l'ensemble complet des contre-exemples qui ne satisfont pas une certaine propriété dans le modèle non contraint. Notre approche améliore les techniques industrielles de vérification basées sur la simulation en deux aspects. D'une part, nous suggérons l'utilisation du modèle formel pour évaluer la bonne construction d'une unité de vérification d'interface. D'autre part, dans l'objectif de générer des cas de test semi-dirigés intelligents à partir des propriétés de logique temporelle, nous proposons une approche en deux étapes. La première étape consiste à générer des cas de tests abstraits au niveau système en utilisant des outils de test basé sur modèle de la boîte à outils CADP. La seconde étape consiste à affiner ces tests en cas de tests concrets au niveau de l'interface qui peuvent être exécutés en RTL grâce aux services d'un outil commercial de génération de tests dirigés par les mesures de couverture. Nous avons constaté que notre approche participe dans la transition entre la vérification du niveau interface, classiquement pratiquée dans l'industrie du matériel, et la vérification au niveau système. Notre approche facilite aussi la validation des propriétés globales du système, et permet une détection précoce des bugs, tant dans le SoC que dans les bancs de test commerciales
State-of-the-art System-on-Chip (SoC) architectures integrate many different components, such as processors, accelerators, memories, and I/O blocks. Some of those components, but not all, may have caches. Because the effort of validation with simulation-based techniques, currently used in industry, grows exponentially with the complexity of the SoC, this thesis investigates the use of formal verification techniques in this context. More precisely, we use the CADP toolbox to develop and validate a generic formal model of a heterogeneous cache-coherent SoC compliant with the recent AMBA 4 ACE specification proposed by ARM. We use a constraint-oriented specification style to model the general requirements of the specification. We verify system properties on both the constrained and unconstrained model to detect the cache coherency corner cases. We take advantage of the parametrization of the proposed model to produce a comprehensive set of counterexamples of non-satisfied properties in the unconstrained model. The results of formal verification are then used to improve the industrial simulation-based verification techniques in two aspects. On the one hand, we suggest using the formal model to assess the sanity of an interface verification unit. On the other hand, in order to generate clever semi-directed test cases from temporal logic properties, we propose a two-step approach. One step consists in generating system-level abstract test cases using model-based testing tools of the CADP toolbox. The other step consists in refining those tests into interface-level concrete test cases that can be executed at RTL level with a commercial Coverage-Directed Test Generation tool. We found that our approach helps in the transition between interface-level and system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench

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Li, Lun. „Integrated techniques for the formal verification and validation of digital systems“. Ann Arbor, Mich. : ProQuest, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3214772.

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Thesis (Ph.D. in Computer Engineering)--S.M.U.
Title from PDF title page (viewed July 10, 2007). Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2151. Adviser: Mitchell A. Thornton. Includes bibliographical references.

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Bücher zum Thema "Functional verification of digital systems"

Schuring, J. Design and experimental verification of a calculation method for frequency response analysis of digital control systems in a continuous environment. Amsterdam: National Aerospace Laboratory, 1985.

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Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2. Aufl. Boston: Kluwer Academic Publishers, 2001.

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Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2. Aufl. Boston: Kluwer Academic Publishers, 2001.

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1956-, Foster Harry, Hrsg. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. Norwell, Mass: Kluwer Academic Publishers, 2000.

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Inan, M. Kemal, und Robert P. Kurshan, Hrsg. Verification of Digital and Hybrid Systems. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/978-3-642-59615-5.

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Formal specification and verification of digital systems. London: McGraw-Hill, 1994.

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Gong, Lingkan, und Oliver Diessel. Functional Verification of Dynamically Reconfigurable FPGA-based Systems. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-06838-1.

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Rushby, John. Formal methods and their role in digital systems validation for airborne systems. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1995.

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Bronstein, Alexandre. String-functional semantics for formal verification of synchronous circuits. Stanford, Calif: Dept. of Computer Science, Stanford University, 1988.

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Kong, Jeong-Taek. Digital Timing Macromodeling for VLSI Design Verification. Boston, MA: Springer US, 1995.

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Buchteile zum Thema "Functional verification of digital systems"

Nishida, Yuki, Hiromasa Saito, Ran Chen, Akira Kawata, Jun Furuse, Kohei Suenaga und Atsushi Igarashi. „Helmholtz: A Verifier for Tezos Smart Contracts Based on Refinement Types“. In Tools and Algorithms for the Construction and Analysis of Systems, 262–80. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-72013-1_14.

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AbstractA smart contract is a program executed on a blockchain, based on which many cryptocurrencies are implemented, and is being used for automating transactions. Due to the large amount of money that smart contracts deal with, there is a surging demand for a method that can statically and formally verify them.This tool paper describes our type-based static verification tool Helmholtz for Michelson, which is a statically typed stack-based language for writing smart contracts that are executed on the blockchain platform Tezos. Helmholtz is designed on top of our extension of Michelson’s type system with refinement types. Helmholtz takes a Michelson program annotated with a user-defined specification written in the form of a refinement type as input; it then typechecks the program against the specification based on the refinement type system, discharging the generated verification conditions with the SMT solver Z3. We briefly introduce our refinement type system for the core calculus Mini-Michelson of Michelson, which incorporates the characteristic features such as compound datatypes (e.g., lists and pairs), higher-order functions, and invocation of another contract. Helmholtz successfully verifies several practical Michelson programs, including one that transfers money to an account and that checks a digital signature.

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Gong, Lingkan, und Oliver Diessel. „Verification Challenges“. In Functional Verification of Dynamically Reconfigurable FPGA-based Systems, 15–40. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-06838-1_2.

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McMillan, Kenneth. „Overview of Verification“. In Verification of Digital and Hybrid Systems, 3–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/978-3-642-59615-5_1.

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Janschek, Klaus, und Kristof Richmond. „Functional Realization: Digital Information Processing“. In Mechatronic Systems Design, 575–627. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17531-2_9.

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Majumdar, Rupak, und Majid Zamani. „Approximately Bisimilar Symbolic Models for Digital Control Systems“. In Computer Aided Verification, 362–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31424-7_28.

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Sato, Ryosuke, und Naoki Kobayashi. „Modular Verification of Higher-Order Functional Programs“. In Programming Languages and Systems, 831–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2017. http://dx.doi.org/10.1007/978-3-662-54434-1_31.

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Gong, Lingkan, und Oliver Diessel. „Getting Started with Verification“. In Functional Verification of Dynamically Reconfigurable FPGA-based Systems, 65–86. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-06838-1_4.

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Huang, Qingdan, Liqiang Pei, Yuqing Chen, Rui Rao und Huiyuan Lv. „Digital Multimeter Automatic Verification Device Design“. In Advances in Intelligent Systems and Computing, 295–301. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3308-2_33.

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McMillan, Kenneth L. „Compositional Systems and Methods“. In Verification of Digital and Hybrid Systems, 138–51. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/978-3-642-59615-5_7.

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Temme, Gerald, Michael Scholz und Mohamed Mahmod. „Digital Map and Environment Generation“. In Validation and Verification of Automated Systems, 75–87. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-14628-3_8.

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Konferenzberichte zum Thema "Functional verification of digital systems"

Cekan, Ondrej, Jakub Podivinsky und Zdenek Kotasek. „Software Fault Tolerance: The Evaluation by Functional Verification“. In 2015 Euromicro Conference on Digital System Design (DSD). IEEE, 2015. http://dx.doi.org/10.1109/dsd.2015.107.

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Thalaimalai Vanaraj, Anantharaj, Marshal Raj und Lakshminarayanan Gopalakrishnan. „Functional Verification closure using Optimal Test scenarios for Digital designs“. In 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT). IEEE, 2020. http://dx.doi.org/10.1109/icssit48917.2020.9214097.

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Shedeed, Mohamed, Ghada Bahig, M. Watheq Elkharashi und Michael Chen. „Functional design and verification of automotive embedded software: An integrated system verification flow“. In 2013 18th International Conference on Digital Signal Processing (DSP). IEEE, 2013. http://dx.doi.org/10.1109/siecpc.2013.6550793.

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Puhar, Primoz, und Andrej Zemva. „Functional Verification of a USB Host Controller“. In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.54.

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Rancea, I., und V. Sgarciu. „Functional verification of digital circuits using a software system“. In 2008 IEEE International Conference on Automation, Quality and Testing, Robotics. IEEE, 2008. http://dx.doi.org/10.1109/aqtr.2008.4588725.

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Serrestou, Youssef, und Vincent Beroulle Chantal Robach. „Functional Verification of RTL Designs driven by Mutation Testing metrics“. In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341472.

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Reza Kakoee, Mohammad, M. H. Neishaburi und Siamak Mohammadi. „Functional Test-Case Generation by a Control Transaction Graph for TLM Verification“. In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341464.

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Dastidar, T. R., und P. Ray. „A new device level digital simulator for simulation and functional verification of large semiconductor memories“. In 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06). IEEE, 2006. http://dx.doi.org/10.1109/vlsid.2006.19.

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Herencia-Zapana, Heber, James Lopez, Glen Gallagher, Baoluo Meng, Cameron Patterson und Lakshman Maalolan. „Formal Verification Tool Evaluation For Unmanned Aircraft Containing Complex Functions“. In 2020 IEEE/AIAA 39th Digital Avionics Systems Conference (DASC). IEEE, 2020. http://dx.doi.org/10.1109/dasc50938.2020.9256529.

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Chen, Ke, Leilei Xu und Zhende Zhou. „Co-Verification Method of NPP Protection System Based on FPGA Platform and SCADE Model“. In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-66606.

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In recent years, the FPGA-based digital technology is being introduced to replace CPU-based digital platform in the NPPs because of its high reliability, security and easy maintainability. Thus the verification and validation of FPGA-based I&C system has aroused a great attention. As most safety I&C systems are composed of four divisions, and perform 2-out-of-4 coincidence voting logic to actuate RT and ESFs. The 4 redundant portions are mostly the same. It is uneconomical and time-consuming to set up the full-size verification platform based on 4 redundant channels. In this paper, the co-verification method based on FPGA platform and SCADE model is proposed to efficiently verify the reactor protection logic. Based on the co-verification platform, it shows the proposed co-verification method is applicable for functional verification. The proposed co-verification method can be used for the preliminary assessment and functional verification of the FPGA-based I&C system and provide a semi-hardware platform for the development of the safety I&C system based on the FPGA platform, which will facilitate the evaluation of FPGA technology in the NPP and accelerate the V&V process.

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Berichte der Organisationen zum Thema "Functional verification of digital systems"

Hu, Yalin. Exploring formal verification methodology for FPGA-based digital systems. Office of Scientific and Technical Information (OSTI), September 2012. http://dx.doi.org/10.2172/1055616.

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Korsah, K., R. L. Clark und R. T. Wood. Functional issues and environmental qualification of digital protection systems of advanced light-water nuclear reactors. Office of Scientific and Technical Information (OSTI), April 1994. http://dx.doi.org/10.2172/10150860.

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