Dissertationen zum Thema „Electronics front-end“

The Center for Translational Neuroimaging of the Brookhaven National Laboratory has been studying the phenomenon of addiction, which has a direct impact on millions of people worldwide. This requires the development of new radiotracers for imaging specific neurotransmitter systems in the brain, and the design and implementation of novel imaging devices to measure the neuroactivity of the brain. The RatCAP, or Rat Conscious Animal Positron Emission Tomography (PET), is a head-mounted miniature PET scanner for brain metabolism imaging of awake rats with minimal mobility restriction to enable correlation with the animal's behavior. The RatCAP detector is based on LSO scintillator crystals and avalanche photodiode (APD) arrays. The design of the RatCAP imposed stringent requirements on the readout electronics. First, due to its size and limited power budget, VLSI of the front-end electronics was mandatory. Second, due to the weak signal to noise ratio from the APD detectors, the analog front-end noise had to be minimized, within the power budget, to provide the best possible timing resolution. Finally, the number of interconnections with the data acquisition system had to be minimal in order to maximize the animal's mobility. This thesis presents the design and implementation of the ASIC for the RatCAP. The final ASIC integrates 32 channels consisting of a charge sensitive preamplifier, programmable gain, a bipolar shaping amplifier, and timing and energy discriminators. A novel 32-to-1 address and timing serial encoder is integrated on-chip to multiplex the acquired data through a single output. The ASIC was realized in 0.18 [mu]m CMOS technology from TSMC, has a size of 3.3 mm × 4.5 mm, and power consumption of 117 mW. The ASIC is fully operational. Noise characterization led to a measured equivalent noise charge of 650 electrons rms with the APD biased at the input. A coincidence timing resolution of 6.7 ns FWHM was measured between two typical LSO-APD-ASIC modules using a 68 Ge source (threshold at 420 keV). An energy resolution of 18.7% FWHM at 511 keV was measured for a 68 Ge source. The ASIC and the technology developed for the RatCAP have opened the door to the realization of many other systems, such as a PET-MRI scanner, and led to the granting of three patents and the publication of numerous scientific presentations.

El Laboratori d'Altes Energies de La Salle és un membre d'un grup acreditat per la Generalitat. Aquest grup està format per part del Departament d'Estructura i Constituents de la Matèria de la Facultat de Física de la Universitat de Barcelona, part del departament d'Electrònica de la mateixa Facultat i pel grup de La Salle. Tots ells estan involucrats en el disseny d'un subdetector en l'experiment de LHCb del CERN: el SPD (Scintillator Pad Detector).

El SPD és part del Calorímetre de LHCb. Aquest sistema proporciona possibles hadrons d'alta energia, electrons i fotons pel primer nivell de trigger. El SPD està format per una làmina centellejeadora de plàstic, dividida en 600 cel.les de diferent tamany per obtenir una millor granularitat aprop del feix. Les partícules carregades que travessin el centellejador generaran una ionització del mateix, a diferència dels fotons que no la ionitzaran. Aquesta ionització, generarà un pols de llum que serà recollit per una WLS que està enrotllada dins de les cel.les centellejadores. La llum serà transmesa al sistema de lectura mitjançant fibres clares. Per reducció de costos, aquestes 6000 cel.les estan dividides en grups, usant MAPMT (fotomultiplicadors multiànode) de 64 canals per rebre la informació en el sistema de lectura. El senyal de sortida dels fotomultilplicadors és irregular degut al baix nivell de fotoestadística, uns 20-30 fotoelectrons per MIP, i degut també a la resposta de la fibra WLS, que té un temps de baixada lent. Degut a tot això, el processat del senyal, es realitza primer durant la integració de la càrrega total i finalment per la correcció de la cua que conté el senyal provinent del PMT.

Aquesta Tesi està enfocada en el sistema de lectura de l'electrònica del VFE del SPD. Aquest, està format per un ASIC (dissenyat pel grup de la UB) encarregat d'integrar el senyal, compensar el senyal restant i comparar el nivell d'energia obtingut amb un llindar programable (fa la distinció entre electrons i fotons), una FPGA que programa aquests llindars i compensacions de cada ASIC i fa el mapeig de cada canal rebut en el detector i finalment usa serialitzadors LVDS per enviar la informació de sortida al trigger de primer nivell. En el disseny d'aquest tipus d'electrònica s'haurà de tenir en compte, per un costat, restriccions de tipus mecànic: l'espai disponible per l'electrònica és limitat i escàs, i per un altre costat, el nivell de radiació que deurà suportar és considerable i s'haurà de comprobar que tots els components superin un cert test de radiació, i finalment, també s'haurà de tenir en compte la distància que separa els VFE dels racks on la informació és enviada i el tipus de senyal amb el que es treballa en aquest tipus d'experiments: mixta i de poc rang.
El Laboratorio de Altas Energías de la Salle es un miembro de un grupo acreditado por La Generalitat. Este grupo está formado por parte del departamento de Estructura i Constituents de la Matèria de la Facultad de Física de la Universidad de Barcelona, parte del departamento de Electrónica de la misma Facultad y el grupo de La Salle. Todos ellos están involucrados en el diseño de un subdetector en el experimento de LHCb del CERN: El SPD (Scintillator Pad Detector).
El SPD es parte del Calorímetro de LHCb. Este sistema proporciona posibles hadrones de alta energía, electrones y fotones para el primer nivel de trigger.El SPD está diseñado para distinguir entre electrones y fotones para el trigger de primer nivel. Este detector está formado por una lámina centelleadora de plástico, dividida en 6000 celdas de diferente tamaño para obtener una mejor granularidad cerca del haz. Las partículas cargadas que atraviesen el centelleador generarán una ionización del mismo, a diferencia de los fotones que no la generarán. Esta ionización generará, a su vez, un pulso de luz que será recogido por una WLS que está enrollada dentro de las celdas centelleadoras. La luz será transmitida al sistema de lectura mediante fibras claras. Para reducción de costes, estas 6000 celdas están divididas en grupos, utilizando un MAPMT (fotomultiplicadores multiánodo) de 64 canales para recibir la información en el sistema de lectura. La señal de salida de los fotomultiplicadores es irregular debido al bajo nivel de fotoestadística, unos 20-30 fotoelectrones por MIP, y debido también a la respuesta de la fibra WLS, que tiene un tiempo de bajada lento. Debido a todo esto, el procesado de la señal, se realiza primero mediante la integración de la carga total y finalmente por la substracción de la señal restante fuera del período de integración.
Esta Tesis está enfocada en el sistema de lectura de la electrónica del VFE del SPD. Éste, está formado por un ASIC (diseñado por el grupo de la UB) encargado de integrar la señal, compensar la señal restante y comparar el nivel de energía obtenido con un umbral programable (que distingue entre electrones y fotones), y una FPGA que programa estos umbrales y compensaciones de cada ASIC, y mapea cada uno de los canales recibidos en el detector y finalmente usa serializadores LVDS para enviar la información de salida al trigger de primer nivel. En el diseño de este tipo de electrónica se deberá tener en cuenta, por un lado, restricciones del tipo mecánico: el espacio disponible para la electrónica en sí, es limitado y escaso, por otro lado, el nivel de radiación que deberá soportar es considerable y se tendrá que comprobar que todos los componentes usado superen un cierto test de radiación, y finalmente, también se deberá tener en cuenta la distancia que separa los VFE de los racks dónde la información es enviada y el tipo de señal con el que se trabaja en este tipo de experimentos: mixta y de poco rango.
Laboratory in La Salle is a member of a Credited Research Group by La Generatitat. This group is formed by a part of the ECM department, a part of the Electronics department at UB (University of Barcelona) and La Salle's group. Together, they are involved in the design of a subdetector at LHCb Experiment at CERN: the SPD (Scintillator Pad Detector).
The SPD is a part of LHCb Calorimeter. That system provides high energy hadrons, electron and photons candidates for the first level trigger.
The SPD is designed to distinguish electrons and photons for this first level trigger. This detector is a plastic scintillator layer, divided in about 6000 cells of different size to obtain better granularity near the beam. Charged particles will produce, and photons will not, ionisation on the scintillator. This ionisation generates a light pulse that is collected by a Wavelength Shifting (WLS) fibre that is twisted inside the scintillator cell. The light is transmitted through a clear fibre to the readout system.
For cost reduction, these 6000 cells are divided in groups using a MAPMT of 64 channels for receiving information in the readout system. The signal outing the SPD PMTs is rather unpredictable as a result of the low number of photostatistics, 20-30 photoelectrons per MIP, and the due to the response of the WLS fibre, which has low decay time. Then, the signal processing must be performed by first integrating the total charge and later subtracting to avoid pile-up.
This PhD is focused on the VFE (Very Front End) of SPD Readout system. It is performed by a specific ASIC (designed by the UB group) which integrates the signal, makes the pile-up compensation, and compares the level obtained to a programmable threshold (distinguishing electrons and photons), an FPGA which programs the ASIC thresholds, pile-up subtraction and mapping the channels in the detector and finally LVDS serializers, in order to send information to the first level trigger system.
Not only mechanical constraints had to be taken into account in the design of the card as a result of the little space for the readout electronics but also, on one hand, the radiation quote expected in the environment and on the other hand, the distance between the VFE electronics and the racks were information is sent and the signal range that this kind of experiments usually have.

In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.

ce rapport résume les développements réalisés en électronique pour lire le calorimètre à Argon Liquide (LAr) d'ATLAS au LHC puis le R&D effectué dans CALICE pour lire ceux de l'ILC en passant par les circuits développés pour lire les photomultiplicateurs multi-anode (MaPMT) pour OPERA ou pour la luminosité d'ATLAS et qui ont aussi des applications en imagerie médicale. Commencée au début des années 90, le R&D pour la calorimétrie d'ATLAS était extrêmement challenging en termes de vitesse de lecture, tenue aux radiations et précision de mesure. La vitesse élevée a nécessité une nouvelle approche de préamplificateurs de courant plutôt que de charge et la définition du bruit en ENI. Les préamplificateurs ont été développés a Orsay ainsi que les shapers monolithiques, ils sont détaillés dans le chapitre 1 ainsi que les considérations sur le filtrage numérique, qui constituait une nouveauté pour la communauté et qui ne donnait pas les résultas escomptés au début. Le chapitre 2 est consacré au système de calibration, développé et produit par Orsay et dont la performance poussée a nécessité des études approfondies. Le chapitre 3 clôt les études pour ATLAS avec un résumé des mesures qui ont dû être faites sur les 200 000 voies du détecteur pour le comprendre et le modéliser afin d'atteindre partout la précision et l'uniformité meilleures que le pourcent. Ces travaux pour ATLAS se sont achevés en 2004, même si des développements ont été réalisés pour les calorimètres de NA48 et D0 durant cette même période et sur des sujets connexes qui ne sont pas détaillés ici. La prochaine génération de collisionneurs après le LHC nécessitera une nouvelle génération de calorimètres, beaucoup plus granulaires (on parle d' « imaging calorimetry », avec des centaines de millions de canaux) et d'électronique de lecture intégrée dans le détecteur. Les ASICs développés pour cette application dans le cadre de la collaboration « CALICE » sont décrits au chapitre 4. Ils intègrent toutes les fonctions d'amplification, digitisation et lecture intégrée qui ont font de véritables « Systems On Chip » (SoC). Une famille de 3 circuits permet de lire le calorimètre électromagnétique Silicium-Tungstène, les RPCs du calorimètre hadronique digital ou les SiPM du calorimètre hadronique analogique ; très performants et versatiles, ils trouvent de nombreuses applications extérieures Ces circuits ont repris de précédents blocs de chips mis au point dans les années 2000 pour lire les photomultiplicateurs multi-anodes du Target Tracker de l'expérience OPERA puis du luminomètre de l'expérience ATLAS et qui sont décrits au chapitre 5 Ces circuits trouvent une continuation actuelle dans les photodétecteurs intégrés de grandes dimensions, développés pour de futures expériences Neutrino.

Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET). En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente cargadas que atraviesan su volumen gaseoso. La tesis incluye un estudio de los objetivos para futuros detectores, resumiendo los parámetros que un sistema de adquisición de datos debe cumplir en esos casos. Además, estos requisitos son comparados con los actuales sistemas de lectura utilizados en diferentes detectores TPC. Se concluye que ninguno de los sistemas cumple las restrictivas condiciones. Algunos de los principales objetivos para futuros detectores TPC son un altísimo nivel de integración, incremento del número de canales, electrónica más rápida y muy baja potencia. El principal inconveniente del estado del arte de los sistemas anteriores es la utilización de varios circuitos integrados en la cadena de adquisición. Este hecho hace imposible alcanzar el altísimo nivel de integración requerido para futuros detectores. Además, un aumento del número de canales y frecuencia de muestreo haría incrementar hasta valores no permitidos la potencia utilizada. Y en consecuencia, incrementar la refrigeración necesaria (en caso de ser posible). Una de las novedades presentadas es la integración de toda la cadena de adquisición (filtros analógicos de entrada, conversor analógico-digital (ADC) y procesado de señal digital) en un único circuito integrado en tecnología de 130nm. Este chip es el primero que realiza esta altísima integración para detectores TPC. Por otro lado, se presenta un análisis detallado de los filtros de procesado de señal. Los objetivos más importantes es la reducció
García García, EJ. (2012). Novel Front-end Electronics for Time Projection Chamber Detectors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16980
Palancia

With the advantages of low cost, low power consumption, high reliability and potential for large scale integration, CMOS monolithically integrated active pixel chips have significant application in optical sensing systems. The optical front end presented in this thesis will have application in Optical Scanning Acoustic Microscope System (O-SAM), which involves a totally non-contact method of acquiring images of the interaction between surface acoustic waves (SAWs) and a solid material to be characterized. In this work, an ultra fast optical front-end using improved regulated cascade scheme is developed based on AMS 0.35mm CMOS technology. The receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p+ junctions as the active region, the integrated photodiode operates up to 4.9 GHz with no process modification. Its responsivity was measured to be 0.016 A/W. With multi-inductive-series peaking technique, the improved ReGulated-Cascade (RGC) transimpedance amplifier achieves an experimentally measured -3dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dBW, which is the fastest reported TIA in CMOS 0.35mm technology. The 5 GHz Gilbert cell mixer produces a conversion gain of 11 dB, which greatly minimized the noise contribution from the IF stage. The noise figure and input IIP3 of the mixer were measured to be 15.7 dB and 1.5 dBm, respectively. The IF amplifier and output buffer pick up and further amplify the signal for post processing. The optical front end demonstrates a typical equivalent input noise current of 35 pA=pHz at 5 GHz, and a total transimpedance gain of 83 dB ohm whileconsuming a total current of 40 mA from 3.3 V power supply. The -3 dB bandwidth for the optical front end was measured to be 4.9 GHz. All the prototype chips, including the optical front end, and the individual circuits including the photodiode, TIA, mixer were probe-tested and all the measurements were taken with Anritsu VNA 37397D and Anritsu spectrum analyser MS2721A.

Le travail de thèse porte sur l'étude de l'électronique front-end pour le télescope WFCTA (Wide Field of View Cherenkov Telescope Array,) qui est l'un des détecteurs de l’observatoire LHAASO (Large High Altitude Air shower Observatory,). Le manuscrit de thèse couvre six thèmes principaux allant de la simulation physique au développement d’un nouveau système d'acquisition de données.Tout d'abord, les principes de la physique des rayons cosmiques et de l'expérience LHAASO sont présentés donnant ainsi une introduction sur les sujets discutés dans la thèse. Des simulations ont été faites dans le but de comprendre la propagation des rayons cosmiques dans l'atmosphère et d’en déduire les caractéristiques du signal d'entrée de l'électronique. Ces simulations ont également été utilisées pour approfondir la compréhension des spécifications du télescope et de les vérifier.Un nouveau modèle de PMT a été élaboré pour être utilisé dans les simulations. Ce nouveau modèle est comparé aux autres modèles de PMT. Des modèles d’électronique pour les conceptions basées sur les composants électroniques classiques et sur l’ASIC (Application-specific Integrated Circuit) sont construites et étudiées. Ces deux solutions remplissent les spécifications du télescope WFCTA. Néanmoins, compte tenu du développement de la micro-électronique, il est proposé que l’électronique des télescopes de haute performance devrait être basée sur l’ASIC.L'ASIC sélectionné, PARISROC 2, est évalué en utilisant des bancs de tests existants. Les résultats montrent que ces bancs de tests ne peuvent pas démontrer pleinement la véritable performance de l’ASIC. Par conséquent, une carte électronique front-end prototype qui est basée sur ASIC a été conçu et fabriqué. Plusieurs modifications ont été apportées pour améliorer la performance de la nouvelle carte. Une description détaillée de ce développement est présentée dans la thèse. Un nouveau système d’acquisition de données a également été conçu pour améliorer la capacité de lecture de données dans le banc de tests de la carte front-end.Enfin, une série de tests ont été effectués pour vérifier le concept de design et pour évaluer la performance de la carte front-end. Ces résultats montrent la bonne performance générale de l'ASIC PARISROC 2 et que la carte front-end répond globalement aux spécifications de la WFCTA. Basé sur les résultats de ce travail de thèse, un nouveau ASIC, mieux adapté pour les télescopes de type WFCTA, a été conçu et est actuellement en cours de fabrication
This thesis is focused on the study of the front-end electronics for the wide field of view Cherenkov telescope array (WFCTA), which is one of the large high altitude air shower observatory (LHAASO) detectors. The thesis manuscript covers six main topics going from the physics simulations to the implementation of a new data acquisition system. The physics of cosmic rays and the LHAASO experiment is presented giving foundation for discussion of the main topics of the thesis. Simulations were performed to understand the propagation of cosmic rays in the atmosphere and to determine the characteristics of the input signal of the electronics. These simulations allow also understand the specifications of the telescope and to verify them. A new PMT model was successfully built for both physical and electronic simulations. This new model is compared to other models and its performance is evaluated. Behavior models for the designs based on the classical electronics and application-specific integrated circuit (ASIC) were built and studied. It is shown that both solutions fit the requirements of the telescope. However, considering the development of the micro-electronics, it is proposed that the electronics of the high-performance telescopes should be based on ASIC. The selected ASIC, PARISROC 2, is evaluated by using the existing application boards. The results showed that the designs considered could not fully demonstrate the real performance of the chip. Therefore, a prototype front-end electronics board, based on PARISROC 2, was designed, implemented and fabricated. Several modifications and enhancements were made to improve the performance of the new design. A detailed description of the development is presented and discussed in the manuscript. Furthermore, a new data acquisition system was developed to enhance the readout capabilities in the front-end test bench.Finally, a series of tests were performed to verify the concept of the design and to evaluate the front-end board. The results show the good general performance of the PARISROC 2 and that this design globally meets the specifications of the WFCTA. Based on the results of this thesis work, a new ASIC chip, better adapted for telescopes such as WFCTA, has been designed and is currently being fabricated

In this master degree work, a digital attenuator and a low noise amplifier (LNA) have been designed and integrated with the RF front-end receiver for IEEE 802.11b Wireless LAN standard. Firstly, the 4-bit digitally controlled attenuator has been designed with theattenuation range of 50 to 80 dB and reflection coefficient less than -25 dB. Next, the single stage wide band low noise amplifier with voltage gain larger than 14 dB and noise figure below 4 dB has been designed to operate at frequency 2.4 GHz. Finally, the integration with a down-conversion mixer has been done and evaluated its performance.

The attenuator and low noise amplifier desired in this thesis have been implemented using standard CMOS 0.35µm technology and validated by the simulation tools Cadence Spectre-RF.

Thesis (M.S. of electrical engineering)--Washington State University, December 2009.
Title from PDF title page (viewed on Jan. 14, 2010). "Department of Electrical Engineering and Computer Science." Includes bibliographical references (p. 62-63).

A highly segmented silicon tracking detector has been constructed at the University of Liverpool that will form an integral part of the future R3B (Reactions with Relativistic Radioactive Beams) experimental setup at FAIR (Facility for Antiproton and Ion Research). The requirements and design of the tracking detector are explained as well as the tracker's functionality in relation to the other R3B detectors. The tracking detector will provide high resolution position measurements and vertex capabilities that will significantly enhance the wide ranging physics programme that is anticipated for R3B. Individual detectors have been constructed by combining several silicon sensors with a double-sided stereoangle strip geometry. All sensors have a strip pitch of 50 μm to ensure high granularity. The tracker is formed of two types of detector which have a total of 4096 or 3072 independent strips. All silicon sensors used for detector construction have been subjected to a quality assurance process at the University of Liverpool. The different stages of the quality assurance process are described and the results for all accepted sensors are presented. The process by which detectors are produced is outlined and the final test data for each completed detector is presented. The detector readout relies on an Application Specific Integrated Circuit (ASIC), which has been designed, at Rutherford Appleton Laboratory, specifically for the silicon tracker. A detailed description of the R3B ASIC architecture is given and ideal operational amplifier calculations have been performed for the different pulse processing stages. A bare ASIC test setup has been assembled at STFC Daresbury, to develop an understanding of the performance of the pre-production ASIC (version two). An analysis of the results has identified issues which have been corrected for the final production ASIC (version three). The results of pre-production ASIC testing have been compared with the specifications and a discussion of the measurements of several key performance criteria is presented, along with theoretical calculations for comparison and verification.

The next generation High Energy Physics experiments require the development of novel radiation sensor technologies adequate to cover very large areas and suitable for extreme radiation conditions. In this field, thanks to its incomparable properties, silicon is still nowadays the dominant semiconductor used to build tracking detectors for ionizing particles. In several experiments all around the world, it is used to cover very large areas with the intent of tracking and identifying the crossing particles generated during the experiments. Different topologies of silicon sensors can be used for these applications but those commonly used for high rate environments are pixel sensors. This research activity focuses mainly on two particular types of these sensors: hybrid pixel sensors and monolithic active pixel sensors (MAPS). Modern detectors use intensively hybrid sensors due to their excellent properties. This technology indeed allows to develop sensor and electronics separately allowing a very effective optimization of each part of the device increasing in this way its versatility and allowing to meet most of the requirements of the new experiments. The hybrid technology is fast and also suitable for working in high radiation environments thanks to the use of high electrical fields for the charge collection. However, the production cost of those devices is much higher than other sensors because two different devices are required and also due to the additional cost for the bump bonding used to interconnect sensor and readout ASIC. On the other hand, monolithic sensors are based on the implementation of sensor and readout electronics in the same silicon wafer. Therefore this technology is much cheaper than the hybrid solution and allows to reduce significantly contribution of the detector to the material budget. However, traditional MAPS have some limitations in terms of speed, extension of the depletion volume, signal to noise ratio and radiation tolerance which make those devices unsuitable for the extreme environment of the new experiments. In this context, this work presents the development of a full depleted monolithic pixel sensor with a thickness of 300 μm which aims to overcome the main limitations of the conventional monolithics. The proposed device has properties similar to the hybrid solution but benefits of the low production cost typical of monolithics. The development of the device has been carried out by the collaboration between the University of Trento, INFN of Padova and INFN of Torino. In addition, thanks to the close collaboration with the experts of a silicon foundry, it was possible a tailored fabrication of the devices. Two ASICs of 2 mm × 2 mm have been developed in a customized double-sided CMOS technology with transistors of 1.2 V and 6 metal layers. The devices have been submitted to the foundry for fabrication on April 2016 and have been delivered for the testing phase on May 2017. A patent for the device has been granted in 2017. In the first part of this work, the state of the art of monolithics is given where hybrid and monolithics are compared. Then, the novel sensor is described in detail with the support of simulations to motivate important solutions adopted to reach the full depletion and to implement PMOS transistors avoiding the competitive charge collection. Some studies to highlight the huge limitations on design MAPS without access to the process data are presented to introduce the custom process used for the development of the device. The first ASIC is a test chip designed to contain test devices used to study important properties of the sensor like depletion and punch-through voltage. All the devices implemented in this ASIC are described in detail motivating the design solutions adopted. The second ASIC is the complete monolithic sensor called MATISSE (Monolithic AcTIve pixel SenSor Electronics) made by a matrix array of 24 × 24 pixels readout with the snapshot shutter technique. Each pixel is 50 μm×50 μm and is based on the same novel sensor. The chip is described in detail with the support of simulation results to motivate some strategies adopted during the design. Special emphasis is placed on the strategy used to design the readout chain with a wide output swing, low noise and excellent linearity with the use of high threshold transistors. Last but not least, in the last chapter the results collected during the characterization of the two prototypes for different wafers are presented. The data acquisition system developed is described and the electrical tests and measurements with active sources and lasers are reported. The measurements performed on the test structures show unwanted trapped charge in the backside oxide. The phenomenon is described putting special attention on an irradiation campaign performed in the test diodes to confirm and quantify this effect. All the results presented in this work aim to prove the device full depletion and the excellent properties of the embedded electronics implemented in these first prototypes.

A study has been made in CMOS RF-switches that can be used in the front-end of a multi-band radio targeting the 802.11a,b,g and W-CDMA standards and working in the frequency range 2.4-5.5GHz. Especially, one single-transistor switch and two types of transmission gates have been analyzed, simulated and compared with respect to loss, linearity, compression point and noise. From this, five different single-transistor switches have been designed for on-chip probing measurements. Special consideration has been taken to accommodate on-chip testing, thus additional structures have been designed. The simulations and design has been performed with Chartered 0.18um RF-CMOS process.

The results from the simulations show that the single-transistor switch has better performance in loss, linearity, compression point and noise compared to the transmission gates. However, for the transmission gates the linearity can be increased beyond the linearity of the single-transistor switch if the widths of the transistors are made sufficiently large.

For the single-transistor switch, simulation results show that the transistor length shall be kept to its minimum for best performance and that the number of fingers does not influence significantly. Also, there are optimum values for the loss in on-mode, the noise and the linearity and worst-case values for the loss in off-mode when the transistor width is varied. Consequently, the single- transistor switch can be tuned by its transistor width to accommodate desired performances.

The overall goal of this diploma work is to produce a design of a 5 GHz radio frontend using Agilent Advanced Design System (ADS) and then build a working prototype. Using this prototype to determine if RF circuits at 5 GHz can be successfully produced using distributed components on a laminate substrate.

The design process for the radio front-end consists of two stages. In the first stage the distributed components are designed and simulated, and in the second stage all components are merged into a PCB. This PCB is then manufactured and assembled. All measurements on the radio front-end and the test components are made using a network analyser, in order to measure the S-parameters.

This diploma work has resulted in a functional design and prototype, which has proved that designing systems for 5 GHz on a laminate substrate is possible but by no means trivial.

Thesis (M.S. in Electrincal Engineering)--Naval Postgraduate School, September 2008.
Thesis Advisor(s): Pace, Phillip E. "September 2008." Description based on title screen as viewed on November 4, 2008. Includes bibliographical references (p. 65-66). Also available in print.

In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology.

Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end.

The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated.

The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.

The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

This thesis describes the design, realization and testing of an integrated millimeter wave receiver front-end in E-plane configuration. In particular, the combination and integration of a balanced mixer, two filters, and a local oscillator stabilized by a dielectric restorator are described. The following is a brief description of those three major components that constitute the receiver front-end. The heart of the mixer is a classical 180 degrees hybrid junction formed by the juxtaposition of unilateral fin-line and coplanar waveguide. Matching of the RF signal to the diodes is critical for good conversion loss. The receiver contains two filters. In order to ensure compatability with the mixer, the 24 GHz local oscillator was realized in such a way that the FET was also situated in the E-plane. The components have been realized on 10 mils thick RT-Duroid 5880 (dielectric constant $\in\sb{\rm r}$ = 2.22) suspended in the E-plane of a WR-42 waveguide. The receiver incorporates a 24.0 GHz oscillator (LO) and accepts an input radio frequency signal (RF) at 24.4 GHz with a bandwidth of 500 MHz. (Abstract shortened by UMI.)

Electronics are normally designed to operate at temperatures less than 125 oC. For high temperature applications, the use of those normal electronics becomes challenging and sometimes impractical. Conventionally, many industries tried to push the maximum operating temperature of electronics by either using passive/active cooling systems or tolerating degraded performance. Recently, there has been a demand for more robust electronics that can operate at higher temperature without sacrificing the performance or the use of any weighty, power hungry, complex cooling systems. One of the major industries that need electronics operating at high temperature is the oil and gas industry. Electronics have been used within the field in many areas, such as well logging downhole telemetry systems, power networks, sensors, and actuators. In the past, the industry has managed to use the existing electronics at temperatures up to 150 oC. However, declining reserves of easily accessible natural resources have motivated the oil and gas industry to drill deeper. The main challenge at deep wells for downhole electronics is the high temperatures as the pressures are handled mechanically. The temperature in deep basins can exceed 210 oC. In addition, existing well logging telemetry systems achieve low data transmission rates of less than 2.0 Mbps at depth of 7.0 Km which do not meet the growing demand for higher data rates due to higher resolution sensors, faster logging speeds, and additional tools available for a single wireline cable. The main issues limiting the speed of the systems are the bandwidth of multi-conductor copper cable and the low speed communication system connecting the tools with the telemetry modem. The next generation of the well logging telemetry system replaces the multi-conductor wireline between the surface and the downhole with an optical fiber cable and uses a coaxial cable to connect tools with the optical node in downhole to meet the growing needs for higher data rates. However, the downhole communication system between the tools and the optical modulator remains the bottleneck for the system. The downhole system is required to provide full duplex and simultaneous communications between multiple downhole tools and the surface with high data rates and able to operate reliably at temperatures up to 230 oC. In this dissertation, a downhole communication system based on radio frequency (RF) transmission is investigated. The major contributions of our research lie in five areas. First, we proposed and designed a downhole communication system that employs RF systems to provide high speed communications between the downhole tools and the surface. The system supports up to six tools and utilizes frequency division multiple access to provide full duplex and simultaneous communications between downhole tools and the surface data acquisition system. The system achieves 20 Mbps per tool for uplink and 6 Mbps per tool for downlink with bit error rate (BER) less than 10-6. Second, a RF front-end of transceiver operating at ambient temperatures up to 230 oC is designed and prototyped using Gallium Nitride (GaN) high electron mobility transistor (HEMT) devices. Measurement results of the transceiver's front end are reported in this dissertation. To our knowledge, this is the first RF transceiver that operates at this high temperature. Third, current-voltage and S-parameters characterizations of the GaN HEMT at ambient temperatures of 250 oC are conducted. An analytic model that accurately predicts the behavior of the drain-source resistor (RDS) of the GaN transistor at temperature up to 250 oC is developed based on these characterizations. The model is verified by the analysis and the performance of the resistive mixer. Fourth, a passive upconversion mixer operating at temperatures of 250 oC is designed and prototyped. The designed mixer has conversion loss (CL) of 6.5 dB at 25 oC under local oscillator (LO) power of 2.5 dBm and less than 0.75 dB CL variation at 250 oC under the optimum biasing condition. Fifth, an active downconversion mixer operating at temperatures up to 250 oC is designed and prototyped. The proposed mixer adopts a common source topology for a reliable thermal connection to the transistor source plate. The designed active mixer has conversion gain (CG) of 12 dB at 25 oC under LO power of 2.5 dBm and less than 3.0 dB CG variation at 250 oC. Finally, a novel high temperature negative adaptive bias voltage circuit for a GaN based RF block is proposed. The proposed design comprises an oscillator, voltage doubler, and temperature dependent bias controller. The voltage offset and temperature coefficient of the generated bias voltage can be adjusted by the bias controller to match the optimum biasing voltage required by a RF building block. The bias controller is designed using a Silicon Carbide (SiC) bipolar junction transistor.
PHD

Thermal management is a rapidly growing field in power electronics today. As power supply systems are designed with higher power density levels, keeping component temperatures within suitable ranges of their maximum operating limits becomes an increasingly challenging task. This project focuses on thermal management at the system level, using a 1.2 kW front-end power converter as a subject for case study. The establishment of a methodology for using the computer code I-deas to computationally simulate the thermal performance of component temperatures within the system was the primary goal. A series of four benchmarking studies was used to verify the computational predictions. The first test compares predictions of a real system with thermocouple measurements, and the second compares computational predictions with infrared camera and thermocouple measurements on a component mounted to a heat sink. The third experiment involves using flow visualization to verify the presence of vortices in the flow field, and the fourth is a comparison of computational temperature predictions of a DC heater in a controlled flow environment. A radiation study using the Monte Carlo ray-trace method for radiation heat transfer resulted in the reduction of some component temperature predictions of significant components. This radiation study focused on an aspect of heat transfer that is often ignored in power electronics. A component rearrangement study was performed to establish a set of guidelines for component placement in future electronic systems. This was done through the use of a test matrix in which the converter layout was varied a number of different ways in order to help determine thermal effects. Based on the options explored and the electrical constraints on the circuit, an optimum circuit layout was suggested for maximum thermal performance. This project provides a foundation for the thermal management of power electronics at the system level. The use of I-deas as a computational modeling tool was explored, and comparison of the code with experimental measurements helped to explore the accuracy of I-deas as a system level thermal modeling tool.
Master of Science

Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.

A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.

The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology. As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.

The NEXT experiment is one of the most innovative ones looking for the neutrinoless double beta decay, which finding will answer one of the most important questions in the last years physics: is the neutrino its own antiparticle? Or in other words, is it a Majorana particle? With that purpose NEXT uses a TPC (Time Projection Chamber) filled with enriched xenon gas at high pressure, and two photosensors planes, one on each end. The first plane contains PMTs (PhotoMultiplier Tube), that collect the light emitted by the xenon when an event happens and precisely measures its energy. The second plane is a SiPM (Silicon PhotoMultiplier) matrix that allows to 3D-reconstruct the event track. Both planes together allows NEXT to have a great background rejection, which makes a difference with the other experiments aiming for the neutrinoless double beta decay. In addition, SiPMs are a new technology which nowadays is evolving to, in the future, displace the classical PMTs. For that reason the study of these sensors starts from zero, as there were not previous uses as pixel-tracking, and lead a new path in the physics detectors, for both high and low energy. This thesis is focused on the study and design of the electronics involving the tracking plane, which includes some technical solutions related also with mechanical issues. From the sensors placed inside the detector, the SiPMs, to the front-end electronic boards, there are few elements on the chain; as the support boards for the SiPMs which must satisfy severe outgassing and radiopurity levels. Also the inner and outer cabling has been designed, focusing on obtaining the best signal-noise ratio; and also the feedthrough for the tracking plane, which solved at low cost the huge problem of taking out about 4000 lines from the pressurized xenon to the outside. Finally, one of the most important elements on this chain and the one that this thesis is focused on, is the front-end board. Starting with the experience acquired with the first prototype, NEXT-DEMO, the electronics have been improved, able to condition, integrate and digitize the signals from all the tracking plane SiPMs; allowing the further acquisition and processing through an ATCA-based system (Advanced Telecommunications Computing Architecture). All the elements designed have been produced and assembled on the NEW detector, a large-scale prototype of the final detector, placed at the Laboratorio Subterra'neo de Canfranc, an underground laboratory at the aragonese Pyrenee.
El experimento NEXT es uno de los más innovadores en la búsqueda de la desintegración doble beta sin neutrinos, cuyo hallazgo daría con la respuesta a una de las cuestiones más importantes de la física en los últimos años: ¿es el neutrino su propia antipartícula? O dicho de otro modo, ¿es una partícula de Majorana? Para ello NEXT hace uso de una TPC (Time Projection Chamber) llena de gas xenón enriquecido a alta presión, y con dos planos de fotosensores, uno en cada extremo. El primero de ellos está formado por PMTs (Photo Multiplier Tube), que recogen la luz generada por el xenón cuando ocurre un evento, y miden la energía de éste. El segundo consiste en una matriz de SiPMs (Silicon PhotoMultipliers) que permiten reconstruir tridimensionalmente la traza de dicho evento. El conjunto de ambos planos de fotosensores otorga al experimento NEXT un gran rechazo a eventos de fondo, lo que marca la diferencia con otros experimentos en busca de la desintegración doble beta sin neutrinos. Además, los SiPMs son una tecnoloía de reciente aparición que en la actualidad está evolucionando a grandes pasos para, en un futuro, desplazar a los fotomultiplicadores clásicos. Por ello el estudio de estos fotosensores parte prácticamente desde cero, ya que no existen aplicaciones previas de su uso como pixel-tracking, y ha permitido abrir un nuevo camino en los detectores de física, tanto de alta como baja energía. Esta tesis doctoral tiene como objetivo el estudio y diseño de la electrónica involucrada en el plano de reconstrucción de trazas, y que involucran en menor medida dar solución a problemas técnicos de aspecto mecánico. Partiendo de los sensores ubicados dentro del detector, los SiPMs, hasta las tarjetas de front-end, se incluyen varios elementos de la cadena; como son las tarjetas empleadas como soporte para los SiPM en el interior de la cámara, las cuáles deben cumplir rigurosas medidas de radiopureza y degasificación. También se ha diseñado el cableado tanto interno como externo, haciendo énfasis en conseguir la mayor relación posible señal-ruido; y el pasamuros específico para el plano de reconstrucción de trazas, el cual ha resuelto a bajo coste el problema de extraer casi 4000 líneas desde la zona de xenón a alta presión hasta el exterior. Por último, uno de los elementos más importantes de esta cadena y en el cuál se centra principalmente esta tesis, es la tarjeta de front-end. Partiendo de la experiencia adquirida del primer prototipo del experimento, NEXT-DEMO, se ha perfeccionado una electrónica capaz de tratar, integrar y adquirir las señales de todos los SiPM del plano de reconstrucción de trazas, permitiendo su posterior adquisición y procesado mediante un sistema basado en la estructura ATCA (Advanced Telecommunications Computing Architecture). Todos los elementos diseñados han sido ensamblados y puestos en marcha en el detector NEW, un prototipo a gran escala del detector final, que está ubicado en el Laboratorio Subterráneo de Canfranc, en el Pirineo Aragonés.
L'experiment NEXT és un dels més innovadors en la recerca de la desintegració doble beta sense neutrins, i aquesta troballa donaria amb la resposta a una de les quèstions més importants de la física en els últims anys: és el neutrí la seua pròpia antipartícula? O dit d'una altra manera, és una partícula de Majorana? Per açò NEXT fa ús d'una TPC (Time Projection Chamber) plena de gas xenó enriquit a alta presió, i amb dos plànols de fotosensors, un a cada extrem. El primer d'ells està format per PMTs (Photo Multiplier Tube), que arrepleguen la llum generada pel xenó quan ocorre un esdeveniment, i mesuren l'energía d'aquest. El segon consisteix en una matriu de SiPMs (Silicon PhotoMultipliers) que permeten reconstruir tridimensionalment la traça d'aquest esdeveniment. El conjunt de tots dos plànols de fotosensors atorga a l'experiment NEXT un gran rebuig a esdeveniments de fons, la qual cosa marca la diferència amb altres experiments a la recerca de la desintegració doble beta sense neutrins. A més, els SiPMs so'n una tecnología de recent aparició que en l'actualitat està evolucionant a grans passos per a, en un futur, desplaçar als fotomultiplicadors clàssics. Per això l'estudi d'aquests fotosensors part pràcticament des de zero, ja que no hi ha aplicacions prèvies del seu ús com a pixel-tracking, i ha permés obrir un nou camí en els detectors de física, tant d'alta com de baixa energia. Aquesta tesi doctoral té com a objectiu l'estudi i diseny de l'electrònica involucrada en el plànol de reconstrucció de traces, i que involucra en menor mesura donar solució a problemes tècnics d'aspecte mecànic. Partint dels sensors situats dins del detector, els SiPMs, fins a les targetes de front-end, s'inclouen diversos elements de la cadena; com són les targetes emprades com a suport per als SiPMs a l'interior de la càmera, les quals han de complir rigoroses mesures de radioactivitat i degasificació. També s'ha disenyat el cablejat tant intern com extern, fent èmfasi en aconseguir la major relació possible senyal-soroll; i el passamurs específic per al plànol de reconstrucció de traces, el qual ha resolt a baix cost el problema d'extraure quasi 4000 línies des de la zona de xenó a alta presió fins a l'exterior. Finalment, un dels elements més importants d'aquesta cadena i en el qual es centra principalment aquesta tesi, és la targeta de front-end. Partint de l'experiència adquirida del primer prototip de l'experiment, NEXT-DEMO, s'ha perfeccionat una electrònica capaç de tractar, integrar i adquirir les senyals de tots els SiPM del plànol de reconstrucció de traces, permetent la seua posterior adquisició i processament mitjançant un sistema basat en l'estructura ATCA (Advanced Telecommunications Computing Architecture). Tots els elements disenyats han sigut muntats i engegats en el detector NEW, un prototip a gran escala del detector final, que està situat en el Laboratorio Subterráneo de Canfranc, al Pirineu Aragonés.
Rodríguez Samaniego, J. (2017). Study and design of the front-end and readout electronics for the tracking plane in the NEXT experiment [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/86285
TESIS

This dissertation proposes three novel bandpass filter structures to protect systems exposed to damaging levels of electromagnetic (EM) radiation from intentional and unintentional high-power microwave (HPM) sources. This is of interest because many commercial microwave communications and sensor systems are unprotected from high power levels. Novel technologies to harden front-end components must maintain existing system performance and cost. The proposed concepts all use low-cost printed circuit board (PCB) fabrication to create compact solutions that support high integration.

The first proposed filter achieves size reduction of 46% using a technology that is suitable for low-loss, narrowband filters that can handle high power levels. This is accomplished by reducing a substrate-integrated waveguide (SIW) loaded evanescent-mode bandpass filter to a half-mode SIW (HMSIW) structure. Demonstrated third-order SIW and HMSIW filters have 1.7 GHz center frequency and 0.2 GHz bandwidth. Simulation and measurements of the filters utilizing combline resonators prove the underlying principles.

The second proposed device combines a traditional microstrip bent hairpin filter with encapsulated gas plasma elements to create a filter-limiter: a novel narrowband filter with integral HPM limiter behavior. An equivalent circuit model is presented for the ac coupled plasma-shell components used in this dissertation, and parameter values were extracted from measured results and EM simulation. The theory of operation of the proposed filter-limiter was experimentally validated and key predictions were demonstrated including two modes of operation in the on state: a constant output power mode and constant attenuation mode at high power. A third-order filter-limiter with center frequency of 870 MHz was demonstrated. It operates passively from incident microwave energy, and can be primed with an external voltage source to reduce both limiter turn-on threshold power and output power variation during limiting. Limiter functionality has minimal impact on filter size, weight, performance, and cost.

The third proposed device demonstrates a large-area, light-weight plasma device that interacts with propagating X-band (8-12 GHz) microwave energy. The structure acts as a switchable EM aperture that can be integrated into a radome structure that shields enclosed antenna(s) from incident energy. Active elements are plasma-shells that are electrically excited by frequency selective surfaces (FSS) that are transparent to the frequency band of interest. The result is equivalent to large-area free-space plasma confined in a discrete layer. A novel structure was designed with the aid of full-wave simulation and was fabricated as a 76.2 mm square array. Transmission performance was tested across different drive voltages and incidence angles. Switchable attenuation of 7 dB was measured across the passband when driven with 1400 V_pp at 1 MHz. Plasma electron density was estimated to be 3.6 × 10 ¹² cm^-3 from theory and full-wave simulation. The proposed structure has potential for use on mobile platforms.

In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.

For the new generation wireless communication systems, there is an increasing demand for devices that covers more than one frequency band. This results in a need for wide-band tunable front-ends. The main objective of this study is to use dual band filters in the design of a multi-band front-end. A wide-band low noise amplifier is also required. To accomplish this project, a fixed frequency bandstop filter, a tunable dual-band filter and a wide-band LNA are designed and implemented successfully. The predefined specifications of this front-end include gain, gain flatness, spurious signal rejection, frequency tuning range, noise figure and linearity. Total power dissipation and number of elements are also taken into consideration. Test results of the manufactured front-end are compared with the results of existing single band front-ends. In order to design a good tunable wide-band filter, just tuning its center frequency will not be enough. The noise figure of this dual-band filter will be proportional to its insertion loss if it will be used as a pre-selection filter in front of a LNA. Hence its insertion loss will affect the overall noise figure of the system. If it will be used after the LNA, its linearity will be more important. When a bandpass filter is tuned over wide range of frequencies, its bandwidth varies significantly which leads to a degradation in rejection of the spurious signals. Therefore, there must be a simultaneous control of center frequency, bandwidth and insertion loss while providing enough linearity. In order to accomplish this mission, a filter that has two passbands is designed and implemented. The first passband is tunable between 136MHz and 174MHz while the second one is tunable between 380MHz and 470MHz. Also, the low noise amplifier works properly between 136MHz and 470MHz. As a result, a front-end that covers two bands is obtained.

In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.

The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.

The applied particle physics has a strong R&D tradition aimed at rising the instrumentation performances to achieve relevant results for the scientific community. The know-how achieved in developing particle detectors can be applied to apparently divergent fields like hadrontherapy and cosmic ray detection. A proof of this fact is presented in this doctoral thesis, where the results coming from three different projects are discussed in likewise macro-chapters. A brief introduction (Chapter 1) reports the basic features characterizing a typical particle detector system. This section is developed following the data transmission path: from the sensor, the data moves through the front-end electronics for being readout and collected, ready for the data manipulation. After this general section, the thesis describes the results achieved in two projects developed by the collaboration between the medical physics group of the University of Turin and the Turin section of the Italian Nuclear Institute for Nuclear Physics. Chapter 2 focuses on the TERA09 project. TERA09 is a 64 channels customized chip that has been realized to equip the front-end readout electronics for the new generation of beam monitor chambers for particle therapy applications. In this field, the trend in the accelerators development is moving toward compact solutions providing high-intensity pulsed-beams. However, such a high intensity will saturate the present readout electronics. In order to overcome this critical issue, the TERA09 chip is able to cope with the expected maximum intensity while keeping high resolution by working on a wide conversion-linearity zone which extends from hundreds of pA to hundreds of μA. The chip gain spread is in the order of 1-3% (r.m.s.), with a 200 fC charge resolution. The thesis author took part in the chip design and fully characterized the device. The same group is currently working on behalf of the MoVeIT collaboration for the development of a new silicon strip detector prototype for particle therapy applications. Chapter 3 presents the technical aspects of this project, focusing on the author’s contribution: the front-end electronics design. The sensor adopted for the MoVeIT project is based on 50 μm thin sensors with internal gain, aiming to detect the single beam particle thus counting their number up to 109 cm2/s fluxes, with a pileup probability < 1%. A similar approach would lead to a drastic step forward if compared to the classical and widely used monitoring system based on gas ionization chambers. For what concerns the front-end electronics, the group strategy has been to design two prototypes of custom front-end: one based on a transimpedance preamplifier with a resistive feedback and the other one based on a charge sensitive amplifier. The challenging tasks for the electronics are represented by the charge and dynamic range which are respectively the 3 - 150 fC and the hundreds of MHz instantaneous rate (100 MHz as the milestone, up to 250 MHz ideally). Chapter 4 is a report on the trigger logic development for the Mini-EUSO detector. Mini-EUSO is a telescope designed by the JEM-EUSO Collaboration to map the Earth in the UV range from the vantage point of the International Space Station (ISS), in low Earth orbit. This approach will lay the groundwork for the detection of Extreme Energy Cosmic Rays (EECRs) from space. Due to its 2.5 μs time resolution, Mini-EUSO is capable of detecting a wide range of UV phenomena in the Earth’s atmosphere. In order to maximize the scientific return of the mission, it is necessary to implement a multi-level trigger logic for data selection over different timescales. This logic is key to the success of the mission and thus must be thoroughly tested and carefully integrated into the data processing system prior to the launch. The author took part in the trigger integration in hardware, laboratory trigger tests and also developed the firmware of the trigger ancillary blocks. Chapter 5 closes this doctoral thesis, with a dedicated summary part for each of the three macro-chapters.

The Plasma Impedance Probe (PIP) is an electronic instrument that measures the impedance of a dipole antenna immersed in a plasma environment. Measurements made by the PIP provide valuable information regarding the plasma environment. Knowledge of ionospheric plasma density and density disturbances is required to understand radio frequency communication with satellites. The impedance curve provides us with significant plasma characteristics such as the electron-neutral collision frequency and plasma electron density. The work proposed here is a transistor-level implementation of the analog front-end, the non-inverting amplifier that is used to drive the antenna. The antenna immersed in plasma is excited with a sinusoidal/pulse stimulus and the output from the non-inverting configuration is fed into the difference amplifier. In the difference amplifier the output signal from the non- inverting amplifier is subtracted from the original stimulus and then fed into a high-speed pipeline data converter. The entire analog and mixed signal components are integrated on a single chip. The obvious advantages with this design are that it eliminates several sources of analog signal processing errors, thereby improving stability. A Fast Fourier Transform (FFT) is then applied on the sampled input stimulus as well as the processed signal. The input voltage FFT is then divided by the current FFT to obtain the antenna impedance. The FFT method helps in reducing transient errors and improves noise immunity of the system. The antenna impedance span curves over the frequency range from 100 kHz to 20MHz. The approach for the tranistor-level design is implementing short-channel design tech- niques using the gm/ID method. This is the primary focus of the thesis where the emphasis has been on using a simple and intuitive method to design the front-end amplifier in the TSMC .35 um technology. The design specifications for this amplifier are derived from the system-level simulations. The transition from a Printed Circuit Board (PCB)-based design to System on Chip (SOC) implementation is explored. This makes the design components highly specific to the application. The following are the design approaches used for the analog front-end design. * A detailed study of the various factors affecting the PIP instrument measurement capabilities from the previous works. * System-level simulation of the the entire PIP system to completely characterize the analog front-end. * Exploration of the possible design topologies for the transistor-level implementation. * A novel method of analog amplifier design using the gm/ID methodology. Miniaturization of the instrument and using a pulse-based measurement scheme also offer an immediate benefit to sounding rocket missions. The reduction of power, mass, and volume will enable the instrument to be flown on many more sounding rockets than at present. The faster measurement is especially valuable since the ionospheric plasma changes in character most rapidly with altitude.

[EN] Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals. The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one. As a first step, a general study of DAQ arquitectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards. Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the particular case of two detectors. This DAQ is finally installed at the experimental setup, where their synchronization properties and resolution as a PET system are characterized and its performance is verified to have improved with respect to the previous system.
[ES] La Tomografía por Emisión de Positrones (PET) es una modalidad de imagen médica nuclear no invasiva que permite observar la distribución de sustancias metabólicas en el interior del cuerpo de un paciente tras marcarlas con isótopos radioactivos y disponer después un escáner anular a su alrededor para detectar su desintegración. Las principales aplicaciones de esta técnica son la detección y seguimiento de tumores en pacientes con cáncer y los estudios metabólicos en animales pequeños. El grupo de investigación Electronic Design for Nuclear Applications (EDNA) del Instituto de Instrumentación para Imagen Molecular (I3M) ha estado involucrado en el estudio de sistemas PET de alto rendimiento y mantiene un pequeño setup experimental con dos módulos detectores. La presente tesis se enmarca dentro de la necesidad de desarrollar un nuevo sistema de adquisición de datos (DAQ) para dicho setup que corrija los inconvenientes del ya existente. En particular, el objetivo es definir una arquitectura de DAQ que sea totalmente escalable, modular, y que asegure la movilidad y la posibilidad de reutilización de sus componentes, de manera que admita cualquier ampliación o alteración del setup y pueda exportarse directamente a los de otros grupos o experimentos. Al mismo tiempo, se desea que dicha arquitectura no limite artificialmente el rendimiento del sistema sino que sea compatible con las mejores resoluciones disponibles en la actualidad, y en particular que sus prestaciones superen a las del DAQ instalado previamente. En primer lugar, se lleva a cabo un estudio general de las arquitecturas de DAQ para setups experimentales para PET y otras aplicaciones de física de altas energías. Por un lado, se determina que las características deseadas implican la digitalización temprana de las señales del detector, la comunicación exclusivamente digital entre módulos, y la ausencia de trigger centralizado. Por otro lado, se hace patente la necesidad de un esquema de sincronización distribuida muy preciso entre módulos, con errores del orden de 100 ps, que opere directamente sobre los enlaces de datos. Un estudio de los métodos ya existentes revela sus graves limitaciones a la hora de alcanzar esas precisiones. Con el fin de paliarlos, se lleva a cabo un análisis teórico de la situación y se propone un nuevo algoritmo de sincronización que es capaz de alcanzar la resolución deseada y elimina las restricciones de alineamiento de reloj impuestas por casi todos los esquemas usuales. Dado que la medida de desfase entre relojes juega un papel crucial en el algoritmo propuesto, se definen y analizan extensiones a los métodos ya existentes que suponen una mejora sustancial. El esquema de sincronismo propuesto se valida utilizando placas de evaluación comerciales. Partiendo del método de sincronismo propuesto, se define una arquitectura de DAQ para PET compuesta de dos tipos de módulos (adquisición y concentración) cuya replicación permite construir un sistema jerárquico de tamaño arbitrario, y se diseñan e implementan placas de circuito basadas en dicha arquitectura para el caso particular de dos detectores. El DAQ así construído se instala finalmente en el setup experimental, donde se caracterizan tanto sus propiedades de sincronización como su resolución como sistema PET y se comprueba que sus prestaciones son superiores a las del sistema previo.
[CAT] La Tomografia per Emissió de Positrons (PET) és una modalitat d'imatge mèdica nuclear no invasiva que permet observar la distribució de substàncies metabòliques a l'interior del cos d'un pacient després d'haver-les marcat amb isòtops radioactius disposant un escàner anular al seu voltant per a detectar la seua desintegració. Aquesta tècnica troba les seues principals aplicacions a la detecció i seguiment de tumors a pacients amb càncer i als estudis metabòlics en animals petits. El grup d'investigació Electronic Design for Nuclear Applications (EDNA) de l'Instituto de Instrumentación para Imagen Molecular (I3M) ha estat involucrat en l'estudi de sistemes PET d'alt rendiment i manté un petit setup experimental amb dos mòduls detectors. Aquesta tesi neix de la necessitat de desenvolupar un nou sistema d'adquisició de dades (DAQ) per al setup esmentat que corregisca els inconvenients de l'anterior. En particular, l'objectiu és definir una arquitectura de DAQ que sigui totalment escalable, modular, i que asseguri la mobilitat i la possibilitat de reutilització dels seus components, de tal manera que admeta qualsevol ampliació o alteració del setup i pugui exportar-se directament a aquells d'altres grups o experiments. Al mateix temps, es desitja que aquesta arquitectura no introduisca límits artificials al rendiment del sistema sinó que sigui compatible amb les millors resolucions disponibles a l'actualitat, i en particular que les seues prestacions siguin superiors a les del DAQ instal.lat amb anterioritat. En primer lloc, es porta a terme un estudi general de les arquitectures de DAQ per a setups experimentals per a PET i altres aplicacions de física d'altes energies. Per una banda, s'arriba a la conclusió que les característiques desitjades impliquen la digitalització dels senyals del detector el més aviat possible, la comunicació exclusivament digital entre mòduls, i l'absència de trigger centralitzat. D'altra banda, es fa palesa la necessitat d'un mecanisme de sincronització distribuïda molt precís entre mòduls, amb errors de l'ordre de 100 ps, que treballi directament sobre els enllaços de dades. Un estudi dels mètodes ja existents revela les seues greus limitacions a l'hora d'assolir aquest nivell de precisió. Amb l'objectiu de pal.liar-les, es duu a terme una anàlisi teòrica de la situació i es proposa un nou algoritme de sincronització que és capaç d'obtindre la resolució desitjada i es desfà de les restriccions d'alineament de rellotges imposades per gairebé tots els esquemes usuals. Atès que la mesura del desfasament entre rellotges juga un paper cabdal a l'algoritme proposat, es defineixen i analitzen extensions als mètodes ja existents que suposen una millora substancial. L'esquema de sincronisme proposat es valida mitjançant plaques d'avaluació comercials. Prenent el mètode proposat com a punt de partida, es defineix una arquitectura de DAQ per a PET composta de dos tipus de mòduls (d'adquisició i de concentració) tals que la replicació d'aquests elements permet construir un sistema jeràrquic de mida arbitrària, i es dissenyen i implementen plaques de circuit basades en aquesta arquitectura per al cas particular de dos detectors. L'electrònica desenvolupada s'instal.la finalment al setup experimental, on es caracteritzen tant les seues propietats de sincronització com la seua resolució com a sistema PET i es comprova que les seues prestacions són superiors a les del sistema previ.
Aliaga Varea, RJ. (2016). Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63271
TESIS
Premiado

In this thesis the design, control, stability, input power quality, and motor drive performance of ac motor drives with front end three phase diode rectifiers utilizing low capacitance dc bus capacitor are investigated. Detailed computer simulations of conventional motor drives with diode rectifier front end utilizing high capacitance dc bus capacitor and the drives with low capacitance dc bus capacitor are conducted and the performances are compared. Performance evaluation of various active control methods found in previous studies aiming to provide the dc bus stability of drives with low capacitance dc bus capacitor are done at various load levels and types. Design recommendations are provided for the drives utilizing low capacitance dc bus capacitor.

Le travail présenté dans ce manuscrit a été effectué au sein de l’équipe de microélectronique de l’Institut de Recherche sur les lois Fondamentales de l’Univers (IRFU) du CEA. Il s’inscrit dans le contexte de la spectro-imagerie X et gamma pour la recherche en Astrophysique. Dans ce domaine, les futures expériences embarquées à bords de satellites nécessiteront des instruments d’imagerie à très hautes résolutions spatiales et énergétiques.La résolution spectrale d’une gamma-camera est dégradée par l’imperfection du détecteur lors de l’interaction photon-matière lui-même et par le bruit électronique. Si on ne peut réduire l’imprécision de conversion photon-charge du détecteur, on peut minimiser le bruit apporté par l’électronique de lecture. L’objectif de cette thèse est la conception d’une électronique intégrée de lecture de détecteur semi-conducteurs CdTe pixélisés pour gamma-caméra(s) compacte(s) et aboutable(s) sur 4 côtés à résolution spatiale « Fano limitée ». Les objectifs principaux de ce circuit intégré sont: un très bas bruit pour la mesure d’énergie des rayons-X, une très basse consommation, et une taille de canal de détection adaptée au pas des pixels CdTe. Pour concevoir une telle électronique, chaque paramètre contribuant au bruit doit être optimisé. L’hybridation entre l’électronique de lecture et le détecteur est également un paramètre clef qui fait généralement la résolution finale de l’instrument : en imposant une géométrie matricielle à l’ASIC adaptée au pas de 300 µm des pixels de CdTe, on peut espérer, réduire d’un facteur 10 la capacité parasite amenée par la connexion détecteur-électronique et améliorer d’autant le bruit électronique tout en conservant une densité de puissance constante. Une bonne connaissance des propriétés du détecteur nous permet alors d’extraire ses paramètres électroniques clefs pour concevoir l’architecture électronique de conversion et de filtrage optimale. Dans le cadre de cette thèse j’ai conçu deux circuits intégrés en technologies CMOS XFAB 0.18 µm. Le premier, Caterpylar, est destiné à caractériser cette nouvelle technologie, y compris en radiation, identifier un étage d’entrée pour le pixel adapté au détecteur, et valider par la mesure les résultats théoriques établis sur deux architectures de filtrage, semi gaussien et « Multi-Correlated Double Sampling » (MCDS), approchant l’efficacité du filtrage optimal et adaptées aux applications finales. Le deuxième circuit, D2R1, est un système complet, constitué de 256 canaux de lecture de détecteur CdTe, organisés dans une matrice de 16×16 pixels. Chaque canal comprend un préamplificateur de charge adapté à des pixels de 300 μm×300 μm, un opérateur de filtrage de type MCDS de profondeur programmable, d’un discriminateur auto-déclenché à bas seuil de détection programmable par canal. L’ASIC a été caractérisé sans détecteur et est en voie d’être hybridé à une matrice de CdTe très prochainement. Les résultats de caractérisations de la puce nue, en particulier en terme de produit puissance × bruit, sont excellents. La consommation de la puce est de 315 µW/ canal, la charge équivalente de bruit mesurée sur tous les canaux est de 29 électrons rms. Ces résultats valident le choix d’intégration d’un filtrage de type MCDS, qui est, à notre connaissance une première mondiale pour la lecture de détecteurs CdTe. Par ailleurs, ils nous permettent d’envisager d’excellentes résolutions spectrales de l’ensemble détecteur+ASIC, de l’ordre de 600 eV FWHM à 60 keV
The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l’Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit.In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit. related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF - 1 pF and a dark current below 5 pA.In the frame of this thesis I have designed two ASICs. The first one, Caterpylar, is a testchip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 μm pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D2R1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16×16 array. Each channel fits into a layout area of 300 μm × 300 μm. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 μW⁄channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV

Il s'agit à la fois d'étudier des détecteurs de particules (électrons et neutrons) en carbure de silicium à l'état de l'art, et de réaliser une interface électronique reconfigurable et intégrée adaptative à partir de technologies durcies pour le conditionnement et le traitement du signal électrique généré. Le front-end électronique (électronique de lecture) devra être capable d'extraire les signaux utiles (réponse en courant) des détecteurs ayant des caractéristiques différentes (dimensions, temps de réponse) et de fournir des données résolues (nature de la particule, spectroscopie, etc.) à l'aide de processeur embarqué. Plusieurs scénarios de co-intégration de l’ensemble " détecteur et électronique de lecture " prenant en compte l'environnement d'utilisation seront étudiés pour concevoir un détecteur de particules muni d'intelligence embarquée et plaçant ainsi l'étude à l'état de l’art
It involves both studying a state-of-the-art silicon carbide particles (electrons and neutrons) detector and producing an adaptive integrated reconfigurable electronics interface from hardened technologies for the conditioning and processing electrical signal generated. The electronics front-end will be capable to extract all useful signals (current answer) from the detector having different characteristics (dimensions, response times) and providing resolved data (nature of the particle, spectroscopy, etc.) using on-board processor. Several scenarios of co-integration of the "detector and electronic reading" assembly taking into account the environment of use will be studied to design a particle detector equipped with on-board intelligence and placing the study in the state of art

The number of vehicles has increased significantly in recent years, which causeshigh density in traffic and further problems like accidents and road congestions.A solution regarding to this problem is vehicle-to-vehicle communication, wherevehicles are able to communicate with their neighboring vehicles even in the absenceof a central base station, to provide safer and more efficient roads and toincrease passenger safety.The goal of this thesis is to investigate basic physical layer parameters of ainter-vehicle communication system, like emission power, spectral emission, errorvector magnitude, guard interval, ramp-up/down time, and third order interceptpoint. I also studied the intelligent transportation system’s channel layout inEurope, how the interference of other systems are working in co-channel and adjacentchannels, and some proposals to use the allocated frequency bands. On theother hand, the fundamentals of OFDM transmission and definitions of OFDMkey parameters in IEEE 802.11p are investigated.The focus of this work is on the measurement of transmitter frontend parametersof a new testbed designed and fabricated in order to be used at inter-vehiclecommunication based on IEEE 802.11p.

Road safety applications, Vehicle-to-Vehicle communication

Orientador: Hugo Enrique Hernadez Figueroa
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-25T04:08:57Z (GMT). No. of bitstreams: 1 Baron_RafaelAntonio_M.pdf: 2527156 bytes, checksum: b044c223ca1a051a13e9264f599fe8c2 (MD5) Previous issue date: 2014
Resumo: Atualmente está em fase de projeto o novo acelerador de elétrons do Laboratório Nacional de Luz Síncrotron (LNLS). Este acelerador de partículas, denominado Sirius, é constituído por diversos sistemas de instrumentação, sendo um deles de particular interesse para o diagnóstico de posição do feixe de elétrons estocado no acelerador. Este sistema, denominado monitor de posição de feixe, é constituído por sua vez por outros subsistemas, dentre os quais uma eletrônica de RF, dedicado a fazer processamento analógico de sinais de Rádio Frequência advindos de sensores que interagem eletromagneticamente com o feixe de elétrons. Esta eletrônica de RF deve condicionar o sinal, fornecendo ganho, filtragem, linearidade e estabilidade necessárias na faixa de operação de potências de entrada para que o sinal possa ser digitalizado. Este trabalho tem por objetivo descrever a respeito do desenvolvimento desta eletrônica, abarcando o projeto do circuito de RF de alta linearidade e alta estabilidade, implementação em placa de circuito impresso e testes em bancada e no acelerador de elétrons UVX, do LNLS
Abstract: The new electron accelerator of the Brazilian Synchrotron Light Laboratory (LNLS) is being designed to provide users with more brilliant photon beams. This particle accelerator, called Sirius, is composed of hundreds of instrumentation systems that are responsible for the machine operation. The Beam Position Monitor System is dedicated to monitor the position of the electron beam stored inside the vacuum chamber of the machine. It is composed by a subsystem called RF Front-End, dedicated to the analog processing of the beam signals that is originated by the interaction between the ultra-relativistic electromagnetic field of the electron beam and sensors specially designed for it. The RF Front-End electronics have been designed to provide filtering and gain with high linearity and stability along all the input power range. This work presents the design of the electronics, its implementation in printed-circuit board and tests results that have been performed in the laboratory and with a real beam signal
Mestrado
Telecomunicações e Telemática
Mestre em Engenharia Elétrica