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1
Ventruba, Petr. „Výroba prototypu lovecké kuše“. Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2021. http://www.nusl.cz/ntk/nusl-444290.
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This master's thesis deals with the manufacturing of a hunting crossbow prototype. The first part summarizes the history of crossbows, their historical development and usage. The following chapter contains theoretical knowladge about the technological methods that are used in the production. This is followed by a designing of the prototype, creating a technological process and final production. Final part of this thesis evaluates individual parts of the production and the final prototype.
2
Landrus, Matthew. „Leonardo's canons : standards and practices of proportional design in his early work, with special reference to his 'Last supper' and 'Giant crossbow'“. Thesis, University of Oxford, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.433355.
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Wu, Ting. „Design of terabits/s CMOS crossbar switch chip /“. View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WU.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.
4
Zhang, Yixuan. „High-Performance Crossbar Designs for Network-on-Chips (NoCs)“. Ohio University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1282056856.
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Beeley, James Malcolm. „Design and construction of a distributed crossbar switch hypermesh parallel computer“. Thesis, University of Glasgow, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.401958.
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Shin, Eung Seo. „Automated Generation of Round-robin Arbitration and Crossbar Switch Logic“. Diss., Available online, Georgia Institute of Technology, (2003), 2003. http://etd.gatech.edu/theses/available/etd-11232003-150424/.
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7
Yoshigoe, Kenji. „Design and evaluation of the combined input and crossbar queued (CICQ) switch“. [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000464.
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Hung, Chun-Kit. „VLSI design of high-speed and scalable schedulers for input-queued crossbar switches /“. View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HUNG.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 82-84). Also available in electronic version. Access restricted to campus users.
9
Levisse, Alexandre. „3D high density memory based on emering resistive technologies : circuit and architecture design“. Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0584.
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Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAMWhile conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures
10
Hasan, Md Raqibul. „Memristor Based Low Power High Throughput Circuits and Systems Design“. University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1459522347.
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11
Bhide, Kanchan P. „DESIGN ENHANCEMENT AND INTEGRATION OF A PROCESSOR-MEMORY INTERCONNECT NETWORK INTO A SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE“. UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/253.
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This thesis involves modeling, design, Hardware Description Language (HDL) design capture, synthesis, implementation and HDL virtual prototype simulation validation of an interconnect network for a Hybrid Data/Command Driven Computer Architecture (HDCA) system. The HDCA is a single-chip shared memory multiprocessor architecture system. Various candidate processor-memory interconnect topologies that may meet the requirements of the HDCA system are studied and evaluated related to utilization within the HDCA system. It is determined that the Crossbar network topology best meets the HDCA system requirements and it is therefore used as the processormemory interconnect network of the HDCA system. The design capture, synthesis, implementation and HDL simulation is done in VHDL using XILINX ISE 6.2.3i and ModelSim 5.7g CAD softwares. The design is validated by individually testing against some possible test cases and then integrated into the HDCA system and validated against two different applications. The inclusion of crossbar switch in the HDCA architecture involved major modifications to the HDCA system and some minor changes in the design of the switch. Virtual Prototype testing of the HDCA executing applications when utilizing crossbar interconnect revealed proper functioning of the interconnect and HDCA. Inclusion of the interconnect into the HDCA now allows it to implement dynamic node level reconfigurability and multiple forking functionality.
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Alhaj, Ali Khaled. „New design approaches for flexible architectures and in-memory computing based on memristor technologies“. Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2020. http://www.theses.fr/2020IMTA0197.
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Le développement récent de nouvelles technologies de mémoires non-volatiles basées sur le concept de memristor a suscité de nombreux efforts pour explorer leur utilisation potentielle dans différents domaines d'application. Les propriétés uniques de ces dispositifs memristifs et leur compatibilité pour uneintégration avec les technologies CMOS conventionnelles permettent de nouveaux paradigmes de conception d’architecture, offrant des niveaux sans précédent de densité, de reconfigurabilité et d’efficacité énergétique. Dans ce contexte, le but de ce travail de thèse était d'explorer et d'introduire de nouvelles approches de conception basées sur les memristors pour combiner flexibilité et efficacité en proposant des architectures originales qui dépassent les limites des architectures existantes. Cette exploration et cette étude ont été menées à trois niveaux : interconnexion, traitement et mémoire. Au niveau des interconnexions, nous avons étudié l'utilisation de dispositifs memristifs pour permettre une grande flexibilité basée sur des réseaux d'interconnexion programmables. Cela a permis de proposer la première architecture de transformée de Fourier rapide reconfigurable basée sur des memristors, nommée mrFFT. Les memristors sont insérés comme des commutateurs reconfigurables au niveau des interconnexions afin d'établir un routage flexible puce. Au niveau du traitement, nous avons exploré l'utilisation de dispositifs memristifs et leur intégration avec les technologies CMOS pour la conception de fonctions logique combinatoire. Ces circuits hybrides memristor-CMOS exploitent la forte densité d'intégration des memristors afin d'améliorer les performances des implémentations numériques, et en particulier des unités arithmétiques et logiques. Au niveau mémoire, une nouvelle approche de calcul en mémoire a été introduite. Dans ce contexte, un nouveau style de conception logique a été proposé, nommé Memristor Overwrite Logic (MOL), associé à une architecture originale de mémoire de calcul. L’approche proposée permet de combiner efficacement le stockage et le traitement afin de contourner les problèmes liés aux accès mémoire et d'améliorer ainsi l'efficacité de calcul. L'approche proposée a été appliquée dans trois études de cas à des fins de validation et d'évaluation des performancesThe recent development of new non-volatile memory technologies based on the memristor concept has triggered many research efforts to explore their potential usage in different application domains. The distinctive features of memristive devices and their suitability for CMOS integration are expected to lead for novel architecture design paradigms enabling unprecedented levels of energy efficiency, density, and reconfigurability. In this context, the goal of this thesis work was to explore and introduce new memristor based designs that combine flexibility and efficiency through the proposal of original architectures that break the limits of the existing ones. This exploration and study have been conducted at three levels: interconnect, processing, and memory levels. At interconnect level, we have explored the use of memristive devices to allow high degree of flexibility based on programmable interconnects. This allows to propose the first memristor-based reconfigurable fast Fourier transform architecture, namely mrFFT. Memristors are inserted as reconfigurable switches at the level of interconnects in order to establish flexible on-chip routing. At processing level, we have explored the use of memristive devices and their integration with CMOS technologies for combinational logic design. Such hybrid memristor-CMOS designs exploit the high integration density of memristors in order to improve the performance of digital designs, and particularly arithmetic logic units. At memory level, we have explored new in-memory computing approaches and proposed a novel logic design style, namely Memristor Overwrite Logic (MOL), associated with an original MOL-based computational memory. The proposed approach allows efficient combination of storage and processing in order to bypass the memory wall problem and thus to improve the computational efficiency. The proposed approach has been applied in three real application case studies for the sake of validation and performance evaluation
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Matos, Débora da Silva Motta. „Exploring hierarchy, adaptability and 3D in NoCs for the next generation of MPSoCs“. reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/94764.
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A demanda por sistemas com elevado desempenho tem trazido a necessidade de aumentar o número de elementos de processamento, surgindo os chamados Sistemas em Chip Multiprocessados (MPSoCs). Além disso, com a possibilidade de redução da escala tecnológica na era submicrônica, permitindo a integração de vários dispositivos, os chips têm se tornado ainda mais complexos. No entanto, com o aumento no número de elementos de processamento, as interconexões são vistas com o principal gargalo dos sistemas-em-chip. Com isso, uma preocupação na forma como tais elementos se comunicam e estão interconectados tem sido levantada, uma vez que tais características são cruciais nos aspectos de desempenho, energia e potência, principalmente em sistemas embarcados. Essa necessidade permitiu o advento das redes-em-chip (Networks-on-Chip – NoCs) e inúmeros estudos já foram realizados para tais dispositivos. No entanto, devido ao aceleramento tecnológico atual, que traz a necessidade por sistemas ainda mais complexos, que consumam baixa energia e que permitam que as aplicações sejam constantemente atualizadas sem perder as características de desempenho, as arquiteturas de interconexão tradicionais não serão suficientes para satisfazer tais desafios. Outras alternativas de interconexão para MPSoCs precisam ser investigadas e nesse trabalho novas arquiteturas para NoCs com tais requisitos são apresentadas. As soluções propostas exploram hierarquia, adaptabilidade e interconexões em três dimensões. Esse trabalho aborda a necessidade do uso de diferentes estratégias em NoCs a fim de atingir os requisitos de desempenho e baixo consumo de potência dos atuais e futuros MPSoCs. Dessa forma, serão verificadas as diversas arquiteturas de interconexões para sistemas heterogêneos, sua escalabilidade, suas principais características e as vantagens das propostas apresentadas sobre as demais soluções.The demand for systems with high performance has brought the need to increase the number of cores, emerging the called Multi-Processors System-on-Chip (MPSoCs). Also, with the shrinking feature size in deep-submicron era, allowing the integration of several devices, chips have become even more complex. However, with the increase in these elements, interconnections are seen as the main bottleneck in many core systemson- chip. With this, a concern about how these devices communicate and are interconnected has been raised, since these features are crucial for the performance, energy and power consumption aspects, mainly in embedded systems. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies had already been done to analyze such interconnection devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming lower energy and providing constant application updates without losing performance features, traditional interconnect architectures will not be sufficient to satisfy such challenges. Other interconnecting alternatives for MPSoCs need to be investigated and in this work, novel architectures for NoCs meeting such requirements are presented. The proposed solutions explore hierarchy, adaptability and three dimensional interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the performance requisites and low power consumption of the current and future MPSoCs. Hence, in this approach, several interconnection architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.
14
Tsai, Yin-Sheng, und 蔡吟聲. „Design and Implementation of a Crossbar ATM Switch“. Thesis, 1995. http://ndltd.ncl.edu.tw/handle/25864256201053122152.
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碩士國立交通大學
電信研究所
83
Although there are many designs of ATM switch proposed, only few of them have been implemented. The main reason is that hardware implementation takes a lot of time and costs much. However, any idea must be put into practice. So, it is very important to develop a method to implement the design easily. The purpose of this paper is to test the feasibility and complexity of a methodology for the development of an integrated circuit, which combines the new design method "Hardware Description Language"(HDL) and the new chip implementation product "Field Programmable Gate Array"(FPGA) to design and implement an ATM switch. This ATM switch uses Crossbar as the switching fabric. The cells are buffered at input temporarily, and the output contention problem is solved by "Round Robin" mechanism. First , the input ports examine whether there are cells to be switched. We propose two ways to do the examination. Second, from the header of each cell, the input port gets the routing information for switch control circuit. This routing information includes a routing ID and a priority bit. Then the switch control circuit used this information to provide switching fabric the "switch pattern". Finally, the switching fabric switches the cells. This thesis uses the VHDL programing language to describe the behavior of each module, then uses the high level automatic design software, including the Synthesizer and the Simulator, surpported by SYNOPSYS company to finish the high level design. The translation programs surpported by XILINX company then translate the netlist to the bitstream for the use of XILINX FPGA chip. Finally, using the logic analyzer and in-circuit emulator to help the implementation of the circuit. After two year's study, a complete 2 by 2 ATM switch circuit has been done. So, we can say that the new IC design method is applicable for the design and implementation of ATM switch.
15
Jhang, Jhao-Nan, und 張兆男. „Design and Simulation of Scalable Multicasting Crossbar Switches“. Thesis, 2006. http://ndltd.ncl.edu.tw/handle/03896305938618277703.
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碩士國立臺北大學
通訊工程研究所
94
Currently, multicast switches are very significant in heavy traffic networks due to many kinds of data that included videos, voices and images. How to reduce the data loss rate caused by blocking becomes an important issue in the process of duplication and routing of the packets. In this thesis, we propose the multicast crossbar switches with inner queues in each crosspoint. There is no additional control circuits needed to accomplish the purposes of duplication and self-routing. To reduce the data loss rate, we store the duplicated packets in the inner queues and wait for next timeslot to proceed. When the inner queues is fulfilled, the following packets will be lost, which is so-called “Overflow”. The thesis presents an approach, by controlling the interarrival time of two sequential groups of packets, to reduce the data loss rate to 10-6 or less efficiently. Since its simple architecture, its hardware implementation can be realized easily with good scalability and stackability.
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Hsiang, Yi Huang, und 黃湘怡. „Design and Implementation of Birkhoff-von Neumann Crossbar Switches“. Thesis, 1999. http://ndltd.ncl.edu.tw/handle/89875164059305388830.
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碩士國立清華大學
電機工程學系
87
Because of the memory access time limitation on switching speed, the input buffered crossbar switch architecture has been widely used for high speed networks. However, the potential Head-Of-Line blocking may reduce the throughput. In order to provide service guarantees, various scheduling algorithms with special Virtual Output queueing technique have been proposed to overcome this problem. The Birkhoff-von Neumann crossbar switch has been shown to provide uniform service guarantee for all non-uniform traffic and achieve 100% throughput without framing or internal speedup. In this thesis, we design and implement an 4×4 input-buffered Birkhoff-von Neumann crossbar switch by carrying out its on-line algorithm and switching fabric on a FPGA chip.
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Hung, Li-Chuan, und 洪麗娟. „Design of Partially Buffered Crossbar Switches for Supporting Mixed Traffic“. Thesis, 2011. http://ndltd.ncl.edu.tw/handle/17005872659265676871.
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碩士國立雲林科技大學
資訊工程研究所
99
Because new multicasting applications on the Internet are numerous, the demands of multicast traffic will continue growing. Currently, the CICQ with N2 VOQs for unicast flow and k MQs for multicast flow is the major architecture to support mixed traffic. In this study, we propose a switch called multicast virtual output queues and partially buffered crossbar switch (MQ-PBC) to support mix traffic. The number of CB in MQ-PBC switch is much less than traditional CICQ switch and a three phase (request-grant-accept) matching algorithm is adopted to solve the contentions. We also proposed a selecting scheme, MURR, for input schedulers. The experimental results showed that the proposed MQ-PBC switch can achieve well performance and efficiently support the mix traffic.
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Tse, Cindy Ho Yan. „A New Metropolitan Cultural Ligament: Toronto Eglinton Crosstown LRT Prototypical Design Proposal“. Thesis, 2010. http://hdl.handle.net/10012/5013.
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This thesis strives to establish a set of design guidelines for the upcoming Eglinton Crosstown Light Rail Transit development in Toronto. The primary design goals are to promote an enjoyable travel experience to commuters, offer positive public spaces in vicinity, and contribute to the greater social and cultural matrices of the city. Under a realistic project setting, the study will meditate upon spatial anthropological theories to identify essential public space qualities and to formulate underground lighting strategies.
The main objective is to complete the development of both underground station and surface stop prototypes that can be flexibly implemented along the entire transit line. The vision is for these stations to not only provide convenient public transit amenities but also function as locale identifiers, showcasing Toronto’s culture virtually as unique rooms in a gallery. Three sites are chosen: Mount Pleasant, Dufferin, and Keele stations. These stations will provide interesting conditions to demonstrate the way in which a set of design guidelines can facilitate the positive development of subway stations into the powerful loci envisioned.
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Lin, Jhih-Jie, und 林智傑. „VLSI Design of Low-Error Multiplier and High-Performance Crossbar for DSP“. Thesis, 2007. http://ndltd.ncl.edu.tw/handle/19185495256940661425.
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碩士國立雲林科技大學
電子與資訊工程研究所
95
Multiplication is frequently required in the DSP. For the reasons of the higher speed and lower area, the thesis proposes the new truncation multiplier to improve the system performance. Besides, considering that the shared bus architecture can not supply the bandwidth of system on transmission data network, this thesis also presents a switch circuit and implementation to replace the shared bus for increasing bandwidth of transmission data between blocks. First of all, we develop a low-error algorithm of truncation multiplier. Comparing to the previous works used ECP for compensation, our approach can achieve more accurate truncated results after our simulation and analyze. Based the proposed algorithm, two compensation circuit designs are proposed for the lower errors multiplier, and are proved by using Matlab and Hspice. Moreover, in error analysis, the mean, max, and mean-square errors for our truncated multipliers are reduced to “0.200” ,”1.473” and “0.016” respectively. On high performance switch circuit, the arbiter and crossbar are two important element circuits. The performance of arbiter will direct to effect transmission data performance between input ports and output ports. This paper will use mask circuit to mask serviced requests, and it can achieve fair arbitration. The delay, hardware cost and power consumption of our arbiter circuit can reduce about 25%, 25% and 15% respectively than Mux-Tree work from simulation. The power consumption of switch circuit reduces to get up to 36% than Mux-Tree work. The improving performance of switch will get enhancement apparently when input of switch increases. Under the TSMC 0.18 processes, the switch can achieve power consumption of 2.09mW, and die size of 0.14mm² .
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Sethi, Sandeep. „Transient permeate flux analysis, cost estimation, and design optimization in crossflow membrane filtration“. Thesis, 1997. http://hdl.handle.net/1911/19209.
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A generalized model is formulated to predict the time-dependent permeate flux by extending previous models to include the particle transport mechanisms of Brownian diffusion, shear-induced diffusion, inertial lift and concentrated flowing layers. A new model for estimating the capital costs of membrane plants is developed which incorporates individual cost correlations for different categories of manufactured equipment. The effects of particle size, design, and operating variables on permeate flux and treatment costs are investigated numerically. Optimization problems are formulated and solved to investigate (a) optimal membrane design and system operation, (b) optimal backflushing frequency, and (c) optimal selection of hybrid filtration configurations, over variable raw water quality.
The combined theory predicts an unfavorable particle size, on the order of 10$\sp{-1}\ \mu$m, where net back-transport is at a minimum. This implies minimum permeate fluxes in the size range of 10$\sp{-2}\ \mu$m - 10$\sp{-1}\ \mu$m, depending on the operating time. These results support experimental observations of minima in back-transport (Chellam and Wiesner, 1996) and permeate flux (Fane, 1984). Inside-out hollow fiber geometry is predicted to be favorable for feed suspensions with small particles and/or low concentrations. The constant pressure mode of operation is predicted to yield higher specific permeate fluxes compared to the constant flux mode, particularly for particles which demonstrate mass-transfer limited behavior. Comparisons and parameter estimations made with available experimental data on polydisperse suspensions give solidosity estimates ranging from 0.70 to 0.77.
Membrane design is predicted to be optimized at values of fiber radius (narrow) and length (short) where the permeate fluxes are maximized. Particles affected by mass-transport limitations demonstrate comparatively lower optimal transmembrane pressures. For unfavorable particles, treatment costs are predicted to be minimized at intermediate recoveries and backflushing frequencies. At small capacities, the hybrid hollow fiber ultrafiltration and spiral wound nanofiltration system with higher non-membrane capital costs is predicted to be largely non-optimal compared to hollow fiber nanofiltration. Membrane costs are expected to play a significant role in determining the optimal configuration at large capacities, where the hybrid configuration is predicted to become largely optimal.
21
Awan, Atiq. „Design, simulation and implementation of enhanced crossbar combined input-output queued switch architecture /“. 2004.
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22
Wu, Cheng-Feng, und 吳政峰. „Design of Buffered Crossbar Switches with Large RTT Latency for Supporting Mixed Traffic“. Thesis, 2010. http://ndltd.ncl.edu.tw/handle/31980404800423675132.
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碩士雲林科技大學
資訊工程研究所
98
The management of core switches has been evolved from single cabinet to multiple cabinets. Therefore, the extended distance between cabinets would increase the round trip time (RTT) of control packets. To avoid the decreased performance caused by RTT, it is necessary to increase crosspoint buffer size to overcome the issue in the switch fabric. When a traditional buffered crossbar switch deals with mixed traffic, unicast and multicast traffic share the same set of crosspoint buffers. It will increase extra delay of multicast traffic while unicast and multicast packets contend for the same buffer. In this thesis, we propose a switch called m-VOQs-CB with m-IMQs to support both traffic types under the large RTT environment. The switch fabric is separated into one unicast section and one multicast section. The unicast section consists of VCQs and CBs, and the multicast section MF-IMQs and CBs. We use two scheduling schemes, MFRR and MURR, for output schedulers, and use the partial fanout policy for supporting mixed traffic. The simulation results show that the proposed m-VOQs-CB with m-IMQs can not only reduce the size demand of crosspoint buffers but also has lower multicast delay.
23
Jao, Zhi-Chun, und 饒智淳. „Design of a Partially Buffered Crossbar Router for Mesh-based Network-on-Chips“. Thesis, 2011. http://ndltd.ncl.edu.tw/handle/24177252714651534860.
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碩士國立雲林科技大學
資訊工程研究所
99
With an increase in the number of transistors on-chip, the complexity of the system also increases. In order to cope with the growing interconnection infrastructure, the Networks-on-chip (NoC) concept was introduced. The router plays an important role since it can affect the overall performance of the NoC. In the literature, the NoC employs input-queued routers to receive and transmit packets. In this study, we employ a Partially Buffered Crossbar (PBC) router architecture which consists of virtual channels (VCs) and a small number of separate internal buffers that are maintained per fabric column output for the NoC. In our experiment, results show that the performance of a PBC router can improve a lot compared with a traditional virtual channel (TVC) router.
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Wu, Cheng-Kwang, und 吳建寬. „Design and Simulation of Fault-Tolerant Crossbar Switches for Multiprocessor Systems with VHDL“. Thesis, 1994. http://ndltd.ncl.edu.tw/handle/87331911686192482042.
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碩士國立交通大學
資訊科學學系
82
In this thesis, we propose two general crossbar switch models, the modified one-sided crossbar switch and the ripple k one- sided crossbar switch, which both balance between cost and fault tolerance degree. The two-sided crossbar switch and the one-sided crossbar switch are just two special cases of the above two new structures. These two structures provide choices for compromising structures between the two-sided crossbar siwtch and the one-sided crossbar switch in terms of cost and fault tolerance degree. We have derive a mathematical model to simulate the effective bandwidth of each crossbar switch. Simulation with VHDL has been performed to verify the functionality of each crossbar system. Synthesis has also been conducted to evaluate delay and area for each crossbar design.
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Chun-YuehHsiao und 蕭鈞悅. „The Integration of Crossflow and Bioimpedance Technique in Rotating Disc Platform Design for Cell Separation“. Thesis, 2017. http://ndltd.ncl.edu.tw/handle/3gwuhw.
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ZHOU, WEI-JUN, und 周威均. „The design and implementation of 4X4 crossbar interconnectioon network board for large scale multiprocessor system-azalea“. Thesis, 1992. http://ndltd.ncl.edu.tw/handle/37377179300800211036.
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(9437825), Oluwatobi O. Busari. „DESIGN AND ANALYSIS OF A STAGED COMBUSTOR FEATURING A PREMIXED TRANSVERSE REACTING FUEL JET INJECTED INTO A VITIATED CONFINED CROSSFLOW“. Thesis, 2021.
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Combustion phenomena are complex in theory and expensive to test, analysis techniquesprovide handles with which we may describe them. Just as simultaneous experimental tech-
niques provide complementary descriptions of flame behavior, one might assume that no
analysis technique for any kind of flame measurement would cover the full description of
the flame. To this end, the search continues for complementary descriptions of engineering
flames that capture enough information for the engine designer to make informed decisions.
The kinds of flames I have encountered are high pressure transverse jet flames issuing into a
vitiated crossflow which is itself generated from combustion of a gaseous fuel and oxidizer.
Summarizing the behavior of these flames has required my understanding of experimen-
tal techniques such as Planar Laser Induced Fluorescence of a reaction intermediate -OH,
Particle Image Velocimetry of a passive tracer in the flame and OH * chemiluminescence of
another reaction intermediate. The analysis tools applied to these measurements must reveal
as much information as is laden in these measurements.
In this work I have also used wavelet optical flow to track flow features in the visualization
of combustion intermediates using OH * chemiluminescence. There are many limitations to
the application of this technique to engineering flames especially due to the interpretation
of the data as a 2-D motion field in 3-D world. The interpretation of such motion fields
as generated by scalar fields is one subject matter discussed in this dissertation. Some
inferences from the topology of the ensuing velocity field has provided insight to the behavior
of reacting turbulent flows which appear attached to an injector in the mean field. It gives
some understanding to the robustness of the attachment mechanism when such flames are
located near walls.