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1
Bond, Steven Winfred. „Through-silicon circuit optical communications links“. Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15390.
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2
Tang, Wei 1976. „High-speed parallel optical receivers“. Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.
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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing.
A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion.
Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.
3
Bhavnagarwala, Azeez Jenúddin. „Voltage scaling constraints for static CMOS logic and memory cirucits“. Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
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4
Ng, Chik-wai, und 吳植偉. „Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits“. Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.
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5
Mony, Madeleine. „Reprogrammable optical phase array“. Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103276.
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The evolving needs of network carriers are changing the design of optical networks. In order to reduce cost, latency, and power consumption, electrical switches are being replaced with optical switching fabrics at the core of the networks. An example of such a network is an Agile All-Photonic Network (AAPN).This thesis presents a novel device that was designed to operate as an optical switch within the context of an AAPN network. The device is a Reprogrammable Optical Phase Array (ROPA), and the design consists of applying multiple electric fields of different magnitudes across an electro-optic material in order to create a diffractive optical element. The configuration of the electric fields can change to modify the properties of the diffractive device.
Such a device has a wide range of potential applications, and two different ROPA designs are presented. Both designs are optimized to function as 1xN optical switches. The switches are wavelength tunable and have switching times on the order of microseconds. The ROPA devices consist of two parts: a bulk electro-optic crystal, and a high-voltage CMOS chip for the electrical control of the device. The design, simulation, fabrication and testing of both the electrical and optical components of the devices are presented.
6
Deshpande, Sandeep. „A cost quality model for CMOS IC design“. Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.
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7
Mule, Anthony Victor. „Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat“. Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/9447.
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8
Xiao, Haiqiao. „Design of Radio-Frequency Filters and Oscillators in Deep-Submicron CMOS Technology“. PDXScholar, 2008. https://pdxscholar.library.pdx.edu/open_access_etds/5233.
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Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operating frequency, only parasitic capacitors were used.
Two new active-inductor circuits are derived from this research, labeled allNMOS and all-NMOS-II. The all-NMOS active inductor was used to design high-Q bandpass filters and oscillators, which were fabricated in TSMC’s 0.18-µm digital CMOS process. The highest center frequency measured was 5.7 GHz at 0.20-µm gate length and the maximum repeatably measured Q was 665. 2.4-GHz circuits were also designed and fabricated in 0.40-µm gate length. The all-NMOS-II circuit has superior linearity and signal fidelity, which are robust against process and temperature variations, due to its novel structure. It was used in signal drivers and will be fabricated in commercial products.
Small-signal analysis was conducted for each of the active-inductor, filter and oscillator circuits, and the calculated performance matches those from simulations. The noise performance of the active inductor, active-inductor filter and oscillator was also analyzed and the calculated results agree with simulations. The difference between simulation and measured results is about 10% due to modeling and parasitic extraction error.
The all-NMOS active-inductor circuit was granted a US patent. The US patent for all-NMOS-II circuit is pending. This research generated three conference papers and two journal papers.
9
Blalock, Benjamin Joseph. „A 1-volt CMOS wide dynamic Range operational amplifier“. Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15441.
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10
Gibson, Jr Allen. „Design and simulation of CMOS active mixers“. Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4765.
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This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 micrometer] CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.ID: 030646192; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.E.E.)--University of Central Florida, 2011.; Includes bibliographical references.
M.S.E.E.
Masters
Electrical Engineering and Computing
Engineering and Computer Science
Electrical Engineering
11
Song, Indal. „Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects“. Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4902.
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Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such advantages as low power consumption, high yield that lowers the cost of fabrication, and a higher degree of integration, have not performed well enough to survive in such a noisy environment without sacrificing other important attributes.
In this research, a high-speed CMOS preamplifier was designed and fabricated through TSMC 0.18/spl mu/m mixed-signal non-epi CMOS technology, and a 20/spl mu/m diameter InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a wavelength of 1550/spl mu/m was post-integrated onto the circuit. The circuit has a overall transimpedance gain of 60dB/spl Omega/, and bit-error-rate data and eye-diagram measurement results taken as high as 10Gbit/s are reported in this dissertation.
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Dong, Zhiwei. „Low-power, low-distortion constant transconductance Gm-C filters“. Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/25400.
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13
Kumar, Ajay. „A novel Q tuning technique for high-Q high-frequency IF bandpass filter“. Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15904.
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14
Shin, Eung Seo. „Automated Generation of Round-robin Arbitration and Crossbar Switch Logic“. Diss., Available online, Georgia Institute of Technology, (2003), 2003. http://etd.gatech.edu/theses/available/etd-11232003-150424/.
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15
Amarnath, Avinash. „A Self-Configurable Architecture on an Irregular Reconfigurable Fabric“. PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/634.
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Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.
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Chan, Chi Hang. „A study on comparator and offset calibration techniques in high speed Nyquist ADCs“. Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493284.
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17
Hass, Joanna R. „Structural characterization of epitaxial graphene on silicon carbide“. Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26654.
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Thesis (Ph.D)--Physics, Georgia Institute of Technology, 2009.Committee Co-Chair: Conrad, Edward; Committee Co-Chair: First, Phillip; Committee Member: Carter, Brent; Committee Member: de Heer, Walter; Committee Member: Zangwill, Andrew. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Long, Ethan Schuyler. „The Role of Temperature in Testing Deep Submicron CMOS ASICs“. PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.
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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.
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Vakili-Amini, Babak. „A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers“. Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.
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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
20
Sarivisetti, Gayathri. „Design and Optimization of Components in a 45nm CMOS Phase Locked Loop“. Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.
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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.
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Park, Yunseo. „Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies“. Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7563.
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This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range.
For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.
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Ukirde, Vaishali. „Trapping of hydrogen in Hf-based high κ dielectric thin films for advanced CMOS applications“. Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc5114/.
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In recent years, advanced high κ gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to optimize the performance of electronic device structures. In this dissertation, a systematic study of hydrogen trapping and the role of carbon impurities in various alternate gate dielectric candidates, HfO2/Si, HfxSi1-xO2/Si, HfON/Si and HfON(C)/Si is presented. It has been shown that processing of high κ dielectrics may lead to some crystallization issues. Rutherford backscattering spectroscopy (RBS) for measuring oxygen deficiencies, elastic recoil detection analysis (ERDA) for quantifying hydrogen and nuclear reaction analysis (NRA) for quantifying carbon, X-ray diffraction (XRD) for measuring degree of crystallinity and X-ray photoelectron spectroscopy (XPS) were used to characterize these thin dielectric materials. ERDA data are used to characterize the evolution of hydrogen during annealing in hydrogen ambient in combination with preprocessing in oxygen and nitrogen.
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Liu, Yidong. „CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation“. Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.
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Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (Vsubscript T) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (Vsubscript T]) shift and 25% to electron mobility (mu subscript n]) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation.ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
24
Srirattana, Nuttapong. „High-Efficiency Linear RF Power Amplifiers Development“. Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.
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Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers.
The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept.
The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique.
In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.
25
Wu, Ting. „Design of terabits/s CMOS crossbar switch chip /“. View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WU.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.
26
Jha, Nand Kishore. „Design of a complementary silicon-germanium variable gain amplifier“. Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.
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27
Venkataraman, Sunitha. „Systematic Analysis of the Small-Signal and Broadband Noise Performance of Highly Scaled Silicon-Based Field-Effect Transistors“. Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16232.
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The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory.
This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-signal AC, and broadband noise performance of 0.18 um and 130 nm Si-CMOS devices operating at cryogenic temperatures is presented. The room temperature RF noise model is extended to model the high-frequency noise performance of scaled MOSFETs at temperatures down to 77 K and 10 K. Significant performance enhancement at cryogenic temperatures is demonstrated, indicating the suitability of scaled CMOS technologies for low temperature electronics. The hot-carrier reliability of MOSFETs at cryogenic temperatures is investigated and the worst-case gate voltage stress condition is determined. The degradation due to hot-carrier-induced interface-state creation is identified as the dominant degradation mechanism at room temperature down to 77 K. The effect of high-energy proton radiation on the DC, AC, and RF noise performance of 130 nm CMOS devices is studied. The performance degradation is investigated up to an equivalent total dose of 1 Mrad, which represents the worst case condition for many earth-orbiting and planetary missions.
The geometric scaling of MOSFETs has been augmented by the introduction of novel FET designs, such as the Si/SiGe MODFETs. A comprehensive characterization and modeling of the small-signal and high-frequency noise performance of highly scaled Si/SiGe n-MODFETs is presented. The effect of gate shot noise is incorporated in the broadband noise model. SiGe MODFETs offer the potential for high-speed and low-voltage operation at high frequencies and hence are attractive devices for future RF and mixed-signal applications.
This work advances the state-of-the-art in the understanding and analysis of the RF performance of highly scaled Si-CMOS devices as well as emerging technologies, such as Si/SiGe MODFETs. The key contribution of this dissertation is to provide a robust framework for the systematic characterization, analysis and modeling of the small-signal and RF noise performance of scaled Si-MOSFETs and Si/SiGe MODFETs both for mainstream and extreme-environment applications.
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Song, Shiunn Luen Steven 1960. „Characterization and design of the complementary JFET LAMBDA-DIODE SRAM“. Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276882.
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The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.
29
Westerhoff, Kevin M. (Kevin Matthew) 1978. „Construction based design“. Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/84827.
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Xie, Xiaoling. „Communications in construction design“. Thesis, Loughborough University, 2002. https://dspace.lboro.ac.uk/2134/7571.
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Construction design has become an increasingly complex synthesis activity for which effective solutions depend upon co-operative participation by a number of people. Thus communication, including the integration of specialised knowledge and negotiation of differences between team members, is a vital process for collaborative design. A questionnaire survey was initially conducted to investigate communication issues and problems, which had been highlighted from a review of the literature, in current construction design. The results confirmed that communication among the different construction team members is often difficult although of paramount important to design outcomes. Based on these results, case studies have been carried out to gain further insights into communication issues and problems, and explore why and how they are caused. Through the application of multiple approaches, a model has been developed, which suggests strategies that may help participants communicate more effectively and ultimately improve the quality of construction design outcomes.
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North-Bates, Susan T. „The influence of complementary practices and spirituality on British design, 1930-2005“. Thesis, Sheffield Hallam University, 2007. http://shura.shu.ac.uk/20298/.
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This thesis investigates the nature and role of spiritually-influenced approaches to design in Britain in the period 1930-2005. The role of spiritual factors in design is considered as a complement to the predominance of the Modernist rationalist-functionalist discourse prevalent in much twentieth century design history writing and theories of design. Non-rational and spiritual facets of Modernism in this period are also examined. The influence of 'alternative' lifestyles, the New Age movement, ecology, holism, complementary and alternative medical practices, and spirituality on design is presented as a complementary paradigm to the predominance of Modernism. The origins and development of these influences are explored in relation to design and material culture. In order to reveal a body of relevant exemplars, the particular areas selected for detailed examination are the domestic environment, gardens and landscape design, and the influence of Complementary and Alternative Medicine on the design of therapeutic environments. This material, arising from practices of consumption as well as those of designing, challenges some of the established methods of design history and to deal with this, insights from the academic disciplines of Archaeology and Pagan Studies, relating to Shamanic concepts of the object, are explored as useful adjuncts to Postmodernism and other approaches in theorising complementary and alternative design practices. The research demonstrates that during the period under consideration, what was once considered outlandish has now become part of the mainstream and has affected contemporary design practice, material culture and consumption. The pluralism of contemporary design ideologies and methods presents a complement to, and a transformation of the Modernist hegemony in design practice and writing. This study contributes to a more complete historical picture of British design in the twentieth century and indicates that the predominance of a Modernist interpretation of design and its history is both insufficient and inadequate to understand the rich texture and complexity of the design history of this period.
32
Correll, Jeffrey. „The design and implementation of an 8 bit CMOS microprocessor /“. Online version of thesis, 1992. http://hdl.handle.net/1850/11649.
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Soto, Leticia S. M. Massachusetts Institute of Technology. „Construction design as a process for flow : applying lean principles to construction design“. Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42995.
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Thesis (S.M.)--Massachusetts Institute of Technology, System Design and Management Program, 2007.Includes bibliographical references (p. 108-111).
Delays and cost overruns are the rule rather than the exception in the construction industry. Design changes due to lack of constructability late in the construction phase generating costly ripple effect which create delay and disruption throughout the entire organization, are the largest contributors to the stated rule. In the building construction industry, of increased competitiveness, demand from many companies continued effort to develop new methods and tools, in which the design for quality, cost, construability and reliability play an important role. The planning and management of building design has historically focused upon traditional methods of planning such as Critical Path Method (CPM). Little effort is made to understand the complexities of the design process; instead design managers focus on allocating work packages where the planned output is a set of deliverables. This current design method forces design teams to manage their work on a discipline basis, each working on achieving their deliverable as dictated by the design program with little regard of the relationship with other disciplines and organizations. In addition, because Architect and Engineering firms view design and construction as two separate independent phases of work in project it makes it difficult to verify constructability in a design and create flow in the overall process. The goal of this study is to look at how aligning interests, objectives and practices based on lean fundamentals, during the earliest stages of a project, as a method of improving construction performance.
by Leticia Soto.
S.M.
34
Yuan, Fangfeng. „Construction and characterization of a full-length complementary DNA infectious clone of emerging porcine Senecavirus A“. Thesis, Kansas State University, 2017. http://hdl.handle.net/2097/35511.
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Master of ScienceDepartment of Diagnostic Medicine/Pathobiology
Ying Fang
Seneca Valley Virus (SVV) causes vesicular disease in pigs. Vesicular lesions on the snout and coronary band of hoof mostly resemble lesions caused by Foot-and-Mouth Disease Virus (FMDV), which may lead to the foreign animal disease investigation. In 2015, Brazil experienced major outbreaks of SVV; then in July, sporadic cases of SVV were reported in United States and became a concern in swine industry. A reverse-genetic system serves as a major tool to study pathogenesis of the virus. In our study, a full-length cDNA infectious clone, pKS15-01-Clone, was constructed from an emerging Seneca Valley Virus (SVV; strain KS15-01). To explore the potential use as a viral backbone for expressing marker genes, the enhanced green fluorescent protein (EGFP)-tagged reporter virus (vKS15-01-EGFP) was generated using reverse genetics. Compared to the parental virus, the pKS15-01-Clone derived virus (vKS15-01-Clone) replicated efficiently in vitro and in vivo, and induced similar levels of neutralizing antibody and cytokine responses in infected animals. In contrast, the vKS15-01-EGFP virus showed impaired growth ability and induced lower level of immune response in infected animals. Lesions on the dorsal snout and coronary bands were observed in all pigs infected by parental virus KS15-01, but not in pigs infected with vKS15-01-Clone or vKS15-01-EGFP viruses. These results demonstrated that the infectious clone and EGFP reporter virus will be important tools in further elucidating the SVV pathogenesis and development of control measures.
35
Kwon, Ohsang. „On high performance multiplier design using dynamic CMOS circuits /“. Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.
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36
Li, Xiaoyong. „Low noise design techniques for radio frequency integrated circuits /“. Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.
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37
Kanitkar, Hrishikesh. „Subthreshold circuits : design, implementation and application /“. Online version of thesis, 2009. http://hdl.handle.net/1850/8926.
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38
Sayre, Edward P. „The design, fabrication, and test of a CMOS operational amplifier /“. Online version of thesis, 1990. http://hdl.handle.net/1850/11226.
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39
McMahon, Terry E. (Terry Edwin) 1963. „Design, fabrication and characterization of complementary heterojunction field effect transistors“. Thesis, 1994. http://hdl.handle.net/1957/34635.
Der volle Inhalt der QuelleAnnotation:
Complementary delta-doped AlGaAs/GaAs Heterojunction Field Effect Transistor
(CHFET) devices and circuits were fabricated using MBE and a 2�� non-planar gate
recess process. Several schemes were used in an attempt to improve the performance of
the p-channel HFETs. These included delta-doping, carbon-doping and dipole-doping.
Circuits and individual n- and p- channel devices were fabricated on a stacked delta-doped
complementary structure. The circuits failed to perform due to complications with
adjusting the threshold voltage. However, Individual devices were successfully
characterized, p-channel devices with extrinsic transconductances up to 14 mS/mm, n-channel
devices with extrinsic transconductances up to 120 mS/mm and a unity power
gain bandwidth of 5.5 GHz.Graduation date: 1995
40
Dang, Yen. „Design, fabrication and characterization of a complementary GaAs MODFET structure“. Thesis, 1993. http://hdl.handle.net/1957/35639.
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41
Yoo, Byungwook 1975. „New platforms for electronic devices: n-channel organic field-effect transistors, complementary circuits, and nanowire transistors“. Thesis, 2007. http://hdl.handle.net/2152/3165.
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This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain.text
42
Hui, Henry. „Design of a True-Q Flip Flop“. Thesis, 1994. http://hdl.handle.net/1957/35209.
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A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as
an asynchronous storage element in micropipelines or a part of the synchronizer. It is
capable of double-edge triggering which latches data at both the rising and the trailing
edges. It is also free of the metastability state problem.
Some analog and digital circuits are incorporated with a true double-edge triggered
Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an
acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding
stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the
flip flop will not be received by the next stage if Q is in a metastable state.
The number of transistors used in this implementation of True-Q flip flop is 90. Due
to the overhead of circuit complexity, the time delay from Request to Acknowledge signal
is 6.5ns.Graduation date: 1995
43
Fiez, Theresa S. „Design of CMOS switched-current filters“. Thesis, 1990. http://hdl.handle.net/1957/37183.
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The design and implementation of Switched-Current (SI) ladder filters is
described. SI filters require only a standard digital CMOS process and the power
supply voltage requirement is low. SI circuits also can be potentially operated at
higher frequencies than Switched-Capacitor (SC) filters due to the low-impedance
wideband nodes of the current mirrors. A simple method has been developed to
design SI ladder and biquadratic fllters with maximum dynamic range that leverages
the well-established design methodologies of SC filters. A standard digital 2-micron
n-well CMOS process has been used to implement two high-order ladder filters and
two biquadratic filters. Simulations accurately predict the measured results of the
first integrated SI filters. The area and power dissipation are comparable to the
switched-capacitor technique.
Analysis of the factors that effect dynamic range in SI filters is presented.
The factors that contribute to harmonic distortion in the current-mode circuits are
characterized and the relationships to maximum signal size are established. Using
measurements of the input-referred noise from SI filters, the dynamic range is
obtained.Graduation date: 1991
44
Shrivastava, Manu B. „Comparison and analysis of current-mode logic circuits with differential and static CMOS“. Thesis, 1994. http://hdl.handle.net/1957/36770.
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This thesis describes the analysis and comparison of Folded Source-Coupled
Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential
split-level logic gates. The advantages of FSCL are low switching noise and
high operating speed. The effect of voltage and device scaling on these topologies is
evaluated in terms of average delay, power dissipation at maximum frequency,
power-delay-product and current spike noise. Several two-summand adders are
designed and simulated using MOSIS 1-μm CMOS process parameters and evaluations
are performed in terms of area, delay, noise and power dissipation.Graduation date: 1994
45
„Design of CMOS digital controlled oscillator (DCO)“. 1998. http://library.cuhk.edu.hk/record=b5889586.
Der volle Inhalt der QuelleAnnotation:
by Cheuk-Him, To.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.
Includes bibliographical references.
Abstract also in Chinese.
ACKNOWLEDGMENT --- p.I
ABSTRACT (ENGLISH) --- p.II
ABSTRACT (CHINESE) --- p.III
CONTENTS --- p.IV
TABLE OF FIGURES --- p.VI
Chapter CHAPTER 1 --- INTRODUCTION --- p.1-1
Chapter 1.1 --- Introduction --- p.1-1
Chapter 1.2 --- Different types of DCO --- p.1-2
Chapter 1.2.1 --- Divided by N counter --- p.1-2
Chapter 1.2.2 --- Increment-decrement counter --- p.1-2
Chapter 1.2.3 --- Controlled delay ring oscillator --- p.1-4
Chapter 1.3 --- Problems suffered from these circuits --- p.1-4
Chapter 1.4 --- Characteristics of the proposed circuit --- p.1-5
Chapter CHAPTER 2 --- BACKGROUND THEORY --- p.2-1
Chapter 2.1 --- Ring Oscillator --- p.2-1
Chapter 2.2 --- Differential Pair --- p.2-1
Chapter 2.3 --- Injection Locked Oscillator (ILO) --- p.2-2
Chapter 2.4 --- Digital Controlled Oscillator --- p.2-3
Chapter CHAPTER 3 --- DESIGN --- p.3-1
Chapter 3.1 --- Circuit Description --- p.3-1
Chapter 3.1.1 --- D/A converter --- p.3-2
Chapter 3.1.2 --- Injection Locked Oscillator (ILO) --- p.3-3
Chapter 3.2 --- Design Characteristics --- p.3-5
Chapter 3.2.1 --- D/A converter --- p.3-5
Chapter 3.2.2 --- ILO --- p.3-7
Chapter 3.2.3 --- Physical Design (Layout Drawing) --- p.3-8
Chapter CHAPTER 4 --- RESULTS --- p.4-1
Chapter 4.1 --- Chip1 --- p.4-1
Chapter 4.1.1 --- Simulation --- p.4-3
Chapter 4.1.2 --- Measurement --- p.4-15
Chapter 4.1.3 --- Evaluation --- p.4-23
Chapter 4.2 --- Chip2 --- p.4-25
Chapter 4.2.1 --- Simulation --- p.4-25
Chapter 4.2.2 --- Measurement --- p.4-36
Chapter 4.2.3 --- Evaluation --- p.4-47
Chapter CHAPTER 5 --- CONCLUSION --- p.5-1
REFERENCES: --- p.1
APPENDIX: --- p.1
46
„Design and modelling of CMOS operational amplifiers“. 1998. http://library.cuhk.edu.hk/record=b5889676.
Der volle Inhalt der QuelleAnnotation:
by Chung-Yuk Or.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.
Includes bibliographical references (leaves 95-[98]).
Abstract also in Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Fully Differential CMOS Operational Amplifier Design --- p.4
Chapter 2.1 --- Wide-Swing Current Mirror --- p.5
Chapter 2.2 --- Wide-Swing Biasing Network --- p.8
Chapter 2.3 --- Fully differential folded-cascode operational amplifier --- p.13
Chapter 2.3.1 --- Small-Signal Analysis --- p.16
Chapter 2.4 --- Gain-boost technique --- p.18
Chapter 2.4.1 --- Frequency Response --- p.24
Chapter 2.5 --- Common-Mode Feedback Network --- p.26
Chapter 2.5.1 --- Continuous-Time CMFB Circuit --- p.27
Chapter 2.5.2 --- Discrete-Time CMFB circuit --- p.33
Chapter 2.6 --- Design Flow of the Operational Amplifier --- p.35
Chapter 3 --- Physical Design of the Operational Amplifier --- p.39
Chapter 3.1 --- Layout Level Design --- p.40
Chapter 3.2 --- Layout Techniques --- p.42
Chapter 3.3 --- Input Protection Circuitry --- p.47
Chapter 4 --- Simulation Results --- p.49
Chapter 4.1 --- Simulation of the Operational Amplifier --- p.49
Chapter 4.2 --- Simulation of Auxiliary Amplifiers --- p.57
Chapter 4.3 --- Simulation of the Common-Mode Feedback Circuit --- p.62
Chapter 5 --- Measurement Results --- p.70
Chapter 5.1 --- Transient Response Measurement --- p.70
Chapter 5.2 --- Frequency Response Measurement --- p.74
Chapter 5.3 --- Power Consumption Measurement --- p.78
Chapter 5.4 --- Performance Evaluation --- p.81
Chapter 6 --- Layout Driven Operational Amplifiers Macromodelling --- p.82
Chapter 6.1 --- Motivations --- p.83
Chapter 6.2 --- Methodology --- p.84
Chapter 6.3 --- Macromodelling the operational amplifier --- p.85
Chapter 6.4 --- Simulation Results --- p.88
Chapter 6.5 --- Conclusions --- p.92
Chapter 7 --- Conclusions --- p.93
Bibliography --- p.95
A Layout Diagrams and Chip Micrograph --- p.99
47
Lo, Ivy Iun. „A wideband CMOS low-noise amplifier for UHF applications“. Thesis, 2005. http://hdl.handle.net/10125/20547.
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48
„Low voltage and low power circuit techniques for CMOS RF frequency synthesizer application“. 2013. http://library.cuhk.edu.hk/record=b5549762.
Der volle Inhalt der QuelleAnnotation:
在過去的幾十年中，無線通信已經歷了顯著的發展，並成為日常生活中必不可少的一部分。隨著對可移動便攜式電子設備的需求不斷增加，功耗已经成為射頻前端電路設計的一個最關鍵參數。在便攜式無線消費類電子中，頻率綜合器在收发机设计中提供本地振盪器（LO），它又是一個高功耗的子系統之一。降低頻率綜合器的功耗將會直接影响電池的使用時間。為了驗證進來新型的低功耗技术，本文基於低成本的0.18微米三阱CMOS工藝，設計並實現了三個不同的電路模塊和一個頻率綜合器系統。第一個設計是一個低壓正交壓控振盪器(QVCO)和除肆分頻器的電流復用電路。在沒有損耗電壓餘量的情況下，兩個高頻模塊通過電流復用的方式，從而降低了功耗。測試結果顯示當電源電壓為1.3V ，電流消耗電流為2.7毫安。在2.2 GHz載波附近1MHz頻偏位置上的相位噪聲為 -114 dBc/Hz。第二個設計是應用於SDR的變壓器和電流復用的壓控振盪器/分頻器的電路。該電路通過調整偏置電壓，僅用一個分頻器就可以實現可變分頻比（2，3，…,9）的功能。實驗結果表明，分頻器的輸出頻率範圍從0.58至3.11 GHz，在5.72 GHz載波附近1MHz頻偏位置上的相位噪聲為-112.5 dBc / Hz，電源電壓為1.8V時，電流為4.7mA。第三個設計是應用於UWB的變壓器和電流復用的QVCO / SSBM電路。這個全新的結構電路面積為0.8平方毫米，在1.6V電源電壓下，消耗功耗約為11 mA。測量結果表明，帶外雜散抑制小於43dBc，頻率偏移1MHz位置處的相位噪聲小於-112 dBc/Hz。最後一個設計是應用於 MB-OFDM UWB的頻率綜合器。這個新結構只用了一個電感在不犧牲主要性能的情況下，可以實現小的芯片尺寸和低的功耗。測試結果全部基於UWB的頻段，相位噪聲為-119 dBc/Hz@10 MHz，電源電壓1.2 V，總電流消耗為24.7mA。
Over the past decades, wireless communication has experienced a remarkable development and become an essential part of daily life. With the rapid increasing demand for mobile and portable electronic devices, the power dissipation has become one of the most critical design parameters, especially for RF front-ends. In portable wireless consumer electronics, the RF frequency synthesizer is one of the most power-consuming subsystems, which serves as local oscillator (LO) in transceiver design. Any power saving in frequency synthesizer will directly affect the running time of battery.
To demonstrate recent innovation in low power techniques, three different circuit blocks and one frequency synthesizer have been developed and fabricated in low-cost 0.18μm triple-well CMOS process. The first design is a low-voltage current reused quadrature VCO and divider-by-4 frequency divider circuit. By the novel sharing of transistors between the two high frequency blocks, the power consumption of the overall design can be reduced with little penalty on voltage headroom. Experimental results show a phase noise level of -114 dBc/Hz at 1 MHz offset from 2.2 GHz carrier and consumes 2.7 mA from a 1.3V power supply. The second design is a transformer-based current reused VCO/ILFD circuits for SDR application. By the adoption of bias tuning techniques, variable division ratios (2,3,…,9) can be achieved with a single divider circuit. Experimental results show an output frequency ranging from 0.58 to 3.11 GHz and a phase noise level of -112.5 dBc/Hz at 1 MHz offset from 5.72 GHz carrier, with a consumed current of 4.7 mA from a 1.8V power supply. The third design is a transformer-based current-reused QVCO/SSBM circuit for UWB application. The prototype is the first of its kind, while occupies a core area of 0.8 mm² and consumes roughly 11 mA from 1.6V power supply. Measurement results show that the out-of-band spurious rejection and phase noise at 1 MHz offset are better than 43 dBc and -112 dBc/Hz respectively. The final design is a frequency synthesizer for MB-OFDM UWB application. It uses a single inductor approach and novel system architecture to realize compact die size and low power consumption without sacrificing major performance. Experimental results show a phase noise level of -119 dBc/Hz@10 MHz offset for all UWB bands and consumes 24.7 mA from a 1.2 V power supply.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Li, Wei.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Abstract --- p.i
Acknowledgement --- p.v
Table of Contents --- p.vi
List of Figures --- p.xi
List of Table --- p.xvi
Chapter CHAPTER 1 --- INTRODUCTION --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Outline of Dissertation --- p.3
References --- p.5
Chapter CHAPTER 2 --- A NOVEL LOW-VOLTAGE CURRENT REUSED, QUADRATURE VCO AND DIVIDE-BY-4 FREQUENCY DIVIDER --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.2 --- Oscillation Principle of VCO --- p.9
Chapter 2.3 --- Circuit Implementation --- p.14
Chapter 2.3.1 --- Back-gate Coupled QVCO --- p.14
Chapter 2.3.2 --- Divider-by-4 Frequency Divider --- p.20
Chapter 2.3.3 --- Current Reuse QVCO and Frequency Divider --- p.24
Chapter 2.3.3.1 --- Voltage Headroom --- p.25
Chapter 2.3.3.2 --- Startup Condition --- p.26
Chapter 2.3.3.3 --- Operating Range --- p.27
Chapter 2.3.3.4 --- Phase Noise --- p.28
Chapter 2.3.3.5 --- Transient Response --- p.30
Chapter 2.4 --- Experimental Result --- p.31
Chapter 2.4.1 --- Frequency Tuning Range --- p.32
Chapter 2.4.2 --- Phase Noise --- p.33
Chapter 2.4.3 --- Transient Response --- p.34
Chapter 2.4.4 --- Performance Comparison --- p.34
Chapter 2.5 --- Summary --- p.36
Reference --- p.36
Chapter CHAPTER 3 --- A TRANSFORMER BASED CURRENT REUSED VCO/ILFD CIRCUIT WITH VARIABLE DIVIDING RATIOS --- p.41
Chapter 3.1 --- Introduction --- p.41
Chapter 3.2 --- Transformer Design --- p.43
Chapter 3.2.1 --- Ideal Transformer --- p.43
Chapter 3.2.2 --- Transformer Tank --- p.45
Chapter 3.3 --- Design of Current Reused VCO/ILFD --- p.49
Chapter 3.3.1 --- Transformer Implement --- p.50
Chapter 3.3.2 --- VCO Implement --- p.52
Chapter 3.3.3 --- ILFD Implement --- p.54
Chapter 3.4 --- Experiment Results --- p.60
Chapter 3.4.1 --- Phase Noise --- p.61
Chapter 3.4.2 --- Frequency Tuning Range --- p.62
Chapter 3.4.3 --- Transient Response --- p.64
Chapter 3.4.4 --- Performance Comparison --- p.65
Chapter 3.5 --- Summary --- p.66
Reference --- p.66
Chapter CHAPTER --- 4 CURRENT REUSED QVCO/SSBM CIRCUIT FOR MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.70
Chapter 4.1 --- Introduction --- p.70
Chapter 4.2 --- Proposed solution for UWB frequency synthesizer --- p.72
Chapter 4.3 --- Bimodal Oscillation Phenomenon --- p.74
Chapter 4.4 --- Design of Current Reused QVCO/SSBM Circuit --- p.81
Chapter 4.4.1 --- Transformer Implementation --- p.82
Chapter 4.4.2 --- QVCO Implementation --- p.85
Chapter 4.4.3 --- SSBM Implementation --- p.88
Chapter 4.5 --- Experimental Results --- p.89
Chapter 4.5.1 --- Phase Noise --- p.91
Chapter 4.5.2 --- Spur Suppression --- p.92
Chapter 4.5.3 --- Performance Comparison --- p.93
Chapter 4.6 --- Summary --- p.94
Reference --- p.95
Chapter CHAPTER 5 --- A SINGLE INDUCTOR APPROACH TO THE DESIGN OF LOW-VOLTAGE MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.98
Chapter 5.1 --- Introduction --- p.98
Chapter 5.2 --- Frequency Synthesizer Background --- p.101
Chapter 5.2.1 --- General Consideration --- p.101
Chapter 5.2.1.1 --- Frequency Requirement --- p.102
Chapter 5.2.1.2 --- Phase Noise --- p.103
Chapter 5.2.1.3 --- Spurious Tones --- p.104
Chapter 5.2.1.4 --- Switching Time --- p.105
Chapter 5.2.2 --- Overview of MB-OFDM UWB Frequency Synthesizer --- p.105
Chapter 5.3 --- Frequency Synthesizer System Design --- p.109
Chapter 5.3.1 --- Proposed Frequency synthesizer Architecture --- p.109
Chapter 5.3.2 --- Stability Analysis --- p.111
Chapter 5.3.3 --- Phase Noise Contribution --- p.115
Chapter 5.4 --- Circuit Implementation --- p.121
Chapter 5.4.1 --- Current Reused Multiplier/SSBM --- p.121
Chapter 5.4.2 --- 12-Phase Cross-coupled Ring VCO --- p.128
Chapter 5.4.3 --- Regenerative Frequency Divider --- p.131
Chapter 5.4.4 --- Tri-mode Phase Calibration Buffer --- p.132
Chapter 5.4.5 --- Phase-Frequency Detector(PFD) --- p.134
Chapter 5.4.6 --- Charge Pump --- p.135
Chapter 5.4.7 --- CML Divider --- p.136
Chapter 5.5 --- Experimental Result --- p.137
Chapter 5.5.1 --- Frequency Tuning Range --- p.139
Chapter 5.5.2 --- Phase Noise --- p.140
Chapter 5.5.3 --- Spur Suppression --- p.141
Chapter 5.5.4 --- Performance Comparison --- p.142
Chapter 5.6 --- Summary --- p.143
Reference --- p.143
Chapter CHAPTER 6 --- CONCLUSIONS AND FUTURE WORKS --- p.147
Chapter 6.1 --- Conclusions --- p.147
Chapter 6.2 --- Future Works --- p.149
List of Publication --- p.150
49
„CMOS dual-modulus prescaler design for RF frequency synthesizer applications“. 2005. http://library.cuhk.edu.hk/record=b5892418.
Der volle Inhalt der QuelleAnnotation:
Ng Chong Chon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.
Includes bibliographical references (leaves 100-103).
Abstract in English and Chinese.
摘要 --- p.iii
Acknowledgments --- p.iv
Contents --- p.vi
List of Figures --- p.ix
List of Tables --- p.xii
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Thesis Organization --- p.4
Chapter Chapter 2 --- DMP Architecture --- p.6
Chapter 2.1 --- Conventional DMP --- p.6
Chapter 2.1.1 --- Operating Principle --- p.7
Chapter 2.1.2 --- Disadvantages --- p.10
Chapter 2.2 --- Pre-processing Clock Architecture --- p.10
Chapter 2.2.1 --- Operating Principle --- p.11
Chapter 2.2.2 --- Advantages and Disadvantages --- p.12
Chapter 2.3 --- Phase-switching Architecture --- p.13
Chapter 2.3.1 --- Operating Principle --- p.13
Chapter 2.3.2 --- Advantages and Disadvantages --- p.14
Chapter 2.4 --- Summary --- p.15
Chapter Chapter 3 --- Full-Speed Divider Design --- p.16
Chapter 3.1 --- Introduction --- p.16
Chapter 3.2 --- Working Principle --- p.16
Chapter 3.3 --- Design Issues --- p.18
Chapter 3.4 --- Device Sizing --- p.19
Chapter 3.5 --- Layout Considerations --- p.20
Chapter 3.6 --- Input Sensitivity --- p.22
Chapter 3.7 --- Modeling --- p.24
Chapter 3.8 --- Review on Different Divider Designs --- p.28
Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28
Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30
Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32
Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34
Chapter 3.9 --- Summary --- p.42
Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43
Chapter 4.1 --- Introduction --- p.43
Chapter 4.2 --- Proposed DMP Topology --- p.46
Chapter 4.3 --- Circuit Design and Implementation --- p.49
Chapter 4.4 --- Simulation Results --- p.51
Chapter 4.5 --- Summary --- p.53
Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54
Chapter 5.1 --- Introduction --- p.54
Chapter 5.2 --- Proposed DMP Topology --- p.56
Chapter 5.3 --- Circuit Design and Implementation --- p.59
Chapter 5.3.1 --- Divide-by-4 stage --- p.59
Chapter 5.3.2 --- TSPC dividers --- p.63
Chapter 5.3.3 --- Phase-selection Network --- p.63
Chapter 5.3.4 --- Mode-control Logic --- p.64
Chapter 5.3.5 --- Duty-cycle Transformer --- p.65
Chapter 5.3.6 --- Glitch Problem --- p.66
Chapter 5.3.7 --- Phase-mismatch Problem --- p.70
Chapter 5.4 --- Simulation Results --- p.70
Chapter 5.5 --- Summary --- p.74
Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75
Chapter 6.1 --- Introduction --- p.75
Chapter 6.2 --- Proposed DMP Architecture --- p.75
Chapter 6.3 --- Divide-by-4 Stage --- p.76
Chapter 6.3.1 --- Current-switch Combining --- p.76
Chapter 6.3.2 --- Capacitive Load Reduction --- p.77
Chapter 6.4 --- Simulation Results --- p.81
Chapter 6.5 --- Summary --- p.83
Chapter Chapter 7 --- Experimental Results --- p.84
Chapter 7.1 --- Introduction --- p.84
Chapter 7.2 --- Equipment Setup --- p.84
Chapter 7.3 --- Measurement Results --- p.85
Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85
Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88
Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93
Chapter 7.3 --- Summary --- p.96
Chapter Chapter 8 --- Conclusions and Future Works --- p.98
Chapter 8.1 --- Conclusions --- p.98
Chapter 8.2 --- Future Works --- p.99
References --- p.100
Publications --- p.104
50
„Novel channel materials for Si based MOS devices: Ge, strained Si and hybrid crystal orientations“. Thesis, 2007. http://hdl.handle.net/2152/3107.
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