Auswahl der wissenschaftlichen Literatur zum Thema „Circuits intégrés – Mesures de sécurité“
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Zeitschriftenartikel zum Thema "Circuits intégrés – Mesures de sécurité"
Dufour, Jean-Luc. „Le statut juridique des bénéficiaires participant aux mesures provinciales de développement de l'employabilité et d'aide à l'emploi : la situation actuelle et la situation à venir“. Les Cahiers de droit 37, Nr. 1 (12.04.2005): 175–262. http://dx.doi.org/10.7202/043382ar.
Der volle Inhalt der Quelle-MAROT, Christian. „Avancement des travaux de normalisation IEC47A/WG9 : méthodes de mesures CEM sur circuits intégrés“. Revue de l'Electricité et de l'Electronique -, Nr. 07 (2000): 33. http://dx.doi.org/10.3845/ree.2000.066.
Der volle Inhalt der QuelleTap, H., R. P. Tan, O. Bernal, P.-F. Calmon, C. Rouabhi, C. Capello, P. Bourdeu d'Aguerre, F. Gessinn und M. Respaud. „De la conception à la fabrication de circuits intégrés en technologie CMOS“. J3eA 18 (2019): 1019. http://dx.doi.org/10.1051/j3ea/20191019.
Der volle Inhalt der QuelleDELAUNE, D., C. BIGAILLON, J. L. KOECK und A. MERENS. „Pandémie grippale 2009 dans les armées : l’expérience du biologiste.“ Revue Médecine et Armées, Volume 40, Numéro 5 (01.12.2012): 411–16. http://dx.doi.org/10.17184/eac.6635.
Der volle Inhalt der QuelleMambou, Jean-Romuald, und Hilaire Elenga. „Erosions, Inondations et Mauvais Drainage des Eaux Pluviales à Brazzaville : Quelles Solutions dans le Cadre d’un Réaménagement Durable de la Ville à l’Horizon 2030 ?“ European Scientific Journal, ESJ 19, Nr. 20 (31.07.2023): 205. http://dx.doi.org/10.19044/esj.2023.v19n20p205.
Der volle Inhalt der QuelleDissertationen zum Thema "Circuits intégrés – Mesures de sécurité"
Cioranesco, Jean-Michel. „Nouvelles Contre-Mesures pour la Protection de Circuits Intégrés“. Thesis, Paris 1, 2014. http://www.theses.fr/2014PA010022/document.
Der volle Inhalt der QuelleEmbedded security applications are diverse and at the center of all personal embedded applications. They introduced an obvious need for data confidentiality and security in general. Invasive attacks on hardware have always been part of the industrial scene. The aim of this thesis is to propose new solutions in order to protect embedded circuits against some physical attacks described above. ln a first part of the manuscript, we detail the techniques used to achieve side-channel, invasive attacks and reverse engineering. I could implement several of these attacks during my thesis research, they will be detailed extensively. ln the second part we propose different hardware countermeasures against side-channel attacks. The third part is dedicated to protection strategies against invasive attacks using active shielding and we conclude this work by proposing an innovative cryptographic shield which is faulty and dpa resistant
Germain, Fabien. „Sécurité cryptographique par la conception spécifique de circuits intégrés“. Phd thesis, Ecole Polytechnique X, 2006. http://pastel.archives-ouvertes.fr/pastel-00001858.
Der volle Inhalt der QuelleDumont, Mathieu. „Modélisation de l’injection de faute électromagnétique sur circuits intégrés sécurisés et contre-mesures“. Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS031.
Der volle Inhalt der QuelleThis thesis is devoted to the study of electromagnetic fault injection attack on se-cure integrated circuits. Electrical modeling permits to simulate the coupling between an EM probe injection and the circuit supply and ground grids in order to understand the effect of the EM pulse. This modeling is then applied on a logic circuit simulation with a D flip-flop and its components. The simulation results were used to determine the various faults that could be induced by this attack and to explain their formation. Measurements on a test circuit revealed the appearance of timing and sampling faults and validated ex-perimentally the proposed model. Finally, some countermeasures based on the model are proposed in order to increase the robustness of a circuit against electromagnetic fault in-jection
Hély, David. „Conception en vue du test de circuits sécurisés“. Montpellier 2, 2005. http://www.theses.fr/2005MON20123.
Der volle Inhalt der QuelleDehbaoui, Amine. „Analyse Sécuritaire des Émanations Électromagnétiques des Circuits Intégrés“. Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20020.
Der volle Inhalt der QuelleThe integration of cryptographic primitives in different electronic devices is widely used today incommunications, financial services, government services or PayTV.Foremost among these devices include the smart card. According to a report published in August 2010, IMS Research forecasts that the smart card market will reach 5.8 billion units sold in this year. The vast majority is used in telecommunications (SIM) and banking.The smart card incorporates an integrated circuit which can be a dedicated processor for cryptographic calculations. Therefore, these integrated circuits contain secrets such as secret or private keys used by the symmetric or asymmetric cryptographic algorithms. These keys must remain absolutely confidential to ensure the safety chain.Therefore the robustness of smart cards against attacks is crucial. These attacks can be classifiedinto three main categories: invasive, semi-invasive and non-invasive.Non-invasive attacks can be considered the most dangerous, since this kind of attack can be achieved without any contact with the circuit.Indeed, while using electronic circuits that compose them are subjected to variations in current and voltage. These variations generate an electromagnetic radiation propagating in the vicinity of the circuit.These radiations are correlated with secret information (eg a secret key used for authentication). Several attacks based on these leakages were published by the scientific community.This thesis aims to: (a) understand the different sources of electromagnetic emanations of integrated circuits, and propose a localized near field attack to test the robustness of a cryptographic circuit and (b) propose counter-measures to these attacks
Joaquim, da Rolt Jean. „Testabilité versus Sécurité : Nouvelles attaques par chaîne de scan & contremesures“. Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20168.
Der volle Inhalt der QuelleIn this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks
Vaquié, Bruno. „Contributions à la sécurité des circuits intégrés face aux attaques par canaux auxiliaires“. Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20133/document.
Der volle Inhalt der QuelleSide channel attacks such as power analysis attacks are a threat to the security of integrated circuits.They exploit the physical leakage of circuits during the cryptographic computations to retrieve the secret informations they contain. Many countermeasures, including hardware, have been proposed by the community in order to protect cryptosystems against such attacks. Despite their effectiveness, their major drawback is their significant additional cost in area, speed and consumption. This thesis aims at proposing low cost countermeasures able to reduce the leaks and offering a good compromise between security and costs. First we identify the main sources of leakage of a cryptographic system that integrates an iterative hardware architecture of a symetric algorithm. Then we propose several low cost countermeasures, which aim at reducing this leakage. Finally, we evaluate the robustness of our solutions against side channel attacks
Razafindraibe, Hanitriniaina Mamitiana Alin. „Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés“. Montpellier 2, 2006. http://www.theses.fr/2006MON20117.
Der volle Inhalt der QuelleClavier, Christophe. „De la sécurité physique des crypto-systèmes embarqués“. Versailles-St Quentin en Yvelines, 2007. http://www.theses.fr/2007VERS0028.
Der volle Inhalt der QuelleIn a world full of threats, the development of widespread digital applications has led to the need for a practical device containing cryptographic functions that provide the everyday needs for secure transactions, confidentiality of communications, identification of the subject or authentication for access to a particular service. Among the cryptographic embedded devices ensuring these functionalities, smart cards are certainly the most widely used. Their portability (a wallet may easily contain a dozen) and their ability to protect its data and programs against intruders, make it as the ideal ``bunker'' for key storage and the execution of cryptographic functions during mobile usage requiring a high level of security. Whilst the design of mathematically robust (or even proven secure in some models) cryptographic schemes is an obvious requirement, it is apparently insufficient in the light of the first physical attacks that were published in 1996. Taking advantage of weaknesses related to the basic implementation of security routines, these threats include side-channel analysis which obtains information about the internal state of the process, and the exploitation of induced faults allowing certain cryptanalysis to be performed which otherwise would not have been possible. This thesis presents a series of research works covering the physical security of embedded cryptosystems. Two parts of this document are dedicated to the description of some attacks and to a study of the efficiency of conceivable countermeasures. A third part deals with that particular and still mainly unexplored area which considers the applicability of physical attacks when the cryptographic function is, partly or totally, unknown by the adversary
Acunha, guimarães Leonel. „Techniques de Test Pour la Détection de Chevaux de Troie Matériels en Circuits Intégrés de Systèmes Sécurisés“. Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT080/document.
Der volle Inhalt der QuelleThe world globalization has led the semiconductor industry to outsource design and fabrication phases, making integrated circuits (ICs) potentially more vulnerable to malicious modifications at design or fabrication time: the hardware Trojans (HTs). New efficient testing techniques are thus required to disclose potential slight and stealth HTs, and to ensure trusted devices. This thesis studies possible threats and proposes two new post-silicon testing techniques able to detect HTs implanted after the generation of the IC netlist. The first proposed technique exploits bulk built-in current sensors (BBICS) -- which are originally designed to identify transient faults in ICs -- by using them as testing mechanisms that provide statistically-comparable digital signatures of the devices under test. With only 16 IC samples, the testing technique can detect dopant-level Trojans of zero-area overhead. The second proposition is a non-intrusive technique for detection of gate-level HTs in asynchronous circuits. With this technique, neither additional hardware nor alterations on the original test set-up are required to detect Trojans smaller than 1% of the original circuit. The studies and techniques devised in this thesis contribute to reduce the IC vulnerability to HT, reusing testing mechanisms and keeping security features of original devices
Bücher zum Thema "Circuits intégrés – Mesures de sécurité"
A, Bolmen Richard, Hrsg. Semiconductor safety handbook: Safety and health in the semiconductor industry. Westwood, N.J: Noyes Publications, 1998.
Den vollen Inhalt der Quelle findenRonald, Kitchen, Hrsg. RF and microwave radiation safety handbook. 2. Aufl. Oxford: Newnes, 2001.
Den vollen Inhalt der Quelle findenBolmen, Richard A. Semiconductor Safety Handbook: Safety and Health in the Semiconductor Industry. Elsevier Science & Technology Books, 1998.
Den vollen Inhalt der Quelle findenBolmen, Richard A. Semiconductor Safety Handbook: Safety and Health in the Semiconductor Industry (Semiconductor Safety Series). 2. Aufl. Noyes Publications, 1998.
Den vollen Inhalt der Quelle findenWinburn. Practical Laser Safety. Taylor & Francis Group, 2017.
Den vollen Inhalt der Quelle findenWinburn. Practical Laser Safety. Taylor & Francis Group, 2017.
Den vollen Inhalt der Quelle findenWinburn. Practical Laser Safety. Taylor & Francis Group, 2019.
Den vollen Inhalt der Quelle findenHardware Security: Design, Threats, and Safeguards. Taylor & Francis Group, 2014.
Den vollen Inhalt der Quelle findenHardware Security. Taylor & Francis Group, 2014.
Den vollen Inhalt der Quelle findenVLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects. Institution of Engineering & Technology, 2019.
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