Zeitschriftenartikel: „Binary multiplier“

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Madenda, Sarifuddin, Suryadi Harmanto und Astie Darmayantie. „New Concept of Universal Binary Multiplication and Its Implementation on FPGA“. Journal of Southwest Jiaotong University 56, Nr. 3 (30.06.2021): 124–39. http://dx.doi.org/10.35741/issn.0258-2724.56.3.11.

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This paper proposes the new improvements of signed binary multiplication equation, signed multiplier, and universal multiplier. The proposed multipliers have low complexity algorithms and are easy to implement into software and hardware. Both signed, and universal multipliers are embedded into FPGA by optimizing the use of LUTs (6-LUT and 5-LUT), carry chain Carry4, and fast carry logics: MUXCYs and XORCYs.Each one is implemented as a serial-parallel multiplier and parallel multiplier. The signed multiplier executes four types of multiplication, i.e., between two operands that each one can be a signed positive (SPN) or signed negative numbers (SNN). The universal multiplier can handle all (nine) types of multiplication, where each operand can be as unsigned(USN), signed positive, and signed negative numbers. For 8x8 bits, signed serial-parallel and signed parallel multipliers occupy19 LUTs and 58 LUTs with a logic time delay of 0.769 ns and 3.600 ns. Besides, for 8x8 bits, serial-parallel and parallel universal multipliers inhabit 21 LUTs and 60 LUTs with a logic time delay of 0.831ns and 3.677 ns, successively.

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Kalimoldayev, M., S. Tynymbayev, M. Ibraimov, M. Magzom, Y. Kozhagulov und T. Namazbayev. „PIPELINE MULTIPLIER OF POLYNOMIALS MODULO WITH ANALYSIS OF HIGH-ORDER BITS OF THE MULTIPLIER“. BULLETIN 386, Nr. 4 (15.08.2020): 13–20. http://dx.doi.org/10.32014/2020.2518-1467.98.

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Among public-key cryptosystems, cryptosystems built on the basis of a polynomial system of residual classes are special. Because in these systems, arithmetic operations are performed at high speed. There are many algorithms for encrypting and decrypting data presented in the form of polynomials. The paper considers data encryption based on the multiplication of polynomials modulo irreducible polynomials. In such a multiplier, the binary image of a multiply polynomial can serve as a fragment of encrypted text. The binary image of the multiplier polynomial is the secret key and the binary representation of the irreducible polynomial is the module. Existing sequential polynomial multipliers and single-cycle matrix polynomial multipliers modulo do not provide the speed required by the encryption block. The paper considers the possibility of multiplying polynomials modulo on a Pipeline in which architectural techniques are laid in order to increase computing performance. In the conclusion of the work, the time gain of the multiplication modulo is shown by the example of the multiplication of five triples of polynomials. Verilog language was used to describe the scheme of the Pipeline multiplier. Used FPGA Artix-7 from Xilinx companies. The developed Pipeline multiplier can be used for cryptosystems based on a polynomial system of residual classes, which can be implemented in hardware or software.

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Shetty, P. Akshatha, und Dr Kiran V. „Area Efficient Modified Array Multiplier“. Journal of University of Shanghai for Science and Technology 23, Nr. 09 (09.09.2021): 288–91. http://dx.doi.org/10.51201/jusst/21/09531.

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Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

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Arechabala, J., E. I. Boemo, J. Meneses, F. Moreno und C. Lopez Barrio. „Full systolic binary multiplier“. IEE Proceedings G Circuits, Devices and Systems 139, Nr. 2 (1992): 188. http://dx.doi.org/10.1049/ip-g-2.1992.0032.

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Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar und V. S. Kanchana Bhaaskaran. „Low Power, High Speed and Area Efficient Binary Count Multiplier“. Journal of Circuits, Systems and Computers 25, Nr. 04 (02.02.2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

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Alkurwy, Salah. „A novel approach of multiplier design based on BCD decoder“. Indonesian Journal of Electrical Engineering and Computer Science 14, Nr. 1 (01.04.2019): 38. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp38-43.

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A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems

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Rashidi, Bahram, und Mohammad Abedini. „Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems“. Journal of Circuits, Systems and Computers 28, Nr. 09 (August 2019): 1950149. http://dx.doi.org/10.1142/s0218126619501494.

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This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

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Gnanasekaran. „A Fast Serial-Parallel Binary Multiplier“. IEEE Transactions on Computers C-34, Nr. 8 (August 1985): 741–44. http://dx.doi.org/10.1109/tc.1985.1676620.

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Gao, Shuli, Dhamin Al-Khalili, J. M. Pierre Langlois und Noureddine Chabini. „Efficient Realization of BCD Multipliers Using FPGAs“. International Journal of Reconfigurable Computing 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/2410408.

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In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.

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Joe, Hounghun, und Youngmin Kim. „Novel Stochastic Computing for Energy-Efficient Image Processors“. Electronics 8, Nr. 6 (25.06.2019): 720. http://dx.doi.org/10.3390/electronics8060720.

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Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, we propose an efficient yet simple stochastic computation technique for multipliers and adders by exchanging the wires used for their operation. The results demonstrate that the proposed design reduces the relative error in computation compared with the conventional designs and has smaller area compared to conventional designs. Then, a new energy-efficient and high-performance stochastic adder with acceptable error metrics is investigated. The proposed multiplier shows better error metrics than other existing stochastic multipliers, and significantly improves area utilization and power consumption compared to the exact binary multiplier. Finally, we apply the proposed stochastic architecture to an edge detection algorithm and achieve a significant reduction in area utilization (64%) and power consumption (96%). It is therefore demonstrated that the proposed stochastic architecture is suitable for energy-efficient hardware designs.

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Abdul-Hadi, Alaa Mohammed, Yousraa Abdul-sahib Saif-aldeen und Firas Ghanim Tawfeeq. „Performance Evaluation of Scalar Multiplication in Elliptic Curve Cryptography Implementation using Different Multipliers Over Binary Field GF (2233)“. Journal of Engineering 26, Nr. 9 (01.09.2020): 45–64. http://dx.doi.org/10.31026/j.eng.2020.09.04.

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This paper presents a point multiplication processor over the binary field GF (2233) with internal registers integrated within the point-addition architecture to enhance the Performance Index (PI) of scalar multiplication. The proposed design uses one of two types of finite field multipliers, either the Montgomery multiplier or the interleaved multiplier supported by the additional layer of internal registers. Lopez Dahab coordinates are used for the computation of point multiplication on Koblitz Curve (K-233bit). In contrast, the metric used for comparison of the implementations of the design on different types of FPGA platforms is the Performance Index. The first approach attains a performance index of approximately 0.217610202 when its realization is over Virtex-6 (6vlx130tff1156-3). It uses an interleaved multiplier with 3077 register slices, 4064 lookup tables (LUTs), 2837 flip-flops (FFs) at a maximum frequency of 221.6Mhz. This makes it more suitable for high-frequency applications. The second approach, which uses the Montgomery multiplier, produces a PI of approximately 0.2228157 when its implementation is on Virtex-4 (6vlx130tff1156-3). This approach utilizes 3543 slices, 2985 LUTs, 3691 FFs at a maximum frequency of 190.47MHz. Thus, it is found that the implementation of the second approach on Virtex-4 is more suitable for applications with a low frequency of about 86.4Mhz and a total number of slices of about 12305.

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Vozna, Natalia, Yaroslav Nykolaychuk und Alina Davletova. „Multi-bit structure improvement methods for multiplier devices of matrix type“. Physico-mathematical modelling and informational technologies, Nr. 32 (07.07.2021): 80–85. http://dx.doi.org/10.15407/fmmit2021.32.080.

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The article proposes methods for improving the structures of matrix multipliers of multi-digit numbers. Advanced single-bit total adders with paraphrase switched inputs and paraphrase outputs are used, intended as components of high-speed matrix multipliers. Based on the use of such single-bit adders, the structures of matrix multipliers are proposed, characterized by 2 times increased speed, 5 times reduced structural complexity compared to known multipliers based on classical single-bit adders. Optimization of structures of multi-bit matrix multipliers is offered. Comparative estimates of structural and temporal complexities of their circuit implementations depending on the bit size of multiplied binary numbers are given. The use of optimized circuit solutions of matrix multipliers can significantly improve the system characteristics of complex computing devices with many such components in the crystals of microelectronic technologies.

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Lin, Rong. „A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits“. VLSI Design 12, Nr. 3 (01.01.2001): 377–90. http://dx.doi.org/10.1155/2001/97598.

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A highly regular parallel multiplier architecture along with the novel low-power, high-performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8-b small parallel multipliers, then, by small parallel counters in each of the remaining three stages. A family of shift switch parallel counters, including non-binary (6, 3)∗ and complementary (k, 2) for 2 ≤ k ≤ 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non-binary logic operates 4-bit state signals (representing integers ranging from (0 to 3), where no more than half of the signal bits are subject to value-change at any logic stage. This and others including minimum transistor counts, fewer inverters, and low-leakage logic structure, significantly reduce circuit power dissipation.

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Hänninen, Ismo, und Jarmo Takala. „Binary multipliers on quantum-dot cellular automata“. Facta universitatis - series: Electronics and Energetics 20, Nr. 3 (2007): 541–60. http://dx.doi.org/10.2298/fuee0703541h.

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This article describes the design of ultra-low-power multipliers on quantum dot cellular automata (QCA) nanotechnology, promising very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct structures without the earlier noise problems, verified by the QCA Designer coherence vector simulation. Our results show that the wiring overhead of the arithmetic circuits grows quadratically with the operand word length, and our pipelined array multiplier has linearly better performance-area efficiency than the previously proposed serial-parallel structure. Power analysis at the fundamental Landauer's limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the limits for the clock rates on molecular QCA are much lower, than the switching speeds of the technology.

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Saha, Aloke, Rahul Pal und Jayanta Ghosh. „Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication“. Micro and Nanosystems 12, Nr. 3 (01.12.2020): 149–58. http://dx.doi.org/10.2174/1876402911666190916155445.

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Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation. Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.

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Al-Khaleel, Osama, Zakaria Al-Qudah, Mohammad Al-Khaleel, Raed Bani-Hani, Christos Papachristou und Francis Wolff. „Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication“. Journal of Circuits, Systems and Computers 24, Nr. 02 (27.11.2014): 1550019. http://dx.doi.org/10.1142/s021812661550019x.

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This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.

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Perisic, D. M., A. C. Zoric und Z. Gavric. „A Frequency Multiplier Based on Time Recursive Processing“. Engineering, Technology & Applied Science Research 7, Nr. 6 (18.12.2017): 2104–8. http://dx.doi.org/10.48084/etasr.1499.

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This paper describes a digital frequency multiplier for a pulse rate. The multiplier is based on the recursive processing of the input and output periods and their time differences. Special emphasis is devoted to the techniques which provide the development of multipliers based on this principle. The circuit is defined by two system parameters. One is the ratio of two clock frequencies and the other is a division factor of a binary counter. The realization of the circuit is described. The region of the system parameters for the stable circuit is presented. The different aspects of applications and limitations in realization of the circuit are considered. All mathematical analyses are made using a Z transform approach. It is shown that the circuit can be also used in tracking and prediction applications. Computer simulations are performed to prove the correctness of the math and the whole approach.

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Baesler, Malte, Sven-Ole Voigt und Thomas Teufel. „A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA“. International Journal of Reconfigurable Computing 2010 (2010): 1–13. http://dx.doi.org/10.1155/2010/357839.

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Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754-2008decimal64data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate scalar product unit's latency even by a factor of five.

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Aaron D’costa, Mr, Dr Abdul Razak und Dr Shazia Hasan. „Analysis and comparison of fast multiplier circuits based on different parameters“. International Journal of Engineering & Technology 7, Nr. 3 (26.06.2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.

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Andreev, Boris D., Edward L. Titlebaum und Eby G. Friedman. „Complex ±1 Multiplier Based on Signed-Binary Transformations“. Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 38, Nr. 1 (August 2004): 13–24. http://dx.doi.org/10.1023/b:vlsi.0000028530.88948.36.

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Wei, Shugang, und Kensuke Shimizu. „Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits“. Journal of Circuits, Systems and Computers 12, Nr. 01 (Februar 2003): 41–53. http://dx.doi.org/10.1142/s0218126603000842.

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This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2p ± 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to log 2 p and an n-bit binary number is converted into a p-digit SD residue number, n ≫ p, in a time proportional to log 2(n/p). By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.

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ZHANG, MINGDA, und SHUGANG WEI. „HIGH-SPEED MODULAR MULTIPLIERS BASED ON A NEW BINARY SIGNED-DIGIT ADDER TREE STRUCTURE“. Journal of Circuits, Systems and Computers 22, Nr. 06 (Juli 2013): 1350043. http://dx.doi.org/10.1142/s0218126613500436.

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Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number adders where m = 2n + μ(μ = ±1, 0). To simplify the residue SD adder, new addition rules are used for generating the intermediate sum and carry with an 1-bit binary encoded number representation. By using the new encoding method, the proposed residue addition requires less hardware and shorter delay time than previous one. A modulo m multiplier can be implemented by a binary modulo m adder tree which has a depth of log 2 n. In order to introduce a binary SD adder tree with the new addition rules, two novel modulo m adders have been proposed in this paper. Finally, the evaluation apparently shows that the proposed two kinds of modulo m adders are performed more efficiency by comparing with the modulo SD adder which is mentioned in our previous work, and a new binary SD adder tree structure has been proposed.

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Rodríguez-Villegas, E., M. J. Avedillo, J. M. Quintana, G. Huertas und A. Rueda. „νMOS-based Sorter for Arithmetic Applications“. VLSI Design 11, Nr. 2 (01.01.2000): 129–36. http://dx.doi.org/10.1155/2000/57240.

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The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8 × 8)-multiplier and a (15, 4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation.

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Deokate, Rajesh. „A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics“. International Journal for Research in Applied Science and Engineering Technology 9, Nr. VI (20.06.2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.

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The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

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Siva Kumar, M., Sanath Kumar Tulasi, N. Srinivasulu, G. S. Krishnam Naidu Yedla, E. Raghuveer und K. Hari Kishore. „Improvement of the efficiency of booth multiplier“. International Journal of Engineering & Technology 7, Nr. 1.5 (31.12.2017): 31. http://dx.doi.org/10.14419/ijet.v7i1.5.9118.

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Objective: To Improve the performance of Booth Multiplier and reduce power consumption.Method: The most essential form of multiplication consists of framing the result of two unsigned (positive) binary numbers.Finding: Booth Multiplier consists of pre-defined table. According to this algorithm, multiplication of two numbers x and y (x*y) is same as multiplication of y and x (y*x). At times this rule fails due to which we modify the logic by converting the decimal number in to 4 bit binary number and appending (n-2) zeros at most significant bit and one zero at least significant bit.Improvement: By using this method we can get accurate results in multiplication by multiplying like (x*y) and (y*x).

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Sethi, Kabiraj, und Rutuparna Panda. „Multiplier less high-speed squaring circuit for binary numbers“. International Journal of Electronics 102, Nr. 3 (28.03.2014): 433–43. http://dx.doi.org/10.1080/00207217.2014.897381.

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Barik, Ranjan Kumar, Manoranjan Pradhan und Rutuparna Panda. „Time efficient signed Vedic multiplier using redundant binary representation“. Journal of Engineering 2017, Nr. 3 (01.03.2017): 60–68. http://dx.doi.org/10.1049/joe.2016.0376.

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28

AMIN, ALAAELDIN. „GENERALIZED ALGORITHMS FOR BINARY MODULO MULTIPLICATION AND MULTIPLICATION-DIVISION“. Journal of Circuits, Systems and Computers 19, Nr. 08 (Dezember 2010): 1797–815. http://dx.doi.org/10.1142/s0218126610007134.

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This paper, describes novel algorithms and circuitry for binary modulo-multiplication and combined multiplication-division. Unlike the commonly used Montgomery modular multiplier, no domain mapping is needed for the input operands or the output result. Further, the new algorithms work for both even and odd moduli. The combined multiplication-division algorithm produces the quotient as well as the remainder thus allowing the implementation of simple multiplier-dividers. The proposed algorithm uses left shift-based multiplication while maintaining the size of the intermediate running product contained by interleaving reduction and multiplication operations. Reduction is determined by examining only the two most significant bits of the running product if Carry-Propagate adders are used or the 3 most significant bits if Carry-Save Adders are used. Hardware implementations of the proposed algorithms show area and delay figures comparable to those of Montgomery.

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29

Kumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi und K. Hari Kishore. „Bit wise and delay of vedic multiplier“. International Journal of Engineering & Technology 7, Nr. 1.5 (31.12.2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.

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The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

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Vadlamani, Sri Krishna, Tianyao Patrick Xiao und Eli Yablonovitch. „Physics successfully implements Lagrange multiplier optimization“. Proceedings of the National Academy of Sciences 117, Nr. 43 (12.10.2020): 26639–50. http://dx.doi.org/10.1073/pnas.2015192117.

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Optimization is a major part of human effort. While being mathematical, optimization is also built into physics. For example, physics has the Principle of Least Action; the Principle of Minimum Power Dissipation, also called Minimum Entropy Generation; and the Variational Principle. Physics also has Physical Annealing, which, of course, preceded computational Simulated Annealing. Physics has the Adiabatic Principle, which, in its quantum form, is called Quantum Annealing. Thus, physical machines can solve the mathematical problem of optimization, including constraints. Binary constraints can be built into the physical optimization. In that case, the machines are digital in the same sense that a flip–flop is digital. A wide variety of machines have had recent success at optimizing the Ising magnetic energy. We demonstrate in this paper that almost all those machines perform optimization according to the Principle of Minimum Power Dissipation as put forth by Onsager. Further, we show that this optimization is in fact equivalent to Lagrange multiplier optimization for constrained problems. We find that the physical gain coefficients that drive those systems actually play the role of the corresponding Lagrange multipliers.

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Jain, Sonal, und Monika Kapoor. „CMOS Layout for Low Power Four Bit Adiabatic Binary Multiplier“. International Journal of Computer Applications 83, Nr. 8 (18.12.2013): 7–10. http://dx.doi.org/10.5120/14466-2749.

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32

Mahmoud, Mervat M. A., Dalia A. El-Dib und Hossam A. H. Fahmy. „Low energy pipelined Dual Base (decimal/binary) Multiplier, DBM, design“. Microelectronics Journal 65 (Juli 2017): 11–20. http://dx.doi.org/10.1016/j.mejo.2017.05.004.

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33

Harata, Y., Y. Nakamura, H. Nagase, M. Takigawa und N. Takagi. „A high-speed multiplier using a redundant binary adder tree“. IEEE Journal of Solid-State Circuits 22, Nr. 1 (Februar 1987): 28–34. http://dx.doi.org/10.1109/jssc.1987.1052667.

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34

Moniem, Tamer A. „Parallel-shift register and binary multiplier using optical hardware components“. Optical Engineering 47, Nr. 3 (01.03.2008): 035201. http://dx.doi.org/10.1117/1.2898632.

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35

Kyung-Wook Shin, Bang-Sup Song und K. Bacrania. „A 200-MHz complex number multiplier using redundant binary arithmetic“. IEEE Journal of Solid-State Circuits 33, Nr. 6 (Juni 1998): 904–9. http://dx.doi.org/10.1109/4.678655.

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36

Bajard, Jean-Claude, Christophe Negre und Thomas Plantard. „Subquadratic Space Complexity Binary Field Multiplier Using Double Polynomial Representation“. IEEE Transactions on Computers 59, Nr. 12 (Dezember 2010): 1585–97. http://dx.doi.org/10.1109/tc.2010.141.

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37

NIEZNAŃSKI, JANUSZ. „Correspondence between Walsh functions and binary rate multiplier pulse trains“. International Journal of Electronics 74, Nr. 1 (Januar 1993): 47–50. http://dx.doi.org/10.1080/00207219308925811.

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38

Huang, Xiaoping, Belle W. Y. Wei, Honglu Chen und Yuhai H. Mao. „High-performance VLSI multiplier with a new redundant binary coding“. Journal of VLSI signal processing systems for signal, image and video technology 3, Nr. 4 (Oktober 1991): 283–91. http://dx.doi.org/10.1007/bf00936901.

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39

Shetty, Mamtha. „Design of BPSK Modulator Using VHDL“. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, Nr. 12 (23.10.2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyzed using VHDL. Designed modulators using VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) was realized on high speed FPGA (Field Program Programmable Gate Array). Because for used modulation technique data rate transfer is fairly important in wireless communication systems. The highest speed data rate transfer can be realized using fiber optic cables. In addition, BER (Bit Error Rate) of BASK and BPSK modulator was compared using MATLAB simulation program. Binary data rate is same for BPSK and BASK. BPSK and BASK modulations were designed on FPGA using VHDL hardware description language.

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Gan, Hongping, Song Xiao und Feng Liu. „Chaotic Binary Sensing Matrices“. International Journal of Bifurcation and Chaos 29, Nr. 09 (August 2019): 1950121. http://dx.doi.org/10.1142/s0218127419501219.

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As an emerging field for sampling paradigms, compressive sensing (CS) can sample and represent signals at a sub-Shannon–Nyquist rate. To realize CS from theory to practice, the random sensing matrices must be substituted by faster measurement operators that correspond to feasible hardware architectures. In recent years, binary matrices have attracted much research interest because of their multiplier-less and faster data acquisition. In this work, we aim to pinpoint the potential of chaotic binary sequences for constructing high-efficiency sensing implementations. In particular, the proposed chaotic binary sensing matrices are verified to meet near-optimal theoretical guarantees in terms of both the restricted isometry condition and coherence analysis. Simulation results illustrate that the proposed chaotic constructions have considerable sampling efficiency comparable to that of the random counterparts. Our framework encompasses many families of binary sensing architectures, including those formed from Logistic, Chebyshev, and Bernoulli binary chaotic sequences. With many chaotic binary sensing architectures, we can then more easily apply CS paradigm to various fields.

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Tomar, Geetam Singh, und Marcus Lloyde George. „Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization“. Wireless Personal Communications 98, Nr. 4 (31.10.2017): 3549–61. http://dx.doi.org/10.1007/s11277-017-5028-z.

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42

Saha, Amrita, Manideepa Mukherjee, Debanjana Datta, Sangita Saha und Amitabha Sinha. „Performance analysis of a FPGA based novel binary and DBNS multiplier“. ACM SIGARCH Computer Architecture News 41, Nr. 2 (29.05.2013): 9–16. http://dx.doi.org/10.1145/2490302.2490305.

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43

Nakata, Shunji, Takakuni Douseki, Yuichi Kado und Junzo Yamada. „A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit“. Japanese Journal of Applied Physics 39, Part 1, No. 4B (30.04.2000): 2305–11. http://dx.doi.org/10.1143/jjap.39.2305.

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44

Farkas, Z. D. „Binary Peak Power Multiplier and its Application to Linear Accelerator Design“. IEEE Transactions on Microwave Theory and Techniques 34, Nr. 10 (Oktober 1986): 1036–43. http://dx.doi.org/10.1109/tmtt.1986.1133493.

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45

Balakrishnan, W., und N. Burgess. „Very-high-speed VLSI 2s-complement multiplier using signed binary digits“. IEE Proceedings E Computers and Digital Techniques 139, Nr. 1 (1992): 29. http://dx.doi.org/10.1049/ip-e.1992.0005.

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46

Jain, Sonal, und Prof Monika Kapoor. „Design and Analysis of CMOS and Adiabatic 4-Bit Binary Multiplier“. International Journal of Engineering Trends and Technology 7, Nr. 2 (25.01.2014): 71–74. http://dx.doi.org/10.14445/22315381/ijett-v7p210.

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47

Kumar, Ravi. „Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates“. IOSR Journal of Electronics and Communication Engineering 12, Nr. 01 (März 2017): 40–42. http://dx.doi.org/10.9790/2834-1201034042.

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48

Tomar, Geetam Singh, Marcus Llyode George und Abhineet Singh Tomar. „Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication“. IET Circuits, Devices & Systems 15, Nr. 5 (11.03.2021): 455–64. http://dx.doi.org/10.1049/cds2.12041.

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49

Seo, Seog Chung, und Donggeun Kwon. „Highly Efficient SCA-Resistant Binary Field Multiplication on 8-Bit AVR Microcontrollers“. Applied Sciences 10, Nr. 8 (19.04.2020): 2821. http://dx.doi.org/10.3390/app10082821.

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Binary field ( B F ) multiplication is a basic and important operation for widely used crypto algorithms such as the GHASH function of GCM (Galois/Counter Mode) mode and NIST-compliant binary Elliptic Curve Cryptosystems (ECCs). Recently, Seo et al. proposed a novel SCA-resistant binary field multiplication method in the context of GHASH optimization in AES GCM mode on 8-bit AVR microcontrollers (MCUs). They proposed a concept of Dummy XOR operation with a kind of garbage registers and a concept of instruction level atomicity ( I L A ) for resistance against Timing Analysis (TA) and Simple Power Analysis (SPA) and used a Karatsuba Block-Comb multiplication approach for efficiency. Even though their method achieved a large performance improvement compared with previous works, it still has room for improvement on the 8-bit AVR platform. In this paper, we propose a more improved binary field multiplication method on 8-bit AVR MCUs. Our method basically adopts a Dummy XOR technique using a set of garbage registers for TA and SPA security; however, we save the number of used garbage registers from eight to one by using the fact that the number of used garbage registers does not affect TA and SPA security. In addition, we apply a multiplier encoding approach so as to decrease the number of required registers when accessing the multiplier, which enables the use of extended block size in the Karatsuba Block-Comb multiplication technique. Actually, the proposed technique extends the block size from four to eight and the proposed binary field multiplication method can compute a 128-bit B F multiplication with only 3816 clock cycles ( c c ) (resp. 3490 c c ) with (resp. without) the multiplier encoding process, which is almost a 32.8% (resp. 38.5%) improvement compared with 5675 c c of the best previous work. We apply the proposed technique to the GHASH function of the GCM mode with several additional optimization techniques. The proposed GHASH implementation provides improved performance by over 42% compared with the previous best result. The concept of the proposed B F method can be extended to other MCUs, including 16-bit MSP430 MCUs and 32-bit ARM MCUs.

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Rashid, Muhammad, Malik Imran und Asher Sajid. „An Efficient Elliptic-Curve Point Multiplication Architecture for High-Speed Cryptographic Applications“. Electronics 9, Nr. 12 (12.12.2020): 2126. http://dx.doi.org/10.3390/electronics9122126.

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This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over GF(2163) and GF(2571). The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over GF(2163) and GF(2571) on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.

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