Thematische Bibliographien / Binary multiplier

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Auswahl der wissenschaftlichen Literatur zum Thema „Binary multiplier“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 11. Februar 2022

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Zeitschriftenartikel zum Thema "Binary multiplier"

Madenda, Sarifuddin, Suryadi Harmanto und Astie Darmayantie. „New Concept of Universal Binary Multiplication and Its Implementation on FPGA“. Journal of Southwest Jiaotong University 56, Nr. 3 (30.06.2021): 124–39. http://dx.doi.org/10.35741/issn.0258-2724.56.3.11.

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This paper proposes the new improvements of signed binary multiplication equation, signed multiplier, and universal multiplier. The proposed multipliers have low complexity algorithms and are easy to implement into software and hardware. Both signed, and universal multipliers are embedded into FPGA by optimizing the use of LUTs (6-LUT and 5-LUT), carry chain Carry4, and fast carry logics: MUXCYs and XORCYs.Each one is implemented as a serial-parallel multiplier and parallel multiplier. The signed multiplier executes four types of multiplication, i.e., between two operands that each one can be a signed positive (SPN) or signed negative numbers (SNN). The universal multiplier can handle all (nine) types of multiplication, where each operand can be as unsigned(USN), signed positive, and signed negative numbers. For 8x8 bits, signed serial-parallel and signed parallel multipliers occupy19 LUTs and 58 LUTs with a logic time delay of 0.769 ns and 3.600 ns. Besides, for 8x8 bits, serial-parallel and parallel universal multipliers inhabit 21 LUTs and 60 LUTs with a logic time delay of 0.831ns and 3.677 ns, successively.

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Kalimoldayev, M., S. Tynymbayev, M. Ibraimov, M. Magzom, Y. Kozhagulov und T. Namazbayev. „PIPELINE MULTIPLIER OF POLYNOMIALS MODULO WITH ANALYSIS OF HIGH-ORDER BITS OF THE MULTIPLIER“. BULLETIN 386, Nr. 4 (15.08.2020): 13–20. http://dx.doi.org/10.32014/2020.2518-1467.98.

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Among public-key cryptosystems, cryptosystems built on the basis of a polynomial system of residual classes are special. Because in these systems, arithmetic operations are performed at high speed. There are many algorithms for encrypting and decrypting data presented in the form of polynomials. The paper considers data encryption based on the multiplication of polynomials modulo irreducible polynomials. In such a multiplier, the binary image of a multiply polynomial can serve as a fragment of encrypted text. The binary image of the multiplier polynomial is the secret key and the binary representation of the irreducible polynomial is the module. Existing sequential polynomial multipliers and single-cycle matrix polynomial multipliers modulo do not provide the speed required by the encryption block. The paper considers the possibility of multiplying polynomials modulo on a Pipeline in which architectural techniques are laid in order to increase computing performance. In the conclusion of the work, the time gain of the multiplication modulo is shown by the example of the multiplication of five triples of polynomials. Verilog language was used to describe the scheme of the Pipeline multiplier. Used FPGA Artix-7 from Xilinx companies. The developed Pipeline multiplier can be used for cryptosystems based on a polynomial system of residual classes, which can be implemented in hardware or software.

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Shetty, P. Akshatha, und Dr Kiran V. „Area Efficient Modified Array Multiplier“. Journal of University of Shanghai for Science and Technology 23, Nr. 09 (09.09.2021): 288–91. http://dx.doi.org/10.51201/jusst/21/09531.

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Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

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Arechabala, J., E. I. Boemo, J. Meneses, F. Moreno und C. Lopez Barrio. „Full systolic binary multiplier“. IEE Proceedings G Circuits, Devices and Systems 139, Nr. 2 (1992): 188. http://dx.doi.org/10.1049/ip-g-2.1992.0032.

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Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar und V. S. Kanchana Bhaaskaran. „Low Power, High Speed and Area Efficient Binary Count Multiplier“. Journal of Circuits, Systems and Computers 25, Nr. 04 (02.02.2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

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Alkurwy, Salah. „A novel approach of multiplier design based on BCD decoder“. Indonesian Journal of Electrical Engineering and Computer Science 14, Nr. 1 (01.04.2019): 38. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp38-43.

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A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems

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Rashidi, Bahram, und Mohammad Abedini. „Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems“. Journal of Circuits, Systems and Computers 28, Nr. 09 (August 2019): 1950149. http://dx.doi.org/10.1142/s0218126619501494.

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This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

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Gnanasekaran. „A Fast Serial-Parallel Binary Multiplier“. IEEE Transactions on Computers C-34, Nr. 8 (August 1985): 741–44. http://dx.doi.org/10.1109/tc.1985.1676620.

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Gao, Shuli, Dhamin Al-Khalili, J. M. Pierre Langlois und Noureddine Chabini. „Efficient Realization of BCD Multipliers Using FPGAs“. International Journal of Reconfigurable Computing 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/2410408.

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In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.

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Joe, Hounghun, und Youngmin Kim. „Novel Stochastic Computing for Energy-Efficient Image Processors“. Electronics 8, Nr. 6 (25.06.2019): 720. http://dx.doi.org/10.3390/electronics8060720.

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Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, we propose an efficient yet simple stochastic computation technique for multipliers and adders by exchanging the wires used for their operation. The results demonstrate that the proposed design reduces the relative error in computation compared with the conventional designs and has smaller area compared to conventional designs. Then, a new energy-efficient and high-performance stochastic adder with acceptable error metrics is investigated. The proposed multiplier shows better error metrics than other existing stochastic multipliers, and significantly improves area utilization and power consumption compared to the exact binary multiplier. Finally, we apply the proposed stochastic architecture to an edge detection algorithm and achieve a significant reduction in area utilization (64%) and power consumption (96%). It is therefore demonstrated that the proposed stochastic architecture is suitable for energy-efficient hardware designs.

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Dissertationen zum Thema "Binary multiplier"

Hojný, Ondřej. „Evoluční návrh kombinačních obvodů“. Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2021. http://www.nusl.cz/ntk/nusl-442801.

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This diploma thesis deals with the use of Cartesian Genetic Programming (CGP) for combinational circuits design. The work addresses the issue of optimizaion of selected logic circuts, arithmetic adders and multipliers, using Cartesian Genetic Programming. The implementation of the CPG is performed in the Python programming language with the aid of NumPy, Numba and Pandas libraries. The method was tested on selected examples and the results were discussed.

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Rogers, Derek. „Non-binary spread-spectrum multiple-access communications /“. Title page, contents and abstract only, 1995. http://web4.library.adelaide.edu.au/theses/09PH/09phr725.pdf.

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Khalid, Abbas. „Coding for the multiple access binary channel“. Thesis, Lancaster University, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.659445.

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Transmitting the maximum amount of information in minimum possible bandwidth is always desired . Multiple access (MA) communication is often used to achieve this objective. However, the mutual interference among the users handicaps the performance considerably. Addition of redundancy bits for reliable transmission demands more bandwidth. Power line communication (PLC) is considered an attractive candidate to overcome the scarcity of the bandwidth and the associated huge cost. PLC uses power lines as a communication medium which were originally designed for power distribution rather than data transmission and are more harsh compared to other communication media. Frequency-selective fading and inter-symbol-interference (ISI) due to multipaths degrade the bit error rate (BER) substantially. Furthermore, devices connected to the grid introduce impulsive noise on the network. Robust coding and modulation schemes are therefore required to increase the communication reliability. Multi-fold turbo coding is a technique used to improve the error performance of conventional turbo codes. Multi-fold turbo coding increases the randomness of a turbo code by dividing the long information sequence in small subsequences and making use of multiple pseudo random interleavers. Multiple interleavers spread the error burst over several symbols making the errors appear in random. Orthogonal frequency-division multiplex (OFDM) distributes the overall transmitted data in parallel on several orthogonal subcarriers and transforms a frequency-selective fading channel to a group of many flat-fading channels. OFDM possesses a unique property which disperses impulsive noise burst across its several sub-carriers; hence Abstract is able to cope better in an impulsive noise environment. This thesis presents multi-fold turbo coding scheme for MA channels. Specifically, a member of multi-fold family called two-fold has been adopted for the simplest MA channel, the two-user binary adder channel (2-BAC). Each user uses a distinct code to encode the information and the decoder employed uses iterative decoding to decode the received signal. Making use of distinct codes not only allows the correction of errors due to noise but also the correction of errors due to interference between users. Performance of multi-fold turbo codes has been evaluated under Gaussian and power-line conditions. Depedance of performance on number of iterations and blocklength is also presented. A simplified multipath model approach is introduced for complex power-line channels in which the power-line network is divided into number of small segments and each segment is considered as an independent sub-channel. Transfer function of each sub-channel is determined. The transfer function of the whole network is taken as a product of all component transfer functions. The approach has been applied to model two PLC networks that are used as reference channels for the work presented in the thesis. Multi-fold turbo codes can be modified to provide unequal error protection (UEP) levels to the information having different ranks of importance where the most significant information is protected more than the information with least importance. To demonstrate the practicality of the UEP mechanism for the 2-BAC, two test images are decomposed into luminance (£), saturation (8) and hue (if) components. The L component of each image is protected twice than the other two components. The performance of the modified multi-fold turbo codes is compared with the multi-fold turbo codes and conventional turbo codes in terms of pixel error rate (PER.) in Gaussian and power-line environments. The visual effects of PER. for each image are also presented.

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Clarici, Georg. „Multiple quantum well binary-phase modulators : a feasibility study“. Thesis, Heriot-Watt University, 2002. http://hdl.handle.net/10399/458.

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Novak, Gregory S. „Simulated galaxy remnants produced by binary and multiple mergers /“. Diss., Digital Dissertations Database. Restricted to UC campuses, 2008. http://uclibs.org/PID/11984.

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Kubik, Lauren Ashley. „Simultaneously lifting multiple sets in binary knapsack integer programs“. Thesis, Manhattan, Kan. : Kansas State University, 2009. http://hdl.handle.net/2097/1460.

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Crowley, William L. „Lossless compression using binary necklace classes and multiple huffman trees“. Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2001. http://handle.dtic.mil/100.2/ADA397592.

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Benachour, Phillip. „Trellis decoding techniques for the multiple access binary adder channel“. Thesis, Lancaster University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.314240.

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Merkl, Frank J. „Binary image compression using run length encoding and multiple scanning techniques /“. Online version of thesis, 1988. http://hdl.handle.net/1850/8309.

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Baxter, Rodney Charles. „The thermodynamics of binary liquid mixtures of compounds containing multiple bonds“. Thesis, Rhodes University, 1989. http://hdl.handle.net/10962/d1016079.

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Excess thermodynamic properties have been determined for several binary liquid mixtures with the aim of testing various thermodynamic theories and postulates. Excess molar enthalpies, HEm, have been determined using an LKB flow microcalorimeter and excess molar volumes, VEm, have been determined using an Anton Paar vibrating tube densitometer. The activity coefficients at infinite dilution ƴ∞₁₃, have been determined using an atmospheric pressure gas-liquid chromatograph. The excess molar enthalpies and the excess molar volumes have been measured at 298.15 K for systems involving the bicyclic compounds decahydronaphthalene (decalin), 1,2,3,4-tetrahydronaphthalene (tetralin), bicyclohexyl, or cyclohexylbenzene mixed with 1- hexene, 1-hexyne, 1-heptene, 1-heptyne, cyclohexene, 1,3-cyclohexadiene, 1,4- cyclohexadiene, or benzene. These excess properties have also been measured for systems where the bicyclic compound has been replaced with benzene, cyclohexane or n-hexane. The results show defmite trends related to the size, shape, and the degree of unsaturation of the component molecules. The Flory theory has been used to predict excess molar enthalpies and excess molar volumes for {(a bicyclic compound or benzene or cyclohexane or n-hexane) +(an n-alkane or a 1-alkene or a 1-alkyne or a cycloalkane or cyclohexene or a cycloalkadiene or benzene)}. The one parameter equations offer reasonably good correlations between the predicted and the experimental results. More insight into the origins of the contnbutions to the excess thermodynamic properties for these systems has been gained by considering the approximate equations of Patterson and co-workers, which separate the interactional and the free volume contributions to the excess molar enthalpy and the excess molar volume. The one parameter equations have adequately rationalized a good deal of the observed behaviour for HEm and VEm. The theory of Liebermann and co-workers, which does not employ any adjustable parameters, has not been as successful at predicting the excess thermodynamic properties for the above systems. The activity coefficients at infinite dilution have been measured at 278.15 K, 288.15 K and 298.15 K for n-bexane, 1-bexene, 1-hexyne, n-heptane, 1-heptene, 1-heptyne, cyclohexane, cyclohexene, 1,3-cyclohexadiene, 1,4-cyclohexadiene, and benzene, in decalin, tetralin, bicyclohexyl, and cyclohexylbenzene. Solvent losses from the column have been accounted for by an extrapolation procedure. The activity coefficient results together with the HEm and VEm values have been used to calculate the partial molar excess thermodynamic properties of mixing at infinite dilution. The partial molar excess properties at infinite dilution for decalin mixtures are similar to those for bicyclohexyl mixtures. There is also a similarity between the properties of the tetralin mixtures and the cyclohexylbenzene mixtures. The cycloalkadienes, benzene and the 1-alkynes exhibit a strong dissociation effect on being mixed with the saturated solvents, decalin and bicyclohexyl, but associate strongly with tetralin and with cyclohexylbenzene. The Flory theory bas been used to predict activity coefficients at infinite dilution from the experimentally determined HEm results for { (n-bexane or 1-hexene or 1-hexyne or naheptane or 1-heptene or 1-beptyne) + (a bicyclic compound)}. The theory is much better at predicting values for mixtures where both components are either saturated molecules or are unsaturated molecules than for {saturated + unsaturated} mixtures.

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Bücher zum Thema "Binary multiplier"

Pirlot, Paul. Brains and behaviours: From binary structures to multiple functions. 2. Aufl. Frelighsburg, Que: Orbis Pub., 1993.

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Symposium, International Astronomical Union. Birth and evolution of binary stars: Poster proceedings of IAU Symposium No. 200 on the formation of binary stars, 10-15 April 2000, Potsdam, Germany. Potsdam, Germany: Astrophysikalisches Institut Potsdam, 2000.

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Eggleton, Peter. Evolutionary Processes in Binary and Multiple Stars. Cambridge University Press, 2011.

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Evolutionary Processes in Binary and Multiple Stars. Cambridge University Press, 2006.

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Eggleton, Peter. Evolutionary Processes in Binary and Multiple Stars (Cambridge Astrophysics). Cambridge University Press, 2006.

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Lossless Compression Using Binary Necklace Classes and Multiple Huffman Trees. Storming Media, 2001.

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United States. National Aeronautics and Space Administration., Hrsg. NRA, first multiwavelength, multiple layer doppler imaging of an active binary. [Washington, DC: National Aeronautics and Space Administration, 1998.

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Ophir, Adi, und Ishay Rosen-Zvi. One Goy, Multiple Language Games. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198744900.003.0008.

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This chapter analyzes the characteristic features of the goy as a specific type of other, in both its legal (halakhic) and homiletical (aggadic) manifestations, as well as the division of labor between these two genres of the rabbinic corpus. It reconstructs the goy as a figure and a discursive position, and examines the technology of separation associated with it in both legal (laws of idolatry; purity; pedigree; murder, theft, recovering lost items; etc.) and non-legal (embryology; eschatology; daily liturgy; homilies on the exodus and the Sinai covenant; etc.) domains. The chapter demonstrates the consolidation of the binary, total, individualized discursive formation of Jew-goy opposition, through each of these aspects, and traces the triadic structure in which the opposition is embedded in the aggadic discourse, with God serving as the mediating position between the two parties. Analyzing the different domains together exposes the depth and comprehensiveness of the new structure.

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A Direct Sequence - Code Division Multiple Access/Binary Phase Shift Keying (DS-CDMA/BPSK) Modem Design. Storming Media, 1997.

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Buchteile zum Thema "Binary multiplier"

Pattimi, Hari, und Rajanbabu Mallavarapu. „Pipeline Decimal Multiplier Using Binary Multipliers“. In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications, 211–19. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_22.

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Walker, Alvernon, und Evelyn Sowells-Boone. „Efficient Set-Bit Driven Shift-Add Binary Multiplier“. In Advances in Intelligent Systems and Computing, 1346–50. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-01177-2_99.

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Miomo, Takahiro, Koichi Yasuoka und Masanori Kanazawa. „The Fastest Multiplier on FPGAs with Redundant Binary Representation“. In Lecture Notes in Computer Science, 515–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44614-1_56.

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Kelly, P. M., C. J. Thompson, T. M. McGinnity und L. P. Maguire. „A Binary Multiplier Using RTD Based Threshold Logic Gates“. In Artificial Neural Nets Problem Solving Methods, 41–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-44869-1_6.

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Barik, Ranjan Kumar, Ashish Panda und Manoranjan Pradhan. „A High-Speed Booth Multiplier Based on Redundant Binary Algorithm“. In Advances in Intelligent Systems and Computing, 569–75. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6875-1_56.

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Taverne, Jonathan, Armando Faz-Hernández, Diego F. Aranha, Francisco Rodríguez-Henríquez, Darrel Hankerson und Julio López. „Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication“. In Cryptographic Hardware and Embedded Systems – CHES 2011, 108–23. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23951-9_8.

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Yu, Po-Lung. „Binary Relations“. In Multiple-Criteria Decision Making, 7–19. Boston, MA: Springer US, 1985. http://dx.doi.org/10.1007/978-1-4684-8395-6_2.

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Zhou, Yu, und Zhuoyi Song. „Binary Decision Trees for Melanoma Diagnosis“. In Multiple Classifier Systems, 374–85. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38067-9_33.

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Narasimhamurthy, Anand. „Evaluation of Diversity Measures for Binary Classifier Ensembles“. In Multiple Classifier Systems, 267–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11494683_27.

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Turner, J. A., S. J. Chapman, A. S. Bhattal, M. J. Disney und A. P. Whitworth. „Binary and Multiple Star Formation“. In Kinematics and Dynamics of Diffuse Astrophysical Media, 323–24. Dordrecht: Springer Netherlands, 1994. http://dx.doi.org/10.1007/978-94-011-0926-0_52.

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Konferenzberichte zum Thema "Binary multiplier"

Neto, Horacio C., und Mario P. Vestias. „Decimal multiplier on FPGA using embedded binary multipliers“. In 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4629931.

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Haghiri, Saeed, Ali Nemati, Soheil Feizi, Amirali Amirsoleimani, Arash Ahmadi und Majid Ahmadi. „A memristor based binary multiplier“. In 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2017. http://dx.doi.org/10.1109/ccece.2017.7946783.

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Bawaskar, Ashish A., Vilas Alagdeve und Rashmi Keote. „High performance redundant binary multiplier“. In 2016 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2016. http://dx.doi.org/10.1109/iccsp.2016.7754358.

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Arun, Konduri, und K. Srivatsan. „A binary high speed floating point multiplier“. In 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2). IEEE, 2017. http://dx.doi.org/10.1109/icnets2.2017.8067953.

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Kumar Kattamuri, R. S. N., und S. K. Sahoo. „Computation sharing multiplier using redundant binary arithmetic“. In APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2010. http://dx.doi.org/10.1109/apccas.2010.5774869.

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Bhattacharjee, Pritam, Arindam Sadhu und Kunal Das. „A register-transfer-level description of synthesizable binary multiplier and binary divider“. In 2016 International Conference on Microelectronics, Computing and Communications (MicroCom). IEEE, 2016. http://dx.doi.org/10.1109/microcom.2016.7522470.

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Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois und Noureddine Chabini. „Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier“. In 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2017. http://dx.doi.org/10.1109/ccece.2017.7946692.

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Bisoyi, Abhyarthana, Mitu Baral und Manoja Kumar Senapati. „Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier“. In 2014 International Conference on Advanced Communication, Control and Computing Technologies (ICACCCT). IEEE, 2014. http://dx.doi.org/10.1109/icaccct.2014.7019410.

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Tsen, Charles, Sonia Gonzalez-Navarro, Michael Schulte, Brian Hickmann und Katherine Compton. „A Combined Decimal and Binary Floating-Point Multiplier“. In 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2009. http://dx.doi.org/10.1109/asap.2009.28.

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Akhter, Shamim, und Saurabh Chaturvedi. „Modified Binary Multiplier Circuit Based on Vedic Mathematics“. In 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2019. http://dx.doi.org/10.1109/spin.2019.8711583.

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Berichte der Organisationen zum Thema "Binary multiplier"

Knop, R., und R. G. Stokstad. BRANDEX: A FORTRAN/Pascal code to calculate the multiple binary splitting of an excited nucleus. Office of Scientific and Technical Information (OSTI), Mai 1989. http://dx.doi.org/10.2172/5704795.

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Reimus, Paul W. Binary Tracers and Multiple Geophysical Data Set Inversion Methods to Improve EGS Reservoir Characterization and Imaging. Office of Scientific and Technical Information (OSTI), April 2014. http://dx.doi.org/10.2172/1130518.

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