Zeitschriftenartikel: „ARM® Cortex-M0+“

1

Laban, Marek, und Milos Drutarovsky. „Low-cost ARM Cortex-M0 Based TRNG for IoT Applications“. Acta Electrotechnica et Informatica 18, Nr. 1 (01.03.2018): 52–56. http://dx.doi.org/10.15546/aeei-2018-0008.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

2

NISHINAGA, Toshifumi, und Masahiro MAMBO. „Implementation of µNaCl on 32-bit ARM Cortex-M0“. IEICE Transactions on Information and Systems E99.D, Nr. 8 (2016): 2056–60. http://dx.doi.org/10.1587/transinf.2015inp0013.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

3

Bannatyne, R., D. Gifford, K. Klein und C. Merritt. „High temperature / radiation hardened capable ARM® Cortex®-M0 microcontrollers“. Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (01.01.2016): 000046–50. http://dx.doi.org/10.4071/2016-hitec-46.

Der volle Inhalt der Quelle

Annotation:

Abstract VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

4

Patel, Zuber M. „DEVICE DRIVER FOR 3-AXIS ACCELEROMETER BASED ON ARM CORTEX-M0+ PROCESSOR“. MATTER: International Journal of Science and Technology 4, Nr. 2 (24.09.2018): 200–206. http://dx.doi.org/10.20319/mijst.2018.42.200206.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

5

Bannatyne, R., D. Gifford, K. Klein, K. McCarville, C. Merritt und S. Neddermeyer. „Creation of an ARM® Cortex®-M0 microcontroller for high temperature embedded systems“. Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, HiTEN (01.07.2017): 000031–35. http://dx.doi.org/10.4071/2380-4491.2017.hiten.31.

Der volle Inhalt der Quelle

Annotation:

Abstract This paper will describe the development and testing of a new ARM© Cortex©-M based microcontroller for high temperature electronic systems. High temperature and electrical overstresses can cause latch-up in CMOS devices that will interfere with normal device operation or destroy the device. For reliable operation in the downhole drilling environment it was necessary to immunize this device against latch-up using an innovation processing technique. HARDSIL® technology that allows reliable latch-up free operation at extreme temperatures will be described. Details on the qualification and testing of the product to ensure that it meets the challenging environment will also be discussed. This includes electrical testing and temperature cycling testing to ensure that the different package options for the silicon device are mechanically sound in a high temperature environment that exposes the silicon and packaging materials to thermal cycling. The ecosystem for the microcontroller will also be discussed – hardware and software development tools are required to optimize the use of the device in extreme temperature embedded systems. An ecosystem of components is also required to operate with the microcontroller in the high temperature harsh environment.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

6

Reyserhove, Hans, und Wim Dehaene. „A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs“. IEEE Journal of Solid-State Circuits 52, Nr. 7 (Juli 2017): 1904–14. http://dx.doi.org/10.1109/jssc.2017.2693241.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

7

Choifin, Mochamad, und Wiji Lestariningsih. „Design and Development of Microcontroller Battery Filling Control System Arm Cortex M0-Nuc 120 on Axial Axis Wind Turbine Type“. IOP Conference Series: Materials Science and Engineering 494 (29.03.2019): 012032. http://dx.doi.org/10.1088/1757-899x/494/1/012032.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

8

V., Arun, und Prabaharan N. „Micro controller based asymmetrical multilevel inverter“. IAES International Journal of Robotics and Automation (IJRA) 8, Nr. 1 (01.03.2019): 18. http://dx.doi.org/10.11591/ijra.v8i1.pp18-25.

Der volle Inhalt der Quelle

Annotation:

This paper presents the Asymmetrical multilevel inverter with 1:3 voltage propagation. Switching pulse for Asymmetrical multilevel inverter are generated using embedded controller in m-file using MATLAB. The Asymmetrical multilevel inverter with 1:3 voltage propagation can produce high quality output voltage with less number of switches and voltage sources compare to conventional multilevel inverters. Contrasting other switching schemes, the proposed Switching scheme significantly reduces the Total Harmonic Distortion (THD) and minimize switching losses and reduces the complexity. To evaluate the developed scheme, simulations are carried out through MATLAB and real time implementations are done through microcontroller ARM Cortex™-M0 Core. The simulation and hardware results are presented.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

9

Lallement, Guenole, Fady Abouzeid, Jean-Marc Daveau, Philippe Roche und Jean-Luc Autran. „A 1.1-pJ/cycle, 20-MHz, 0.42-V Temperature Compensated ARM Cortex-M0+ SoC With Adaptive Self Body-Biasing in FD-SOI“. IEEE Solid-State Circuits Letters 1, Nr. 7 (Juli 2018): 174–77. http://dx.doi.org/10.1109/lssc.2019.2897016.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

10

Benites, Luis A. C., Fabio Benevenuti, Adria B. De Oliveira, Fernanda L. Kastensmidt, Nemitala Added, Vitor A. P. Aguiar, Nilberto H. Medina und Marcilei A. Guazzelli. „Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA“. IEEE Transactions on Nuclear Science 66, Nr. 7 (Juli 2019): 1433–40. http://dx.doi.org/10.1109/tns.2019.2921796.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

11

Lallement, Guenole, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche und Jean-Luc Autran. „A 2.7 pJ/cycle 16 MHz, 0.7 $\mu\text{W}$ Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI“. IEEE Journal of Solid-State Circuits 53, Nr. 7 (Juli 2018): 2088–100. http://dx.doi.org/10.1109/jssc.2018.2821167.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

12

Onuki, Tatsuya, Wataru Uesugi, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew et al. „Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium–Gallium–Zinc Oxide FET Integrated With 65-nm Si CMOS“. IEEE Journal of Solid-State Circuits 52, Nr. 4 (April 2017): 925–32. http://dx.doi.org/10.1109/jssc.2016.2632303.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

13

Ungurean, Ioan. „Timing Comparison of the Real-Time Operating Systems for Small Microcontrollers“. Symmetry 12, Nr. 4 (08.04.2020): 592. http://dx.doi.org/10.3390/sym12040592.

Der volle Inhalt der Quelle

Annotation:

In automatic systems used in the control and monitoring of industrial processes, fieldbuses with specific real-time requirements are used. Often, the sensors are connected to these fieldbuses through embedded systems, which also have real-time features specific to the industrial environment in which it operates. The embedded operating systems are very important in the design and development of embedded systems. A distinct class of these operating systems is real-time operating systems (RTOSs) that can be used to develop embedded systems, which have hard and/or soft real-time requirements on small microcontrollers (MCUs). RTOSs offer the basic support for developing embedded systems with applicability in a wide range of fields such as data acquisition, internet of things, data compression, pattern recognition, diversity, similarity, symmetry, and so on. The RTOSs provide basic services for multitasking applications with deterministic behavior on MCUs. The services provided by the RTOSs are task management and inter-task synchronization and communication. The selection of the RTOS is very important in the development of the embedded system with real-time requirements and it must be based on the latency in the handling of the critical operations triggered by internal or external events, predictability/determinism in the execution of the RTOS primitives, license costs, and memory footprint. In this paper, we measured and compared the timing performance for synchronization throughout an event, semaphore, and mailbox for the following RTOSs: FreeRTOS 9.0.0, FreeRTOS 10.2.0, rt-thread, Keil RTX, uC/OS-II, and uC/OS-III. For the experimental tests, we developed test applications for two MCUs: ARM Cortex™-M4 and ARM Cortex™-M0+ based MCUs.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

14

Watson, Jeff, Maithil Pachchigar, Ross Bannatyne, Clay Merritt, Christopher Conrad, Glenn Smollinger und Earle Drack. „Performance Test Results of a Precision Data Acquisition and Control Platform for 200°C+ High Temperature Environments“. Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (01.05.2018): 000103–11. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000103.

Der volle Inhalt der Quelle

Annotation:

Abstract In recent years there has been an increasing selection of commercially available electronic components specified for very high temperature (200C+) operation, driven by the needs of harsh-environment applications such as oil and gas exploration/production, aerospace, heavy industrial, and automotive. However, there remains a significant technical challenge to integrate these components into reliable, high performance systems. We previously presented a complete reference design of a precision multichannel sensor data acquisition and control system rated to 200C, including characterized hardware, firmware, and software. The design is based around low power 16 bit SAR ADCs and an ARM® Cortex®-M0 processor and is optimized for high resolution and high throughput measurements while maintaining low power and a small footprint. In this paper we present the test results of this system over temperature. The reference platform is available off the shelf, including hardware design files, processor firmware source code, and PC software for data logging and display, providing engineers a rapid development tool for prototyping and a faster path to production for complex harsh-environment applications.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

15

Watson, Jeff, Maithil Pachchigar, Ross Bannatyne, Clay Merritt, Christopher Conrad, Glenn Smollinger und Earle Drack. „A Precision Data Acquisition and Control Platform for 200°C+ High Temperature Environments“. Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, HiTEN (01.07.2017): 000046–50. http://dx.doi.org/10.4071/2380-4491.2017.hiten.46.

Der volle Inhalt der Quelle

Annotation:

Abstract In recent years there has been an increasing selection of commercially available electronic components specified for very high temperature (200°C+) operation, driven by the needs of harsh-environment applications such as oil and gas exploration/production, aerospace, heavy industrial, and automotive. However, there remains a significant technical challenge to integrate these components into reliable, high performance systems. In this paper we present a complete reference platform implementation of a precision multichannel sensor data acquisition and control system rated to 200°C. The design offers a complete sensors-to-bits solution using a low power 16-bit, 600kSPS SAR ADC and an ARM® Cortex®-M0 based microcontroller. The signal chain is optimized for precision performance and accurate measurements while maintaining low power and a small footprint. The reference platform is available off the shelf, including hardware design files, processor firmware source code, and PC software for data logging and display, offering design engineers a rapid development tool for prototyping and a faster path to production for even complex harsh-environment applications, reducing design risk and evaluation time.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

16

Hema, K., und Muralidharan Muralidharan. „Design and Implementation of Next Generation Automotive Theft Preventive System“. Indonesian Journal of Electrical Engineering and Computer Science 9, Nr. 1 (01.01.2018): 118. http://dx.doi.org/10.11591/ijeecs.v9.i1.pp118-122.

Der volle Inhalt der Quelle

Annotation:

In this paper, we proposed to design a next-generation auto theft prevention system by adding significant enhancements and modernizing the existing security features. As vehicles turn out to be more refined, vehicle security frameworks must be more grounded than at any other time. A current vehicle uses remote keyless passage framework and Immobilizer framework as the primary weaponry against vehicle robbery. These structures avoid unapproved access of the vehicle to a particular degree, however, are not a secure one. Because of the straightforward and imperfect nature of these security frameworks, auto burglary occurrences worldwide are on the ascent. This venture needs a low power microcontroller however with elite prerequisites. LPC11C14 from NXP Semiconductors addresses these issues and in this manner picked as the primary MCU. It is an ultra-low-power ARM Cortex-M0 based microcontroller that can run up to 50MHz. It has 32KB of Flash memory and 8KB RAM.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

17

Büscher, Nils, Daniel Gis, Volker Kühn und Christian Haubelt. „On the Functional and Extra-Functional Properties of IMU Fusion Algorithms for Body-Worn Smart Sensors“. Sensors 21, Nr. 8 (13.04.2021): 2747. http://dx.doi.org/10.3390/s21082747.

Der volle Inhalt der Quelle

Annotation:

In this work, four sensor fusion algorithms for inertial measurement unit data to determine the orientation of a device are assessed regarding their usability in a hardware restricted environment such as body-worn sensor nodes. The assessment is done for both the functional and the extra-functional properties in the context of human operated devices. The four algorithms are implemented in three data formats: 32-bit floating-point, 32-bit fixed-point and 16-bit fixed-point and compared regarding code size, computational effort, and fusion quality. Code size and computational effort are evaluated on an ARM Cortex M0+. For the assessment of the functional properties, the sensor fusion output is compared to a camera generated reference and analyzed in an extensive statistical analysis to determine how data format, algorithm, and human interaction influence the quality of the sensor fusion. Our experiments show that using fixed-point arithmetic can significantly decrease the computational complexity while still maintaining a high fusion quality and all four algorithms are applicable for applications with human interaction.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

18

Chang, Tengfei, Thomas Watteyne, Brad Wheeler, Filip Maksimovic, Osama Khan, Sahar Mesri, Lydia Lee et al. „6TiSCH on SCμM: Running a Synchronized Protocol Stack without Crystals“. Sensors 20, Nr. 7 (30.03.2020): 1912. http://dx.doi.org/10.3390/s20071912.

Der volle Inhalt der Quelle

Annotation:

We report the first time-synchronized protocol stack running on a crystal-free device. We use an early prototype of the Single-Chip micro Mote, SCμM, a single-chip 2 × 3 mm2 mote-on-a-chip, which features an ARM Cortex-M0 micro-controller and an IEEE802.15.4 radio. This prototype consists of an FPGA version of the micro-controller, connected to the SCμM chip which implements the radio front-end. We port OpenWSN, a reference implementation of a synchronized protocol stack, onto SCμM. The challenge is that SCμM has only on-chip oscillators, with no absolute time reference such as a crystal. We use two calibration steps – receiving packets via the on-chip optical receiver and RF transceiver – to initially calibrate the oscillators on SCμM so that it can send frames to an off-the-shelf IEEE802.15.4 radio. We then use a digital trimming compensation algorithm based on tick skipping to turn a 567 ppm apparent drift into a 10 ppm drift. This allows us to run a full-featured standards-compliant 6TiSCH network between one SCμM and one OpenMote. This is a step towards realizing the smart dust vision of ultra-small and cheap ubiquitous wireless devices.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

19

Hoilett, Orlando S., Jenna F. Walker, Bethany M. Balash, Nicholas J. Jaras, Sriram Boppana und Jacqueline C. Linnes. „KickStat: A Coin-Sized Potentiostat for High-Resolution Electrochemical Analysis“. Sensors 20, Nr. 8 (23.04.2020): 2407. http://dx.doi.org/10.3390/s20082407.

Der volle Inhalt der Quelle

Annotation:

The demand for wearable and point-of-care devices has led to an increase in electrochemical sensor development to measure an ever-increasing array of biological molecules. In order to move from the benchtop to truly portable devices, the development of new biosensors requires miniaturized instrumentation capable of making highly sensitive amperometric measurements. To meet this demand, we have developed KickStat, a miniaturized potentiostat that combines the small size of the integrated Texas Instruments LMP91000 potentiostat chip (Texas Instruments, Dallas, TX, USA) with the processing power of the ARM Cortex-M0+ SAMD21 microcontroller (Microchip Technology, Chandler, AZ, USA) on a custom-designed 21.6 mm by 20.3 mm circuit board. By incorporating onboard signal processing via the SAMD21, we achieve 1 mV voltage increment resolution and an instrumental limit of detection of 4.5 nA in a coin-sized form factor. This elegant engineering solution allows for high-resolution electrochemical analysis without requiring extensive circuitry. We measured the faradaic current of an anti-cocaine aptamer using cyclic voltammetry and square wave voltammetry and demonstrated that KickStat’s response was within 0.6% of a high-end benchtop potentiostat. To further support others in electrochemical biosensors development, we have made KickStat’s design and firmware available in an online GitHub repository.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

20

Stančin, Sara, und Sašo Tomažič. „Computationally Efficient 3D Orientation Tracking Using Gyroscope Measurements“. Sensors 20, Nr. 8 (15.04.2020): 2240. http://dx.doi.org/10.3390/s20082240.

Der volle Inhalt der Quelle

Annotation:

Computationally efficient 3D orientation (3DO) tracking using gyroscope angular velocity measurements enables a short execution time and low energy consumption for the computing device. These are essential requirements in today’s wearable device environments, which are characterized by limited resources and demands for high energy autonomy. We show that the computational efficiency of 3DO tracking is significantly improved by correctly interpreting each triplet of gyroscope measurements as simultaneous (using the rotation vector called the Simultaneous Orthogonal Rotation Angle, or SORA) rather than as sequential (using Euler angles) rotation. For an example rotation of 90°, depending on the change in the rotation axis, using Euler angles requires 35 to 78 times more measurement steps for comparable levels of accuracy, implying a higher sampling frequency and computational complexity. In general, the higher the demanded 3DO accuracy, the higher the computational advantage of using the SORA. Furthermore, we demonstrate that 12 to 14 times faster execution is achieved by adapting the SORA-based 3DO tracking to the architecture of the executing low-power ARM Cortex® M0+ microcontroller using only integer arithmetic, lookup tables, and the small-angle approximation. Finally, we show that the computational efficiency is further improved by choosing the appropriate 3DO computational method. Using rotation matrices is 1.85 times faster than using rotation quaternions when 3DO calculations are performed for each measurement step. On the other hand, using rotation quaternions is 1.75 times faster when only the final 3DO result of several consecutive rotations is needed. We conclude that by adopting the presented practices, the clock frequency of a processor computing the 3DO can be significantly reduced. This substantially prolongs the energy autonomy of the device and enhances its usability in day-to-day measurement scenarios.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

21

Lowther, Rex, David Gifford, Wesley Morris, Jim Jensen, Scott Peterson und Kevin Atkinson. „Enabling Bulk Silicon CMOS Technology for Integration, Reliability, and Extended Lifetime at High Temperature“. Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (01.01.2015): 000020–26. http://dx.doi.org/10.4071/hiten-session1-paper1_4.

Der volle Inhalt der Quelle

Annotation:

Silicon Space Technology has developed a commercial bulk CMOS process technology, HardSIL™, which allows optimization of performance, power, and lifetime at high temperatures. A method for preventing latchup, originally developed for use in the space radiation environment, is presently applied to terrestrial high-temperature environments. With the possibility of latchup eliminated in scaled CMOS technology nodes, further designs specific for high-temperature environments have proceeded well. This novel technology has been applied to our 18Mb synchronous burst SBRAM and our ARM® Cortex® M0 microcontroller, and in two CMOS processes at the 130nm technology node (Texas Instruments and GLOBALFOUNDRIES). Extensive temperature testing on these parts demonstrates that bulk silicon CMOS technology has a practical temperature limit of 250°C or higher. Both the microcontroller and the SBRAM have been tested with clock rates up to 70MHz and at temperatures up to 260°C. Both parts have performed without error and without latchup under these conditions, and with low operating current and low leakage current. For example, the 130 million-transistor 18Mb SBRAM has average core leakage current of 580mA at 250°C and core voltage of 1.5V with test lots and simulations showing further reduction in leakage in the next, terrestrial version of this part. In addition, the 18Mb SBRAM is undergoing an endurance test at 250°C, presently at the 2500 hour milestone. Operation at temperatures beyond the present limit of the testing equipment (260°C) appears possible from extrapolation of current data. Integration levels of greater than 8 million gates on a bulk CMOS device would allow multi-core processors with large on-chip secondary caches. Additional DSP engines or other compute engines can be accommodated for processing high resolution three dimensional images in real time. This would provide substantial distributed processing in drilling or jet engine control. These system-on-chip (SOC) integration levels can substantially reduce mechanical failures in a subsystem by reducing the number of wire bonds from greater than 1000 connections to less than 100 connections. Integration of mixed-signal A/Ds and D/As as well as on-chip power management provides a path to further reduction in mechanical connections in a sub-system.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

22

Yu, Liang Jun, Li Hua Sun und Cui Cui Huang. „Design of Comprehensive Test Instrument Based on FPGA and Cortex-M0“. Applied Mechanics and Materials 312 (Februar 2013): 583–87. http://dx.doi.org/10.4028/www.scientific.net/amm.312.583.

Der volle Inhalt der Quelle

Annotation:

The design consists of three modules: the voltage amplitude measurement module, the level oscillator module and the amplitude-frequency characteristic test module. The voltage amplitude measurement module uses AD817 to consist three-stage amplifier. The magnification of each level can be adjusted for 1 times/10 times. At the same time, the author uses the Cortex-M0 for controlling the relay switch to achieve automatic range conversion. The principle of DDS is adopted in the level oscillator module. FPGA is used for realizing the phase accumulator, the phase modulator, the sine ROM look-up table. Digital signal is finally outputted by high-speed analog-to-digital conversion chip DAC900. Then, by controlling the 6-channel relay switch to make the magnification in the amplifying circuit,which can be adjusted step-by-step from-30dB to 20dB. Through outputting sine wave whose amplitude is fixed, but frequency is variable to the network under test, amplitude-frequency characteristic test module measures the relation betthe authoren the amplitude change of the output signal and the signal frequency to obtain the amplitude-frequency characteristics of the network under test..

APA, Harvard, Vancouver, ISO und andere Zitierweisen

23

Wang, Zu Lin, Jian Fei Ouyang, Qiang Fang und Yuan Liu. „Multi-Function Manipulator“. Advanced Materials Research 546-547 (Juli 2012): 1602–7. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.1602.

Der volle Inhalt der Quelle

Annotation:

This paper is for ordinary lathe supporting and design the capture of manipulator. Practice has proved, industrial robots can replace the hands of heavy labor, significantly reduce the labor intensity, improve working conditions, and improve labor productivity and automation level. In addition, it can be in high temperature, low temperature, deep water,cosmos, radioactive and other toxic, pollution environment conditions operation, more shows its superiority, with broad prospects. In the paper, the structure of the manipulator model design and Cortex-M0 micro controller (hereinafter referred to as M0) as the main controller in this paper. With multiple steering gear as the basis, make manipulator model, through the realization to the output M0 PWM control more than the steering gear, and finally achieve the acquirement manipulator workpiece, and the workpiece in designated spot.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

24

Wang, Tie Liu, Yang Dong, Jing Shen, Kui Leng und Hao Meng. „Design of a Digital Tower Tilting Measuring Instrument Based on MEMS Sensor“. Applied Mechanics and Materials 201-202 (Oktober 2012): 608–12. http://dx.doi.org/10.4028/www.scientific.net/amm.201-202.608.

Der volle Inhalt der Quelle

Annotation:

Abstract: This article introduces a new digital inclinometer . It is designed by the combination of MEMS sensors and LPC1114 which is popular with low-power, low-cost 32-bit cortex-M0 embedded microprocessor on the market. Kalman fitter the Digital signal output of MEMS accelerometer and gyroscope . Then calculate the inclination angle in degrees. Finally, transfers data to a remote server. The instrument is low cost, fast signal processing speed, and solar green energy. It has a small size, light weight, high accuracy and high precision. Then, it can be widely used in the tower tilting real-time monitoring of electricity, buildings, bridges and gravity reference system.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

25

Karmakar, Angshuman, Jose Maria Bermudo Mera, Sujoy Sinha Roy und Ingrid Verbauwhede. „Saber on ARM“. IACR Transactions on Cryptographic Hardware and Embedded Systems, 14.08.2018, 243–66. http://dx.doi.org/10.46586/tches.v2018.i3.243-266.

Der volle Inhalt der Quelle

Annotation:

The CCA-secure lattice-based post-quantum key encapsulation scheme Saber is a candidate in the NIST’s post-quantum cryptography standardization process. In this paper, we study the implementation aspects of Saber in resourceconstrained microcontrollers from the ARM Cortex-M series which are very popular for realizing IoT applications. In this work, we carefully optimize various parts of Saber for speed and memory. We exploit digital signal processing instructions and efficient memory access for a fast implementation of polynomial multiplication. We also use memory efficient Karatsuba and just-in-time strategy for generating the public matrix of the module lattice to reduce the memory footprint. We also show that our optimizations can be combined with each other seamlessly to provide various speed-memory trade-offs. Our speed optimized software takes just 1,147K, 1,444K, and 1,543K clock cycles on a Cortex-M4 platform for key generation, encapsulation and decapsulation respectively. Our memory efficient software takes 4,786K, 6,328K, and 7,509K clock cycles on an ultra resource-constrained Cortex-M0 platform for key generation, encapsulation, and decapsulation respectively while consuming only 6.2 KB of memory at most. These results show that lattice-based key encapsulation schemes are perfectly practical for securing IoT devices from quantum computing attacks.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

26

Bronchain, Olivier, und François-Xavier Standaert. „Breaking Masked Implementations with Many Shares on 32-bit Software Platforms“. IACR Transactions on Cryptographic Hardware and Embedded Systems, 09.07.2021, 202–34. http://dx.doi.org/10.46586/tches.v2021.i3.202-234.

Der volle Inhalt der Quelle

Annotation:

We explore the concrete side-channel security provided by state-of-theart higher-order masked software implementations of the AES and the (candidate to the NIST Lightweight Cryptography competition) Clyde, in ARM Cortex-M0 and M3 devices. Rather than looking for possibly reduced security orders (as frequently considered in the literature), we directly target these implementations by assuming their maximum security order and aim at reducing their noise level thanks to multivariate, horizontal and analytical attacks. Our investigations point out that the Cortex-M0 device has so limited physical noise that masking is close to ineffective. The Cortex-M3 shows a better trend but still requires a large number of shares to provide strong security guarantees. Practically, we first exhibit a full 128-bit key recovery in less than 10 traces for a 6-share masked AES implementation running on the Cortex-M0 requiring 232 enumeration power. A similar attack performed against the Cortex-M3 with 5 shares require 1,000 measurements with 244 enumeration power. We then show the positive impact of lightweight block ciphers with limited number of AND gates for side-channel security, and compare our attacks against a masked Clyde with the best reported attacks of the CHES 2020 CTF. We complement these experiments with a careful information theoretic analysis, which allows interpreting our results. We also discuss our conclusions under the umbrella of “backwards security evaluations” recently put forwards by Azouaoui et al. We finally extrapolate the evolution of the proposed attack complexities in the presence of additional countermeasures using the local random probing model proposed at CHES 2020.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

27

KINDAN, Ali Batuhan, und Selçuk KİZİR. „CAN Bus Based Firmware Update System for Distributed Embedded Systems Consisting of ARM Cortex-M0 Series Microcontrollers“. Kocaeli Journal of Science and Engineering, 31.05.2019. http://dx.doi.org/10.34088/kojose.494655.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

28

Gao, Si, Ben Marshall, Dan Page und Elisabeth Oswald. „Share-slicing: Friend or Foe?“ IACR Transactions on Cryptographic Hardware and Embedded Systems, 19.11.2019, 152–74. http://dx.doi.org/10.46586/tches.v2020.i1.152-174.

Der volle Inhalt der Quelle

Annotation:

Masking is a well loved and widely deployed countermeasure against side channel attacks, in particular in software. Under certain assumptions (w.r.t. independence and noise level), masking provably prevents attacks up to a certain security order and leads to a predictable increase in the number of required leakages for successful attacks beyond this order. The noise level in typical processors where software masking is used may not be very high, thus low masking orders are not sufficient for real world security. Higher order masking however comes at a great cost, and therefore a number techniques have been published over the years that make such implementations more efficient via parallelisation in the form of bit or share slicing. We take two highly regarded schemes (ISW and Barthe et al.), and some corresponding open source implementations that make use of share slicing, and discuss their true security on an ARM Cortex-M0 and an ARM Cortex-M3 processor (both from the LPC series). We show that micro-architectural features of the M0 and M3 undermine the independence assumptions made in masking proofs and thus their theoretical guarantees do not translate into practice (even worse it seems unpredictable at which order leaks can be expected). Our results demonstrate how difficult it is to link theoretical security proofs to practical real-world security guarantees.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

29

Bos, Joppe W., Marc Gourjon, Joost Renes, Tobias Schneider und Christine Van Vredendaal. „Masking Kyber: First- and Higher-Order Implementations“. IACR Transactions on Cryptographic Hardware and Embedded Systems, 11.08.2021, 173–214. http://dx.doi.org/10.46586/tches.v2021.i4.173-214.

Der volle Inhalt der Quelle

Annotation:

In the final phase of the post-quantum cryptography standardization effort, the focus has been extended to include the side-channel resistance of the candidates. While some schemes have been already extensively analyzed in this regard, there is no such study yet of the finalist Kyber.In this work, we demonstrate the first completely masked implementation of Kyber which is protected against first- and higher-order attacks. To the best of our knowledge, this results in the first higher-order masked implementation of any post-quantum secure key encapsulation mechanism algorithm. This is realized by introducing two new techniques. First, we propose a higher-order algorithm for the one-bit compression operation. This is based on a masked bit-sliced binary-search that can be applied to prime moduli. Second, we propose a technique which enables one to compare uncompressed masked polynomials with compressed public polynomials. This avoids the costly masking of the ciphertext compression while being able to be instantiated at arbitrary orders.We show performance results for first-, second- and third-order protected implementations on the Arm Cortex-M0+ and Cortex-M4F. Notably, our implementation of first-order masked Kyber decapsulation requires 3.1 million cycles on the Cortex-M4F. This is a factor 3.5 overhead compared to the unprotected optimized implementationin pqm4. We experimentally show that the first-order implementation of our new modules on the Cortex-M0+ is hardened against attacks using 100 000 traces and mechanically verify the security in a fine-grained leakage model using the verification tool scVerif.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

30

„A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator“. IEEE Journal of Solid-State Circuits 51, Nr. 1 (Januar 2016): 31–44. http://dx.doi.org/10.1109/jssc.2015.2477046.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

31

Haase, Björn, und Benoît Labrique. „AuCPace: Efficient verifier-based PAKE protocol tailored for the IIoT“. IACR Transactions on Cryptographic Hardware and Embedded Systems, 28.02.2019, 1–48. http://dx.doi.org/10.46586/tches.v2019.i2.1-48.

Der volle Inhalt der Quelle

Annotation:

Increasingly connectivity becomes integrated in products and devices that previously operated in a stand-alone setting. This observation holds for many consumer applications in the so-called "Internet of Things" (IoT) as well as for corresponding industry applications (IIoT), such as industrial process sensors. Often the only practicable means for authentication of human users is a password. The security of password-based authentication schemes frequently forms the weakest point of the security infrastructure. In this paper we first explain why a tailored protocol designed for the IIoT use case is considered necessary. The differences between IIoT and the conventional Internet use-cases result in largely modified threats and require special procedures for allowing both, convenient and secure use in the highly constrained industrial setting. Specifically the use of a verifier-based password-authenticated key-exchange (V-PAKE) protocol as a hedge against public-key-infrastructure (PKI) failures is considered important. Availability concerns for the case of failures of (part of) the communication infrastructure makes local storage of access credentials mandatory. The larger threat of physical attacks makes it important to use memory-hard password hashing. This paper presents a corresponding tailored protocol, AuCPace, together with a security proof within the Universal Composability (UC) framework considering fully adaptive adversaries. We also introduce a new security notion of partially augmented PAKE that provides specific performance advantages and makes them suitable for a larger set of IIoT applications. We also present an actual instantiation of our protocol, AuCPace25519, and present performance results on ARM Cortex-M0 and Cortex-M4 microcontrollers. Our implementation realizes new speed-records for PAKE and X25519 Diffie-Hellman for the ARM Cortex M4 architecture.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

32

Maia, Michelle Cavalcanti, und Sérgio Campello Oliveira. „Confecção de Sistema Embarcado Dual-Banda Capaz de se Comportar como um Nó de uma Rede de Sensores sem fio“. Revista de Engenharia e Pesquisa Aplicada 1, Nr. 1 (01.07.2016). http://dx.doi.org/10.25286/repa.v1i1.52.

Der volle Inhalt der Quelle

Annotation:

Recentemente, as redes de sensores sem fio (RSSFs) têm sido bastante estudadas. Elas utilizam a retransmissão de pacotes para economizar a energia dos nós e garantir a entrega de pacotes ao destino. As RSSFs podem ser uma das poucas soluções tecnicamente viáveis em locais sem infraestrutura de telecomunicações disponível. Contudo, em ambientes urbanos, as RSSFs podem ser uma alternativa para evitar a dependência das redes de celular para o envio de informações. Este artigo descreve um sistema embarcado, com microcontrolador ARM Cortex-M0+, que incorpora dois módulos transceptores RF, baseados nas bandas ISM de 433 MHz e de 2,4 GHz. O dispositivo foi idealizado para se comportar como um nó de uma rede de sensores sem fio. Ele realiza a comunicação com os outros nós por meio dessas tecnologias sem fio. Para decidir a tecnologia a ser utilizada ao transmitir pacotes de dados, foi testado um algoritmo adaptado que atua fortemente no descarte de retransmissões desnecessárias. Dependendo das situações do ambiente, do sistema e da rede, a tecnologia sem fio a ser utilizada é escolhida e as informações são retransmitidas entre os nós sempre com dois objetivos: garantir a entrega dos pacotes e minimizar o consumo de energia.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

33

Beneda, Károly. „Adevelopment of an Advanced Pressure Signal Acquisition Card for a Modular Turbojet Fadec System“. Acta Avionica Journal, 29.07.2021, 42–51. http://dx.doi.org/10.35116/aa.2021.0007.

Der volle Inhalt der Quelle

Annotation:

Gas turbine engines are very important in aviation. Pressure is one of the key thermodynamic parameters which, first of all, suffers radical change within the flow passage of a gas turbine, on the other hand, there are several accessories like fuel and oil supply, in which the pressure of the working medium is essential. The measurement of this variable is therefore inevitable in data acquisition or engine control systems. The author shows the process of development of an advanced pressure signal acquisition card that fits into a modular electronic control system of a turbojet engine. The unit incorporates numerous experiences gathered with the previous generation of this module regarding power supply and integrated sensors as well. Furthermore, there are several innovations that enable a more efficient installation, data acquisition and built-in test possibilities. The most important difference is the 32-bit ARM Cortex-M0+ microcontroller which allows faster operation which allows the acquisition of more signals, including additional functions as thrust measurement, digital input/output handling and many others. The unit operation was thoroughly assessed using simulated and real operating conditions as well.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

34

Gesper, Sven, Moritz Weißbrich, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume und Guillermo Payá-Vayá. „Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments“. International Journal of Parallel Programming, 26.12.2020. http://dx.doi.org/10.1007/s10766-020-00686-8.

Der volle Inhalt der Quelle

Annotation:

AbstractMicrocontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 $$\upmu $$ μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5$$\times $$ × higher performance and 2.4$$\times $$ × higher computational energy efficiency at a 1.6$$\times $$ × larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Zeitschriftenartikel zum Thema „ARM® Cortex-M0+“

Geben Sie eine Quelle nach APA, MLA, Chicago, Harvard und anderen Zitierweisen an