Um die anderen Arten von Veröffentlichungen zu diesem Thema anzuzeigen, folgen Sie diesem Link: 12-bit.
Dissertationen zum Thema „12-bit“
Geben Sie eine Quelle nach APA, MLA, Chicago, Harvard und anderen Zitierweisen an
Machen Sie sich mit Top-50 Dissertationen für die Forschung zum Thema "12-bit" bekannt.
Neben jedem Werk im Literaturverzeichnis ist die Option "Zur Bibliographie hinzufügen" verfügbar. Nutzen Sie sie, wird Ihre bibliographische Angabe des gewählten Werkes nach der nötigen Zitierweise (APA, MLA, Harvard, Chicago, Vancouver usw.) automatisch gestaltet.
Sie können auch den vollen Text der wissenschaftlichen Publikation im PDF-Format herunterladen und eine Online-Annotation der Arbeit lesen, wenn die relevanten Parameter in den Metadaten verfügbar sind.
Sehen Sie die Dissertationen für verschiedene Spezialgebieten durch und erstellen Sie Ihre Bibliographie auf korrekte Weise.
1
Ricci, Luca. "Design of a 12-bit 200-MSps SAR Analog-to-Digital converter." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-284559.
Der volle Inhalt der QuelleAnnotation:
The Successive Approximation (SAR) Analog-to-Digital converter is one of the most energy-efficient A/D converter. In this thesis, the development of a SAR ADC in a 28-nm CMOS technology based on charge redistribution is presented.The implemented SAR ADC uses a switching procedure based on a modified version of the mono- tonic switching algorithm to reduce the switching energy and area of the DAC. The DAC is a binary- weighted array of unit capacitors. A unit custom capacitor has been designed with a value of 0.8 fF to reduce the DAC energy consumption. Two comparators have been implemented, a dynamic comparator and a static comparator. The dynamic implementation allows to obtain better performance. Therefore, the dynamic comparator is chosen for the SAR ADC. The sampling switches are bootstrapped to reduce the non-linearity introduced when the input signal is sampled. The SAR operations are controlled by an asynchronous logic implemented as a behavioural model in Verilog-A.The effect of the designed circuits on the linearity of the converter is assessed with the integral non- linearity (INL) and differential non-linearity (DNL). Moreover, the performance of the ADC are assessed in terms of signal-to-noise-and-distortion ratio (SNDR). The co-simulation of Verilog-A behavioural models with circuit schematics allowed to evaluate the effect of each block on the overall performance of the ADC. The co-simulations show that the ADC is able to achieve an ENOB of 10.9 at a sampling rate of 200 MSps with a power consumption of 2.83 mW. The resulting FoM is 7.4 fJ/conv-step.<br>SAR (Analog-Digital-omvandlaren) är en av de mest energieffektiva omvandlare. I den här avhandlingen är utvecklingen av en SAR ADC i en 28-nm CMOS-teknik baserad på laddning omfördelning presen- teras.Den implementerade SAR ADC använder en omkopplingsprocedur baserad på en modifierad version av den monotoniska omkopplingsalgoritm för att reducera omkopplingsenergin och DAC-området. DAC är en binärviktad matris med enhetskondensatorer. En anpassad kondensator för enheten har utformats med ett värde av 0,8 fF för att minska DAC-energiförbrukningen. Två komparatorer har implementerats, en dynamisk komparator och en statisk komparator. Den dynamiska implementering gör det möjligt att få bättre prestanda. Därför väljs den dynamiska komparatorn SAR ADC. Provtagningsomkopplarna startas upp för att minska icke-lineariteten introduceras när insignalen samplas. SAR-operationerna styrs av en asynkron logik implementerad som en beteendemodell i Verilog-A.Effekten av de designade kretsarna på konverterarens linearitet bedöms med integralen icke-linearitet (INL) och differentiell icke-linearitet (DNL). Dessutom är ADC: s prestanda bedömdes i termer av signal-till-brus-och-distorsionsförhållande (SNDR). Samsimulering av Verilog-A beteendemodeller och scheman tillåts utvärdera effekten av varje block på prestandan hos ADC. Omvandlaren kan uppnå en ENOB på 10,9 med en samplingshastighet på 200 MSps, vilket resulterar i en FoM eller 7,4 fJ / konv.- steg.
2
Todorov, Borislav St. "Performance evaluation of 12 and 14-bit converter technology for software radio applications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0016/MQ57742.pdf.
Der volle Inhalt der Quelle
3
Todorov, Borislav St (Borislav Stefanov) Carleton University Dissertation Engineering Systems and Computer. "Performance evaluation of 12 and 14-bit converter technology for software radio applications." Ottawa, 2000.
Den vollen Inhalt der Quelle finden
4
Nuytkens, Peter R. (Peter Read). "A 12-bit 500 MHz GaAs MESFET digital-to-analog converter with p+ ohmic contact isolation." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/12760.
Der volle Inhalt der QuelleAnnotation:
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.<br>Vita.<br>Includes bibliographical references (leaves 134-135).<br>by Peter R. Nuytkens.<br>M.S.
5
Thomsson, Pontus, and Aghamiri Cyrus Seyed. "Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177548.
Der volle Inhalt der QuelleAnnotation:
Wireless communication technologies continue to evolve to meet the demand for increased data throughput. To achieve higher data throughput one approach is to increase the bandwidth. One problem related to very large bandwidths is the implementation of digital-to-analog converters with sampling rates roughly in the 5 to 20 GHz range. Traditionally, current-steering data converters have been the go-to choice but their linearity suffers at higher frequencies. An alternative to the current-steering digital-to-analog converter is the voltage-mode digital-to-analog converter, which is an attractive option for integration into digital intensive application-specific integrated circuits due to its digital-in-nature architecture. In this thesis, a resistive voltage-mode digital-to-analog converter with an integrated low-dropout voltage regulator is proposed for a sampling rate of 16 GSps. The proposed resistive voltage-mode digital-to-analog converter with an output impedance matched to a 100 Ω load, achieves a spurious-free dynamic range of 64 dBc and intermodulation distortion of 66 dBc for output frequencies up to 5.5 GHz in the worst process corner.
6
Juo, Ru-Hung, and 卓儒宏. "12-bit Digital Transmitter for VDSL." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/qqzuha.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺北科技大學<br>電機工程系研究所<br>99<br>This thesis describes the chip implementation of a 200 MHz CMOS digital transmitter based on VDSL system specification. which is composed of a 12-bit, 200 MHz digital to analog converter, and a fully differential current-mode line driver. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology.
For high-speed application, the digital to analog converter adopts the switch-current mode architecture. This is a 12-bit digital-to-analog converter (DAC) is implemented with M-bit segmented, which is implemented with 3-bit binary and 9-bit unary. Buffers are used to isolate the output of digital circuit and to reduce the glitch of current. Furthermore, in case of achieving small layout area, reducing the complexity of digital circuit, 9-bit unary is composed with the 3-bit and 6-bit thermometer-encoding architecture. In order to mitigate the process variation and linear error, current source array (CSA) is applied. The simulation of 12-bit DAC shows that the max current is 4095 μA, the integral nonlinearity (INL) and the differential nonlinearity (DNL) are 0.32 LSB and 0.39 LSB respectively.
In order to have high power efficiency, in line driver the utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. Furthermore, the capacitive feed-forward path is introduced used to reduce the crossover distortion; and that the current-feedback circuit is added to increase linearity. According to the simulation result the output voltage of the proposed line driver is 2 VPP at differential load of 100 Ω, the power supply of 1.8 V and the operating frequency of 100 MHz.
7
Sheng-YangWeng and 翁聖洋. "A 14-Bit 2GS/s and 12-Bit 4GS/s Reconfigurable DAC with Triple Modes." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/33707004393574784529.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系<br>102<br>In this thesis, a triple-mode 14-bit 2GS/s or 12-bit 4GS/s reconfigurable current-steering digital-to-analog converter (DAC) is presented. For different DAC applications, triple mode is proposed, which means over-sampling mode, Nyquist mode, and over-Nyquist mode. The target of this work is that using a single DAC chip to fulfill all of the applications and with better performances than any state-of-the-art work. For this target, many techniques are proposed to improve the performances. In current-steering DAC design, current source mismatch is a main problem. Minimum switching dynamic element matching (MSDEM) and data weighted averaging (DWA) are adopted to process the harmonic distortion caused by mismatch. In addition, for over-sampling mode, DWA is used to improve the performance in narrow band. Moreover, for over-Nyquist mode, a novel method is proposed which makes the signal consumption 〈 10dB and spurious-free dynamic range (SFDR) 〉 65 dB up to 3rd Nyquist band.
The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.082mm2 of active area. The measurement results show that the DAC achieves 〉60dB SFDR from dc to 0.55GHz at 1.1GS/s and the 14-bit Nyquist band performance is the best in figure of merit (FOM) comparing to state-of-the-art works.
8
Hsiao, Ming-Kai, and 蕭名開. "12-Bit low power SAR-ADC for ECG application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05793753502319870096.
Der volle Inhalt der QuelleAnnotation:
碩士<br>淡江大學<br>電機工程學系碩士在職專班<br>99<br>With the constant improvement on highly advanced technology nowadays, under the development of the microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP) influence, Analog to Digital Converter (ADC) has become a widely used application. The request for ADC specification will therefore be strict, as a result, more research will be conducted aggressively in the industrial and academic field.
In order for ADC application become extensively used and correspond to the requirement of the present electronic products, four conditions need to be concerned: Speed, Resolution, Power, and Area. However, under the restriction of the factual conditions, in the process of designing, none of the ADC models was able to entirely correspond to the four conditions, thus trade-off was made for several application.
This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system. It is aimed for capturing the probability of arrhythmia through monitoring and recording ECG for a long period of time. Consequently, the power voltage was defined in 1V for low power consumption purpose.
The chip was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The sample rate is 600Hz in 150Hz signal bandwidth. Simulation results show that the SNDR and ENOB of the SAR-ADC with an input frequency of 24Hz are 67.53dB and 10.92dB. The power dissipation is 20.28μW under 1V power supply.
9
Lin, Chi-shen, and 林綮紳. "A 12-bit Power Saving DAC with Clock Controller." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7f3sus.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>102<br>In this thesis, A 12-bit 1GS/s DAC for wireless communications is proposed. In order to achieve the high performance requirements, the current-steering architecture is the most suitable and widely used in the present design. The segmented current steering architecture that comprises 8MSB’s thermometer code and 4LSB’s binary-weighted is used. In this design, a new technique of the column clock controller (CCC) is proposed to improve the DAC performance. The Column clock controller (CCC) is able to reduce the clock feed-through effect for DAC and reduce power consumption from switching activity.
The designed DAC implemented in TSMC 90nm CMOS technology. When the CCC is enabled, the simulation results show that INL is 0.019LSB and DNL is 0.008LSB; When the CCC is disabled, the simulation results show that INL is 0.018LSB and DNL is 0.011LSB. When the CCC is enabled and disabled, the SFDR is 85dB and 82dB respectively. The power consumption is 24mW.
10
LAI, CHENG-QIAN, and 賴承謙. "Ultra Low Power 12-Bit Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/yvz8sn.
Der volle Inhalt der Quelle
11
Wei-ChengHung and 洪偉程. "A 12-bit 2GS/s Current-Steering DAC in 0.07mm2." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/19395243757378184961.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>101<br>In this thesis, a 12-bit 2GS/s current-steering DAC design is presented to overcome the three main nonlinearity sources, which are current source mismatch, output transition nonlinearity, and finite output impedance, and achieve high-speed high-resolution characteristic. Firstly, for the current source mismatch, two different dynamic element matching (DEM) algorithms, random rotation-based binary-weighted selection (RRBS) and data weighted averaging (DWA), are adopted to process the harmonic distortion tones caused by mismatch error for different applications. Secondly, reduced-switch and non-cascoded modifications of the current cells increase the output transition speed and decrease the influence of transition nonlinearity. In addition, a digital resetting return-to-zero (RTZ) is adopted to further enhance the output transition linearity. Finally, for the finite output impedance, an output impedance compensation circuit is proposed to compensate the nonlinear impedance curve of current cells. By dealing with these nonlinearity sources, this DAC performs excellent at high sampling rate.
The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.07mm2 of active area. The measurement results show that the DAC achieves 〉70dB SFDR from dc to 400MHz sampling at 1GHz and performs best in figure of merit (FOM) comparing to state-of-the-art works.
12
Ghezawi, Saeed Ramzi. "Characterization of a 12-bit pipeline analog to digital converter." 2009. http://etd.utk.edu/2009/May2009Theses/GhezawiSaeedRamzi.pdf.
Der volle Inhalt der Quelle
13
Jih, Wei-Shu, and 日韋舒. "Design and Implementation of 12-bit Sub-ranged SAR ADCs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/cq776s.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺灣科技大學<br>電子工程系<br>106<br>This thesis is aimed to present 12-bit Sub-ranged successive approximation register (SAR) analog-to-digital converters (ADCs). In order to speed up the sampling rate, the ADC architecture is proposed using the subrange SAR operation. Besides, by applying a new dynamic latch logic architecture, the DAC control delay between the comparator output and DAC switch is reduced. Thus, the sampling rate of the ADC is also improved. To achieve the 12-bit linearity requirement, the binary-window and capacitor-swapping switching techniques are applied in the DAC.
Two ADCs were implemented in TSMC 65 nm digital CMOS process. The first one is a 12-bit 100-MS/s ADC, which occupies an active area of 0.048 mm^2 . At 100-MS/s, the ADC consumes a total power of 1.8 mW from a 1.2V supply. The measured ENOB is 9.65 bits. Without the capacitor swapping scheme, the measured SNDR and SFDR are 59.84dB and 67.18dB, respectively. After using the swapping scheme, the SFDR is improved to 80.74dB. The measured DNL is+1.47/-0.72 LSB and the INL is +4.01/-0.7 LSB. The other one is a 12-bit 250-MS/s ADC which occupies an active area of 0.124 mm^2 . Using a 1.2V supply and a 250 MHz sampling rate, the measured SNDR and SFDR are 64dB and 82.7dB, respectively.
14
Hsu, Wei-Hung, and 徐偉宏. "A 12-bit 250-MSample/sec Digital-to-Analog Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/50738999911029568589.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>92<br>The goal of this research was to design a low power 12-bit, 250 MHz digital-to-analog converter suitable for applications in video. The proposed DAC composed of segmented coding method for MSB and LSB bits, where the thermometer way for MSB and binary-weighted for LSB. Besides, to promote linearity of performance and suppress undesired glitch, the signal controlled differential switches of current sources is pre-processed by de-glitch latch. There is trade-off between accuracy and area for mismatch issue of current sources. The routing complexity and parasitic capacitance have to be taken into account for speed and signal synchronization.
This DAC is to be implemented in a 0.25 mm 1P5M mixed-signal CMOS process provided by TSMC, with active area of 0.43 mm2 (760 mm × 560 mm) and total area including PADs is 1.67 mm2 (1291 mm × 1291 mm). The simulation results revealed ENOB of 11.24 bit at Nyquist rate transition for 250 MSPS.
15
Gandara, Miguel Francisco. "A 12-bit, 10 Msps two stage SAR-based pipeline ADC." 2012. http://hdl.handle.net/2152/19973.
Der volle Inhalt der QuelleAnnotation:
The market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the
utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is presented
that attempts to mitigate some of the sampling rate limitations of a SAR while maintaining its power and resolution advantages. Special techniques are used to reduce the overall sampling capacitance required in both SAR stages and
to increase the linearity of the multiplying digital to analog converter (MDAC) output. The SAR sampling network, control logic, and MDAC blocks are completely
implemented. Ideal components were used for the clocking, comparators, and switches. At the end of this design, a figure of merit of 51 fJ/conversion-step was achieved.<br>text
16
Lee, Chien-Wei, and 李建緯. "A 12-bit High Speed DAC with Novel Self-Calibrated Technique." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/88294442353421270077.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立中正大學<br>電機工程所<br>95<br>We design the Digital-to-Analog Converter (DAC) with Current-Steering architecture to achieve high-speed specification and propose a novel calibration technique in this thesis. The technique could directly suppress the differential nonlinearity (DNL) and integral nonlinearity (INL) and furthermore lift up dynamic performance to increase the linearity of whole DAC effectively. By this technique, we have attained the destination of high speed, high resolution and low power consumption because of successfully improving the drawback caused by requiring large scale area of unit source to drop random error.
The high-speed 12-bit Digital-to-Analog Converter, whose maximum sampling rate is 400MS/s, is implemented in TSMC CMOS process. New digital calibration circuit can keep the performance in an outstanding level even with a dramatically slight unit source area and lack of specific output stage [17][18].
17
Chou, Wen-Duen, and 周文敦. "12-bit/200MHz Digital Transmitter with Double Sampling-Rate for VDSL." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/28ctf3.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺北科技大學<br>電機工程系所<br>101<br>This thesis describes the chip implementation of a 200MHz/double sampling-rate CMOS digital transmitter based on VDSL system specification. This digital transmitter is composed of a 12-bit, 200MHz digital-to-analog converter (DAC) operated in the proposed double sampling-rate structure, and a fully differential current-mode line driver integrated with a 2nd-ordered transmitting filter. The digital transmitter had been fabricated with the TSMC 0.18μm 1P6M CMOS technology.
VDSL (Very High-Bit Rate Digital Subscriber Line) technology permits the transmission of asymmetric and symmetric data rate up to 100Mbps for upstream and downstream direction on twisted copper pairs using a signal bandwidth up to 30MHz. It can be deployed from fiber-optic connected cabinets located near the customer premises.
For such high-speed applications, the digital-to-analog converter adopts the switch-current mode architecture with a double sampling-rate operation. Under 200MHz clock frequency, the digital-to-analog converter can reach the equivalent 400MHz conversion rate. The simulation of 12-bit DAC shows that the maximum output current is 4095μA, and the conversion signal bandwidth is up to 30MHz.
To conform the bandwidth requirements of VDSL/VDLS2, a transmitting filter is used after the DAC stage to filter the high-frequency harmonics. With the DAC double sampling-rate operation mode, a 2nd-ordered filter is satisfactory in the bandwidth performance. The line drive circuit integrates a transmitting filter and a current-feedback amplifier with capacitor-feedforward compensation to reach high linearity and low harmonic distortion. According to the simulation result, the output voltage of the proposed line driver is 2Vpp at differential load of 100Ω.
18
Tsung-HsienLin and 林宗賢. "A 12-bit 3GS/s 4xTI Pipelined ADC with DigitalBackground Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/3u3jex.
Der volle Inhalt der Quelle
19
Hsieh, Yi-Cheng, and 謝易成. "12-bit SAR ADC with Mixed Switching and Background Offset Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ngq679.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立交通大學<br>電機工程學系<br>106<br>This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used.
For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling rate, simulation results achieve 66.73dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 10.79 effective number of bits (ENOB) at 1.975MHz input frequency. Its power consumption is 736.23µW and figure-of-merit (FOM) is 41.58 fJ/conversion-step. For the SAR ADC with adaptive capacitor at 1.8V supply voltage and 50KHz sampling rate, simulation results achieve 72.56dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 11.76 effective number of bits (ENOB) at 9.876KHz input frequency. Its power consumption is 18.31µW and figure-of-merit (FOM) is 105.59 fJ/conversion-step.
For the SAR ADC with charge pump at 1.8V supply voltage and 1MHz sampling rate, measurement results achieve 39.50dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 6.27 effective number of bits (ENOB) at 12.3444KHz input frequency. Its power consumption is 186.3762µW.
20
Chen, Chien-Chung, and 陳建仲. "An Area-Efficient 12-bit 20 MHz Two-Step SAR ADC." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t295d5.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立清華大學<br>電子工程研究所<br>107<br>This thesis describes an analog-to-digital converter (ADC) for FHD image sensors. The ADC specification is 12-bit resolution and the sampling rate is 20 MHz. The architecture of this ADC is two-step successive approximation register (SAR) ADC. The disadvantage of the traditional SAR ADC is the great area of capacitor. When we add every 1-bit resolution, the area of the capacitor will double. In this thesis, the number of unit capacitor of the two-step SAR ADC is reduced to 1/16th of that of a conventional 12-b SAR ADC.
The prototype was fabricated using TSMC 0.18um 1P6M CMOS technology. At a 1.8-V supply and 20-M Hz sampling rate, simulations showed that the ADC achieves a SNDR of 71.78dB, an ENOB of 11.63 and power consumes 3.62mW.
The chip area including I/O pad is 1.109mm2 .The simulating results of static analysis DNL and INL are （1.004 / -1 LSB） and （0.756 / -1.007 LSB）.
Measurements showed that the chip layout might not be symmetric enough and it might degrade the ADC performance.
21
Chiang, Min-Sheng, and 江民陞. "Design and Implementation of 12-bit Ultra-Low-Power SAR ADCs." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/67t8b9.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺灣科技大學<br>電子工程系<br>107<br>This thesis is aimed to present 12-bit Ultra low power successive approximation register (SAR) analog-to-digital converters (ADCs). In order to save the power, the ADC architecture is proposed using the synchronous clocking operation and low voltage supply. Besides, by applying a bypass window for EKG signals. To achieve the 12-bit linearity requirement, the bypass window and capacitor-swapping switching techniques are applied in the DAC.
Two ADCs were implemented in UMC 180 nm CMOS process. The first one is a 12-bit Synchronous-SAR ADC for IoT applications, which occupies an active area of 0.095 〖"mm" 〗^"2" . At 100-MS/s, the ADC consumes a total power of 735nW from a 0.7V supply. The measured ENOB is 10.4 bits. Without the capacitor swapping scheme, the measured SNDR and SFDR are 64 dB and 75 dB, respectively. After using the swapping scheme, the SFDR is improved to 85 dB. The other one is a 12-bit SAR ADC which occupies an active area of 0.274 〖"mm" 〗^"2" . Using a 0.7V supply with the sampling rate of 100 kHz, the total power is 1.26 W. The measured SNDR and SFDR are 64 dB and 80 dB, respectively.
22
Lee, Yueh-Ru, and 李岳儒. "Design of 12-bit SAR ADCs with Analog Background Calibration Technique." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5gjh23.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立交通大學<br>電機工程學系<br>107<br>In this thesis, the design consideration of low-speed, mid/high resolution successive approximation register analog-to-digital converters (SAR ADCs) is discussed in depth. The three mentioned ADCs are all designed for biomedical applications, such as the external signal receiver of bone-guided cochlear implants. All the ICs were fabricated by using 0.18-μm 1P6M TSMC CMOS process.
The first IC is a 10-bit 47KS/s SAR ADC which adopts monotonic switching technique. Due to the layout simplicity of the digital blocks, the power consumption is as low as 2.6μW. At normal sampling rate and provided with a 1.8VPP input signal, the measured ENOB, SNDR and SFDR are 9.77-bit, 60.55dB, and 82.18dB, respectively. It occupies an area of 598μm×786μm and the FOM is 63 fJ/conv.step. The second one is a 12-bit 62KS/s calibration-free SAR ADC which adopts VCM-based switching technique and includes redundant capacitors to counter comparator offset and reference voltage error. At normal sampling rate and provided with a 1.8VPP input signal, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 11-bit, 68dB, 83dB, 209μV, and 6.7μW, respectively. It occupies an area of 587μm×599μm and the FOM is 53 fJ/conv.step. The third one is also a 12-bit 62KS/s SAR ADC, but with analog background calibration circuit, which quantizes and calibrates the capacitor mismatch error according to the comparator output while certain codes in the register are detected. While disabling the calibration feature and provided with a 1.8VPP input signal, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 10.4-bit, 64.4dB, 73dB, 193μV, and 7.4μW, respectively. While enabling the calibration feature and under the same circumstance, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 10.8-bit, 66.6dB, 79dB, 235μV, and 9μW, respectively. It occupies an area of 560μm×350μm and the FOM is 83 fJ/conv.step.
23
Huang, Chia-Hsuan, and 黃嘉玄. "Low Power 12-bit Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/82543200626928576057.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>Generally, the signal bandwidth of biomedical signals ( EEG, ECG, Oxygen Saturation, Heart Rate, Temperature ) is under 10 kHz [29]. For portable biomedical acquisition system, lower power A/D converter is an important component that can determine the performance of whole system.
In this paper, a 1.8V 12-bit 200-kS/s successive approximation analog-to-digital converter (SAR ADC) is presented in this work. In order to overcome the biomedical signal’s dc shift and acquire accurately, the proposed ADC receives rail-to-rail input and performs 12-bit resolution (10-bit is the basic requirement for normal biomedical signal). Moreover, the digital-to-analog converter without reference voltage (WRV) and binary capacitor array is also adopted to reduce the total chip area. With these properties, the proposed ADC can be easily integrated with other components in biomedical acquisition system at low cost. The proposed converter is designed in a 0.18-μm CMOS process for biomedical application. Simulation results show that both INL and DNL errors are well controlled in 0.34LSB. The measurement results show SNDR is 49.7 dB and the total power consumption is 76.32-μW at 1.8V supply voltage. The core area of the test chip is 0.082 mm2.
24
Sousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Dissertação, 2009. http://hdl.handle.net/10216/57854.
Der volle Inhalt der QuelleAnnotation:
Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões Moreira<br>Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
25
Yen, Chia-Wei, and 顏嘉威. "Design and Implementation of a 12-bit 100-MS/s SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/74411232626403249189.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺灣科技大學<br>電子工程系<br>105<br>This thesis presents a 12bit 100MS/s successive approximation register analog to digital converter (SAR ADC). Sub-ranged SAR architecture is used to achieve 100MS/s sampling rate. This ADC design is based on SAR architecture but with sub-ranged operation. A low resolution and high speed binary-search ADC is used to quantize first five MSBs for speeding up. For 12-bit linearity requirement, capacitor swapping technique is used in digital to analog converter (DAC) to prevent the use of large capacitor array.
This ADC was implemented in TSMC 65nm digital CMOS process. The 12-bit ADC occupies an active area of 0.102mm2. At 1.2V supply voltage and 100MHz sampling rate, the measured dynamic performance, ENOB is 10.0 bit and SNDR achieves 62dB. SFDR with capacitor swapping techniques is 82dB. The measured static performance, DNL is from +2.23LSB to -0.87LSB, INL is from +1.81LSB to -1.49LSB.
26
Wang, Chih-Cheng, and 王智正. "A 12-BIT SEGMENTED DIGITAL-TO-ANALOG CONVERTOR FOR LCD DRIVER ICS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/00210556998549254472.
Der volle Inhalt der QuelleAnnotation:
碩士<br>大同大學<br>通訊工程研究所<br>98<br>In this thesis, a linear 12 bit segmented digital-to-analog converter (DAC) for LCD source driver is proposed. This design employs a method that reduces the area of an LCD source driver without increasing extra power consumption. A typical 12-bit resistor-string DAC requires a 4096-to1 selector. The proposed architecture uses three sets of 4-bit subDACs to reduce the complexity of a 12-bits resistor-string DAC. The digital signal selects 3 voltages from the tree subDACs, and then adds these voltages up by a Switched-Capacitor (SC) adder. The Opamp of the SC adder is also used as the output buffer without extra power consumption.
The proposed LCD source driver was simulated using TSMC 0.35μm 2P4M CMOS process model with a 5V supply. The area for each channel consisting of selectors and an SC adder is about 120μm ×480μm.
27
Tsai, Tsung-Yen, and 蔡宗諺. "A 12-bit 500-MSamples/s Current-Steering CMOS D/A Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/94140123580238255874.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立交通大學<br>電信工程系所<br>95<br>Digital-To-Analog converters are essential components of modern applications, such as digital signal synthesis, video signal processing, and both wired and wireless transmitters.For data converters used in communications applications, the integral nonlinearity (INL) and
differential nonlinearity (DNL) are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the spurious-free dynamic range (SFDR).
The major target specification for SFDR of this paper, a 12-bit 500-MSample/s D/A converter, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to
derive maximum benefit from this relatively advanced technology. This architecture is divided into a coarse sub-DAC and a binary-weighted fine sub-DAC. The differential
switches of current sources are controlled by deglitch
latch. The routing complexity and parasitic capacitance have to be considered for speed and signal synchronization. A 12-bit 500-MSample/s current-steering D/A converter integrated in a TSMC 0.18μm CMOS technology is presented. It is based on a current steering doubly segmented 8 + 4 architectureand requires no trimming, no calibration, or dynamic averaging. The increased switching noise associated with a high degree of segmentation has been reduced by a new latch. The measure resultant shows that with the signal frequency of 34.33 MHz at the update rate of 100 MHz, the SFDR is 32 dB. The differential nonlinearity and integral nonlinearity are below 3.3 and 5.4 least significant bits (LSB’s), respectively. The converter consumers a total power of 128 mW and it’s active area is 1.615 mm2.
28
Sousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Master's thesis, 2009. http://hdl.handle.net/10216/57854.
Der volle Inhalt der QuelleAnnotation:
Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões Moreira<br>Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
29
Yi-AnChao and 趙一安. "A 12-bit 100MHz DAC with Dynamic Element Matching and Output Impedance Calibration." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/56113954744671940792.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>98<br>Current-steering DAC can drive external loads, and usually used in high speed application. In recent years, many digital-to-analog converters have been implemented in advanced process, especially in 130nm, 90nm, and CMOS process. However, as far as the cost is concerned, the area of chip is getting as smaller as possible. In this thesis, a low-cost high resolution and high speed DAC is implemented. A new Dynamic Element Matching (DEM) algorithm is proposed. This algorithm can resist the mismatch error of current source. The effect of Dynamic Element Matching is verified and improves the non-linear effect caused by mismatch of current source. DEM algorithm and Output Impedance Calibration (OIC) are taken to get a smaller area of DAC, especially in advance process. However, the performance at high input frequency can be improved by OIC and return-to-zero.
Besides, a 12-bit DAC is physically implemented in 90nm CMOS process. It has ultra-wide output swing of 1.4-Vpp under 1.2V supply voltage and small area for active area. The SFDR of DAC using proposed DEM and OIC achieves 76.18dB in low input frequency and 70.19dB at Nyquist bandwidth with operating frequency of 100MS/s. The active area is 0.06mm2.
30
Wei, Chia-Liang, and 魏嘉良. "A Low Power 12-bit 100KSample/s Successive- Approximation Analog-to-Digital Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/09580713306729557654.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立暨南國際大學<br>電機工程學系<br>99<br>In this thesis, A low power 12-bit 100KSample/s successive-approximation(SAR) analog-to-digital converter(ADC) is presented. The ADC contains a sample and hold circuit(S/H), a digital-to-analog converter(DAC), a latched comparator, and a successive-approximation register(SAR). The ADC is constructed by using binary search to the reference voltage in order to using a simple comparator. The DAC employs the hybrid structure including a C-2C capacitors array and a binary-weighted capacitors array, which reduces the power consumption.
The 12-bit 100 KSample/s SAR ADC chip works at 1V, and 1.4MHz clock. When input frequency is 13.281kHz, the signal to noise distortion ratio(SNDR) is 67.508dB, the total power consumption is 2.628μW, and the average energy per conversion step is 13.545 fJ.
The chip is designed using TSMC 0.18μm 1P6M CMOS process provided by Chip Implementation Center(CIC). The core area of the chip is 0.171 × 0.219 mm2, and the total area including pads is 0.68 × 0.78 mm2.
31
Wang, Yu-Chung, and 王玉忠. "A LCD SOURCE DRIVER WITH 12-BIT PIECEWISE LINEAR DIGITAL-TO-ANALOG CONVERTOR." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/65675397718599607485.
Der volle Inhalt der QuelleAnnotation:
碩士<br>大同大學<br>電機工程學系(所)<br>99<br>This thesis is to improve liquid crystal displays for color saturation and Gamma correction, and a piecewise linear 12-bit segmented digital-to-analog converter (DAC) for LCD source driver is proposed. The data conversion is carried out by an 8-bit resistor-string type DAC (R-DAC) and a 4-bit charge sharing DAC (C-DAC), which are used for the most significant bit and least significant bit data conversions, respectively. Piecewise linear compensation is utilized to reduce the die area and increase the effective color depth. In addition, Gamma correction can be applied to amend the characteristic of the liquid crystal transmittance-to-voltage to be a linear relationship. A folded-cascade operational amplifier with a class AB output stage has been designed for high frequency response and low static power of the output buffer amplifier.
The proposed LCD source driver was simulated using TSMC 0.35μm 2P4M CMOS process model. The operation voltage is 5V and the settling time of data converter is within 3.5μs. The static bias current of buffer amplifier is 6.64μA for each channel. The layout area for 2 channels is 865μm × 1250μm (without I/O pads).
32
Shen, Yu-Chen, and 沈游城. "A 12-BIT 50-MS/S BUILT-IN ANALOG SELF-CALIBRATED PIPELINE ADC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/77935746102177460675.
Der volle Inhalt der QuelleAnnotation:
碩士<br>大同大學<br>電機工程學系(所)<br>94<br>This thesis describes a design of a low-power, 12-bit, 50Msample/s, and 3.3-V supply pipeline analog-to-digital converter (ADC). In order to achieve the requirements of digital imaging, where differential nonlinearity (DNL) and integral nonlinearity (INL) are both important, we propose a built-in analog self-calibrated circuit of the ADC in this thesis. Compared with the ADC with the typical digital error correction architecture, our circuit does not need a large and complex digital circuit, but they are replaced by the self-calibration capacitor array and linear-range protection architecture. The entire circuit will be fabricated in a 0.35-um 2P4M CMOS process, the estimated chip area is 2.3×2.2mm2, and the power dissipation is 148mW. Final test results will be reported later.
33
"Design and Calibration of a 12-Bit Current-Steering DAC Using Data-Interleaving." Master's thesis, 2014. http://hdl.handle.net/2286/R.I.26805.
Der volle Inhalt der QuelleAnnotation:
abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.<br>Dissertation/Thesis<br>Masters Thesis Electrical Engineering 2014
34
Chang, Yung-Te, and 張永德. "A 12-bit zero-crossing-based pipelined-SAR ADC with single-polarity transfer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t7wu3n.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立清華大學<br>電機工程學系所<br>107<br>This thesis presents a 12-bit zero-crossing-based pipelined-SAR (successive-approximation register) analog-to-digital converter with single-polarity transfer.
The proposed ADC operates on pipelined mode and uses single-polarity transfer zero-crossing detection instead conventional multiplying digital-to-analog converter to achieve a higher operation speed and save power. The proposed single-polarity transfer zero-crossing detection can improve the power consumption from MDAC in pipelined ADC effectively and the error sources from the differential mode, which can save more power and increase linearity of the ADC.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 159×245μm2. At 1 supply voltage and 40MS/s sampling rate, the ADC achieves SNDR from 56.9dB corresponding ENOB from 9.2 bit at low frequency input and consumes 430uW power, resulting in a figure of merit (FoM) from 18.3 fj/coversion-step.
35
Dai, Yu-Kai, and 戴于凱. "12-Bit 500MHz Digital-to-Analog Converter Based on Highly Matching Current Mirror." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/21554786935199671737.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>In recent years, communication systems require high speed and resolution Digital-to-Analog Converter. For high speed operation, the work employed a current-steering and differential pair architecture. In circuit part, output impedance is restricted by the low supply voltage and MOS short-channel effect. Therefore, designing an accurate current source array is extremely difficult. The Digital-to-Analog Converter with a highly matching current mirror circuit is proposed in this work. The precision of this current source array can be obtained.
The proposed 500MHz 12-bit DAC is implemented in 0.18μm CMOS 1P6M technology with the supply voltage of 1.8V. The simulation results show the INL is better than and DNL is between -0.8～+0.02 LSB. Power comsumption of this DAC with a sigle 1.8V supply is 29.8mW. The active area is merely 0.8 mm2.
36
Lei, Kin-Man, and 李健文. "A 12-bit 25MS/s Asynchronous SAR ADC With All Digital Background Calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/07793099824693147628.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立交通大學<br>電控工程研究所<br>100<br>The resolution of a SAR ADC is mainly limited by the accuracy of capacitor ratios. Foreground and background calibration schemes [1][2][3][4][5] have been proposed to calibrate the capacitor weight errors. However, both kinds of calibration schemes may suffer from power and speed penalties. The foreground calibration schemes using charge redistribution have the advantage of simple implementation but the continuous variations of environmental parameters may cause it failed. The background calibration schemes can address the variation problems but its hardware is very complicated due to the implementation of complex mathematical equations.
This thesis proposes a calibration scheme that keeps the advantages of the foreground and background calibration schemes and improve the performance of the SAR ADC in power and speed. We also adopted a suitable bit-cycling scheme to simplify the comparator design and thus to enhance its performance.
Post-layout simulation results show that the calibrated SAR ADC achieves a SNDR improvement from 47.4dB to 63.9dB at a sampling rate of 25MS/ s when random mismatch is added on each capacitor in DAC. Measurement results shows the SAR ADC achieves a SNDR improvment from
47.1dB to 51.8dB at its highest sampling rate of 10MS/s.
37
Huang, Shao-Hung, and 黃少宏. "A Low Power 12-bit SAR ADC with Split Capacitor Array for Biomedical Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/86945961070280859000.
Der volle Inhalt der QuelleAnnotation:
碩士<br>淡江大學<br>電機工程學系碩士班<br>100<br>Under the development of microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP), Analog to Digital Converter (ADC) relted applications has been widely used. Speed, resolution, power consumption, and area are the four key specifications while designing ADC. Under the limitations of the actual conditions, trade-off was made within these four specifications in order to design the most appropriate ADC converter. This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system. In order to be able to capture the probability of arrhythmia through monitoring and recording ECG for a long period of time, the specifications must be low power consumption. The ADC converter chip proposed by this study was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The sample rate is 2000Hz in 500Hz signal bandwidth. The maximum design power is 30μW under 1.8V power supply.
38
Cheng, Ju-tien, and 鄭如恬. "A 12-bit Column-parallel Cyclic Analog-to-Digital Converter for CMOS Image Sensors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/68850192822754286755.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>94<br>Images in digital format is the most effective way for analysis, storage, and operation. The imager is the front-end of any machine vision system. There are two major type imager, Charge Coupled Device (CCD) and Complementary Metal-Oxide Semiconductor (CMOS). In order to achieve the function of digital image output, modern imaging system are typically implement with signal digitization function. For example, a traditional CCD camera system with a single analog output channel can be implemented with an independent single-chip ADC to convert analog image signal to digital format.
However, this traditional architecture faces the insufficient frame-rate limitation as high quality, high resolution digital images are required. For some machine vision applications, this architecture cannot achieve the desirable speed. Compared with CCD, the CMOS imager has the advantage of being integrated with CDS, ADC, and other control circuits on a single chip with CMOS process. Therefore the CMOS imager takes the place of CCD imagers step by step.
This thesis describes the theory, design, characterization and testing of a prototype 64 x 64 active pixel sensor (APS) array. This chip realizes a system including the pixel array, column-parallel correlated double sampling circuit (CDS) and column-parallel 12-bit analog-to-digital converter (ADC). There are on-chip reference voltage circuit and clock generator providing four reference voltage and all operation signals to control the chip. The array output utilizes the CDS and the ADC to convert image signal to digitized format. After reforming these digitized data with FPGA, we can show these image on PC via the digital frame grabber and make other process.
This camera-on-a-chip system uses TSMC 0.18 CMOS RF-Mix signal 3.3V 1p6m process. The layout area of each pixel is 8.05 x 8.05um2. The CDS area and ADC area are 2042 um2 and 11254 um2. The power consumption of the chip is 60 mW with ENOB as high as 11-bit. The CDS and ADC allow a high frame rate that can achieve the HDTV 1080p specification. And the maximum frame rate of the 64 x 64 CMOS image sensor array is 520 frames/s with progressive scan.
39
Hwa-AnTseng and 曾華安. "A 12-bit 50-MS/s Time-Interleaved Successive-Approximation Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/qh4xu4.
Der volle Inhalt der Quelle
40
Li-JenChang and 張力仁. "A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/22jsa9.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系<br>107<br>A 12-bit 10-MS/s calibration-free successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm process is presented in this thesis.
This work adopts two techniques, namely residue oversampling and detect-and-skip (DAS) algorithm. For each sample voltage, the residue oversampling technique generates different residual voltages by dynamically rearranging different weights to different capacitors in the capacitor array. These residual voltages would be quantized to generate digital codes with higher accuracy. Besides, the switching procedure could be optimized by the detect-and-skip (DAS) algorithm, which could effectively reduce the mismatch error caused by the MSB capacitors, during conversion. By combining the two techniques, the impacts caused by noise and capacitors’ mismatches could be improved significantly without any complex calibration scheme.
The proof-of-concept 12-bit SAR ADC occupies 0.47mm2. It operates at 10-MS/s and 6-MS/s with 1.95-V and 1.9-V supplied voltages, respectively. The measurement results show that the prototype ADC achieves 63.87 dB SNDR at 10-MS/s with a Nyquist-rate input and 67.79 dB SNDR at 6-MS/s with a 2MHz input. The figure-of-Merit (FoM) is 185.3fJ/conversion-step and 128fJ/conversion-step, respectively.
41
Su, Yen-Ying, and 蘇彥熒. "A 12‐bit Column‐parallel Cyclic Analog‐to‐Digital Converter for CMOS Image Sensors." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/03752608734621050278.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>ABSTRACT
Images in digital format is more convenient for analysis, storage, and operation. In order to achieve the function of digital image output, modern imaging systems are typically implement with signal digitization function. For example, a traditional CCD camera system with a single analog output channel can be implemented with an independent single-chip ADC to convert analog image signal to digital format. However, this traditional architecture faces the insufficient frame-rate limitation as high quality, high resolution digital images are required. For some machine vision applications this architecture cannot achieve the desirable speed. Modern trend on implementing imagers, ADC and other peripheral circuits on a single chip with CMOS process provides an alternative solution.
This thesis describes the theory, design, and characterization of a prototype 64 x 64 APS pixel array. Area for each pixel is 8.05 x 8.05 um2. The array output utilizes a column-parallel correlated double sampling circuit, and a column-parallel 12-bit analog-to-digital converter to convert image signal to digitized format. It allows a high frame rate that can achieve the HDTV 1080p specification. A bandgap reference voltage circuit provides four temperature insensitive reference voltages. An on-chip clock generator generates all operation signals to control the chip. This camera-on-a-chip system uses TSMC 0.18 CMOS RF-Mix signal 3.3V 1p6m process. The layout area of the CDS is 2042 um2. And the ADC area is 11254 um2 with ENOB as high as 11-bit. The power consumption of the chip is 87 mW . The frame rate of the 64x64 CMOS image sensor array can achieve 520 Frames/s with progressive scan.
42
Ni, Hung-Po, and 倪宏博. "Design and Implementation of 12-bit SAR ADCs with Binary-Window DAC Switching Technique." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/05097672315184836784.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺灣科技大學<br>電子工程系<br>105<br>This dissertation implements two successive-approximation registers (SAR) analog-to-digital converters (ADCs). The first is a 12-bit 20-MS/s SAR ADC in UMC 0.18µm CMOS. The second is a 12-bit 60-MS/s SAR ADC in UMC 55nm LPCMOS. In order to avoid large capacitance to meet the linearity requirement for DAC, we propose two switching techniques. There are the binary-window DAC switching technique and the capacitor-swapping technique to solve the problem of linearity.
The first SAR ADC was fabricated in UMC 0.18µm CMOS. The die area is 2.25mm2 and ADC uses a chip area of approximately 0.1mm2. The ADC consumes 1.17 mW from 1.5V supply voltage, and effective number of bit (ENOB) is 9.3 bits at 10 MS/s. The SFDR with capacitor swapping technique is 86.6dB. Though the analysis and results, the revised chip had been taped-out in June, 2017.
The second SAR ADC was fabricated in 55 nm LPCMOS and achieves 67.7 dB SNDR at 60 MS/s with only 1.14 mW of power consumption, leading to a FoM of 8.69 fJ/conversion-step and SFDR achieves 90dB. The ADC uses a chip area of approximately156×230 μm2. This chip had been taped-out in May, 2017.
43
Guo, Rong-Jhou, and 郭榮洲. "Design of a 12-bit, Ultra-low Power Successive Approximation Analog-to-Digital Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/32630405104494533917.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立交通大學<br>電機與控制工程系所<br>96<br>This paper presents a 12-bit, ultra low power successive approximation analog-to-digital converter in TSMC 0.18μm 1P6M CMOS process. The analog-to-digital converter uses the offset-free pre-amplifiers to alleviate the impacts of the comparator’s offset. The bridging capacitive DAC is adopted to reduce the nonlinearity and to save the power of the DAC. The pre-amplifiers with a rail-to-rail input range are used to make the input range of the ADC also rail-to-rail. We used a diode-connected transistor in parallel with a negative resistor as the loads of the pre-amplifers in order to enable them operating at a supply voltage as low as 0.5V. Measurement results show that at an output rate of 1KS/s and a supply voltage 0.55V, the SA ADC provides a rail-to-rail input range and achieves a signal-to-noise-distortion ratio (SNDR) of 50.7dB and an effective resolution bandwidth (ERBW) up to the Nyquist bandwidth (500Hz). Its power consumption is as low as 35 nW, corresponding to an energy figure of merit (FOM) as good as 124fJ/conversion-step. The power of the proposed ADC is 24 times better than the lowest record of the state-of-the-art works as far as we know.
44
Wei, Yen-Hsin, and 魏衍昕. "A 12-bit 600MS/s Time-Interleaved SAR ADC with Background Timing Skew Calibration." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/19086299833215672228.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>103<br>A four channel time-interleaved 12-b SAR ADC, employing the proposed digital calibration technique to correct timing skew, achieves a 600-MHz sampling rate. The interleaved ADC composed of four channel SAR ADC. Digital mixing method is used to estimate timing skew, and proposed dual core with delay sampling is used to correct the timing skew. The ADC has been fabricated in a 40-nm CMOS technology, improves interleaving spurious tones from -50dB to -76dB and achieves a 61.7-dB SNDR while dissipating 23 mW from a 0.9-V power supply. The figure of merit (FoM) is 38.7 fJ/conversion-step and the active area is 0.3 mm2
45
Pannell, Zachary William. "Design of a Highly Constrained Test System for a 12-bit, 16-channel Wilkinson ADC." 2009. http://trace.tennessee.edu/utk_gradthes/549.
Der volle Inhalt der QuelleAnnotation:
Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.
46
Hsu, Pei-Jung, and 許倍榮. "A 12-bit 100-MS/s Zero Crossing Based Pipelined ADC With Current Mismatch Correction." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/22210442056161344047.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立中正大學<br>電機工程研究所<br>100<br>This work presents a 12b 100MS/s zero-crossing-based switched-capacitor CMOS pipelined analog-to-digital converter (ADC). The proposed ADC improves the resolution, power efficiency, and sample rate of the fully differential zero-crossing-based circuits and features a 90nm CMOS technology. Offset tolerance, current splitting, and a digital correction scheme were implemented to correct mismatches among current sources. Post-layout simulations show that the SNDR is 72.6dB when the input is close to Nyquist rate. The power consumption is 20.8mW from a 1.2V supply and the figure-of-merit (FOM) is 119 fJ/conversion. The chip area occupies 2.88mm2.
47
Tang, Yi Fu, and 湯益福. "A 12-bit Time-Domain Analog-to-Digital Converter With a Multiphase Voltage-Controlled Oscillator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93859287530846279552.
Der volle Inhalt der QuelleAnnotation:
碩士<br>長庚大學<br>電機工程學系<br>100<br>This thesis intends to discuss on how to construct an analog-to-digital conveter (ADC) by using the conversion of time-domain signals. We try to transform the analog voltage signal into digital time-pulse signal hence to form the digitally assisted analog circuit design. In theorical view, while the characteristic length of CMOS gates continuously shrinks to the nano-meter scale, the variations of analog signal increase, the current leakage of gates increases, and the open loop gain decreases…etc., more and more disadvantages occur. Since the accuracy and stability of analog voltage have been decreased ever, researchers want to use the digital signals and circuits to assist traditional analog structures with their advantage of scaling, for example, faster gates and lower power.
Here we construct a conversion system including multiphase voltage-controlled oscillator (VCO), 6-bit time domain analog-to-digital converter (coarse controller), and 6-bit multiphase time-to-digital converter (fine controller). The VCO oscillates at 1 GHz with 16 phases for the fine controller and a frequency divider that provides the counting frequency and sampling frequency for the system. The coarse controller transforms the analog voltage input into time-pulse signals by the ramp generator. The combination of coarse controller and ramp calibrator has enhanced the reliablility of the ramp hence makes the conversions under accurate range of voltage. The fine controller uses the 16 phases from VCO and combines the novel phase expander circuit, it not only increases the resolution, but also has the advantages such as monotonicity of phase triggering and variations resisting due to the synchronization of phases and sampling frequency. The fine controller collects the time residue of the coarse conversion and calculates the time residue to gain extra resolution thus increase the overall accuracy of the system.
This thesis uses the TSMC 0.18μm 1P6M Mixed Signal process to tapeout, the supply voltage is 1.8 V, the sampling frequency is 1 MHz, the counting frequency is 256 MHz, and the phase frequency is 1.024 GHz. The total power dissipation measured is 50.7 mW, the chip size (including pads) is 1.02 mm2, the core circuit size is 0.25 mm2. By simulation: The input signal is about 10 KHz and the results of coarse controller are 36.3 dB for signal-to-noise-and-distortion ratio (SNDR) and 41.5 dB for spurious-free dynamic range (SFDR). The fine controller has differential nonlinearity (DNL) less than 0.25 LSB and integral nonlinearity (INL) less than 0.48 LSB. By measurement: The jitter of the VCO is 10 ps under 10,000 hits of clock, and the dynamic verification has obtained 36.3 dB for SNDR, 44.8 dB for SFDR, and 5.74 bits for ENOB.
48
Lin, Wei-Ting, and 林葦婷. "A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/14040227441703086392.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立清華大學<br>電機工程學系<br>101<br>This thesis presents a 12-bit 100KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The A/D converter is designed in TSMC 0.18um CMOS process and operates at a supply voltage of 1.8V. The SAR A/D converter includes track-and-hold (T/H) stage, comparator, digital-to-analog converter and SAR control logic. Bootstrapped switch is used in S/H for improving circuit linearity and reducing the signal distortion. The comparator is composed of a dynamic latched regenerative circuit which gives comparator output better accuracy and higher speed because of positive feedback. Split capacitor array is used in D/A converter to decrease the total capacitance and save average power. Finally, the SAR control logic circuit uses a form of shift-registers-control conversion process and a row of D flip-flops for controlling the spilt capacitor array.
The performance of the converter would be degraded due to the process variation and device mismatches. This thesis proposes self-correction circuits for comparator and D/A separately capacitor array calibration, larger LSB is chosen as a new reference unit capacitor, and produce a new binary-weighted capacitor array by charge redistribution. After D/A calibration, comparator input offset voltage needs to be calibrated and canceled. Because this offset is not linear, a new calibration method is proposed that divides input voltage into multiple windows and use piecewise linear approximation to predict and reduce input offset. Before normal operation, calibration mode is created to do DAC and comparator calibrations. Digital calibration codes are saved in latches, and these digital codes can be used in normal operation mode without wasting other clock cycles. After digital calibration, when sampling rate is 100KS/s, the SNDR is found to be 66.78dB, and ENOB is 10.8 bits. DNL and INL are found to be 0.69 and 0.86 LSB, respectively.
Comparing to other calibration methods, the proposed calibration can predict and reduce offset for full range input voltages, thus has higher accuracy than other digital calibration methods. Since the digital calibration is used, calibration results are saved in flipflops and can be reused repeatedly. Smaller chip and shorter normal mode operation can be achieved. In addition, digital circuit is easier to scale and thus needs smaller area for advanced technologies.
49
HouTsung-Tien and 侯宗典. "Design and Implementation of a 12-bit 100 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/37193550974193948180.
Der volle Inhalt der QuelleAnnotation:
碩士<br>崑山科技大學<br>電子工程研究所<br>94<br>In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture.
The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.3 LSB, DNL is less than 0.25 LSB, settling time is 9 ns, and glitch is 5.8 pV-s. For 1MHz sine wave input and 100 MHz sampling rate, the SFDR is 80 dB, and for 49MHz sine wave input and 100 MHz sampling rate, the SFDR is 67 dB. The power consumption is 127 mW at the maximum conversion rate.
The real world measurement results show that the proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.6 LSB, DNL is less than 0.4 LSB, settling time is 10 ns, and glitch energy is 25 pV-s. For 200 kHz sine wave input and 100 MHz sampling rate, the measured SFDR is 70.3 dB, and for 5 MHz sine wave input and 100 MHz sampling rate, the measured SFDR is 63.51 dB. The measured power consumption is 142 mW at the maximum conversion rate.
50
Liang, Ming-Chieh, and 梁明傑. "A 12-Bit 200MS/S Current-Steering DAC with TSMC 0.18um PDK Monte-Carlo-Analysis." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/04521674800079642167.
Der volle Inhalt der QuelleAnnotation:
碩士<br>國立清華大學<br>產業研發碩士積體電路設計專班<br>98<br>We propose a 12-Bit 200MS/S Current-Steering DAC based on a Segmented (5+7) current-steering architecture. In order to decrease the differential nonlinearity error (DNL) and reduce area, we employ Unary-Current cell with thermometer code decoder for the 5MSBs and Binary-Weighted Current Cell for the 7LSBs. In order to synchronize inputs and improve glitch energy, we use a digital latch approach. Differential switch order is very critical for DNL, so we use the Two Dimensional Centroid method. In order to enhance DAC output impedance and SFDR, both the MSB and LSB are implemented with Cascode Current Cell.
To meet the 200MS/S and 1mm2 area spec, we perform Monte-Carlo Analysis with TSMC 0.18um Process Design Kit (PDK) and Mismatch Model. Because the Mismatch Model includes Process-Variation information, it can achieve more simulation accuracy than the corner model.
Monte-Carlo simulation result, shows that when the input signal is 100MHz and sample rate is 200MHz, we have DNL=0.6LSB , and INL =0.8LSB. The chip area is 0.2mm2 in a TSMC 0.18um 1P6M CMOS Process.