Inhaltsverzeichnis
Auswahl der wissenschaftlichen Literatur zum Thema „12-bit“
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Zeitschriftenartikel zum Thema "12-bit"
Kaur, Amandeep, Deepak Mishra und Mukul Sarkar. „A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC“. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, Nr. 1 (Januar 2019): 248–52. http://dx.doi.org/10.1109/tvlsi.2018.2871341.
Der volle Inhalt der QuelleSrivastava, Amit K., Atish Sharma, Tushar Raval und D. Chenna Reddy. „CAMAC based 4-channel 12-bit digitizer“. Journal of Physics: Conference Series 208 (01.02.2010): 012022. http://dx.doi.org/10.1088/1742-6596/208/1/012022.
Der volle Inhalt der QuelleKolluri, M. P. V. „A 12-bit 500-ns subranging ADC“. IEEE Journal of Solid-State Circuits 24, Nr. 6 (1989): 1498–506. http://dx.doi.org/10.1109/4.44985.
Der volle Inhalt der QuelleWells, S. C., G. J. Williamson und S. E. Carrie. „Dithering for 12-bit true-color graphics“. IEEE Computer Graphics and Applications 11, Nr. 5 (September 1991): 18–29. http://dx.doi.org/10.1109/38.90564.
Der volle Inhalt der QuelleSahoo, Bibhu Datta, und Behzad Razavi. „A 12-Bit 200-MHz CMOS ADC“. IEEE Journal of Solid-State Circuits 44, Nr. 9 (September 2009): 2366–80. http://dx.doi.org/10.1109/jssc.2009.2024809.
Der volle Inhalt der QuelleNeal, Brent. „Photoshop and 12-bit Digital Microscope Camera Images“. Microscopy Today 12, Nr. 2 (März 2004): 24–25. http://dx.doi.org/10.1017/s1551929500051956.
Der volle Inhalt der QuelleJayamani, Jayapramila, Noor Diyana Osman, Abdul Aziz Tajuddin, Zaker Salehi, Mohd Hanafi Ali und Mohd Zahri Abdul Aziz. „Determination of computed tomography number of high-density materials in 12-bit, 12-bit extended and 16-bit depth for dosimetric calculation in treatment planning system“. Journal of Radiotherapy in Practice 18, Nr. 03 (19.02.2019): 285–94. http://dx.doi.org/10.1017/s1460396919000013.
Der volle Inhalt der QuelleFAN Ci-en, 范赐恩, 吴敏渊 WU Min-yuan, 张立国 ZHANG Li-guo, 邓德祥 DENG De-xiang und 曹庆源 CAO Qing-yuan. „Companding transformation display for 12 bit image data“. Optics and Precision Engineering 19, Nr. 6 (2011): 1421–28. http://dx.doi.org/10.3788/ope.20111906.1421.
Der volle Inhalt der QuelleLu, Jing, Ho Joon Lee, Yong-Bin Kim und Kyung Ki Kim. „A 12-bit Hybrid Digital Pulse Width Modulator“. Journal of the Korea Industrial Information Systems Research 20, Nr. 1 (28.02.2015): 1–7. http://dx.doi.org/10.9723/jksiis.2015.20.1.001.
Der volle Inhalt der QuelleРембеза, S. Rembeza, Кононов und V. Kononov. „12-bit buttongenerator CMOS ADC with SOI-structure“. Modeling of systems and processes 6, Nr. 4 (21.01.2014): 53–55. http://dx.doi.org/10.12737/4047.
Der volle Inhalt der QuelleDissertationen zum Thema "12-bit"
Ricci, Luca. „Design of a 12-bit 200-MSps SAR Analog-to-Digital converter“. Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-284559.
Der volle Inhalt der QuelleSAR (Analog-Digital-omvandlaren) är en av de mest energieffektiva omvandlare. I den här avhandlingen är utvecklingen av en SAR ADC i en 28-nm CMOS-teknik baserad på laddning omfördelning presen- teras.Den implementerade SAR ADC använder en omkopplingsprocedur baserad på en modifierad version av den monotoniska omkopplingsalgoritm för att reducera omkopplingsenergin och DAC-området. DAC är en binärviktad matris med enhetskondensatorer. En anpassad kondensator för enheten har utformats med ett värde av 0,8 fF för att minska DAC-energiförbrukningen. Två komparatorer har implementerats, en dynamisk komparator och en statisk komparator. Den dynamiska implementering gör det möjligt att få bättre prestanda. Därför väljs den dynamiska komparatorn SAR ADC. Provtagningsomkopplarna startas upp för att minska icke-lineariteten introduceras när insignalen samplas. SAR-operationerna styrs av en asynkron logik implementerad som en beteendemodell i Verilog-A.Effekten av de designade kretsarna på konverterarens linearitet bedöms med integralen icke-linearitet (INL) och differentiell icke-linearitet (DNL). Dessutom är ADC: s prestanda bedömdes i termer av signal-till-brus-och-distorsionsförhållande (SNDR). Samsimulering av Verilog-A beteendemodeller och scheman tillåts utvärdera effekten av varje block på prestandan hos ADC. Omvandlaren kan uppnå en ENOB på 10,9 med en samplingshastighet på 200 MSps, vilket resulterar i en FoM eller 7,4 fJ / konv.- steg.
Todorov, Borislav St. „Performance evaluation of 12 and 14-bit converter technology for software radio applications“. Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0016/MQ57742.pdf.
Der volle Inhalt der QuelleTodorov, Borislav St (Borislav Stefanov) Carleton University Dissertation Engineering Systems and Computer. „Performance evaluation of 12 and 14-bit converter technology for software radio applications“. Ottawa, 2000.
Den vollen Inhalt der Quelle findenNuytkens, Peter R. (Peter Read). „A 12-bit 500 MHz GaAs MESFET digital-to-analog converter with p+ ohmic contact isolation“. Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/12760.
Der volle Inhalt der QuelleVita.
Includes bibliographical references (leaves 134-135).
by Peter R. Nuytkens.
M.S.
Thomsson, Pontus, und Aghamiri Cyrus Seyed. „Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator“. Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177548.
Der volle Inhalt der QuelleJuo, Ru-Hung, und 卓儒宏. „12-bit Digital Transmitter for VDSL“. Thesis, 2011. http://ndltd.ncl.edu.tw/handle/qqzuha.
Der volle Inhalt der Quelle國立臺北科技大學
電機工程系研究所
99
This thesis describes the chip implementation of a 200 MHz CMOS digital transmitter based on VDSL system specification. which is composed of a 12-bit, 200 MHz digital to analog converter, and a fully differential current-mode line driver. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology. For high-speed application, the digital to analog converter adopts the switch-current mode architecture. This is a 12-bit digital-to-analog converter (DAC) is implemented with M-bit segmented, which is implemented with 3-bit binary and 9-bit unary. Buffers are used to isolate the output of digital circuit and to reduce the glitch of current. Furthermore, in case of achieving small layout area, reducing the complexity of digital circuit, 9-bit unary is composed with the 3-bit and 6-bit thermometer-encoding architecture. In order to mitigate the process variation and linear error, current source array (CSA) is applied. The simulation of 12-bit DAC shows that the max current is 4095 μA, the integral nonlinearity (INL) and the differential nonlinearity (DNL) are 0.32 LSB and 0.39 LSB respectively. In order to have high power efficiency, in line driver the utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. Furthermore, the capacitive feed-forward path is introduced used to reduce the crossover distortion; and that the current-feedback circuit is added to increase linearity. According to the simulation result the output voltage of the proposed line driver is 2 VPP at differential load of 100 Ω, the power supply of 1.8 V and the operating frequency of 100 MHz.
Sheng-YangWeng und 翁聖洋. „A 14-Bit 2GS/s and 12-Bit 4GS/s Reconfigurable DAC with Triple Modes“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/33707004393574784529.
Der volle Inhalt der Quelle國立成功大學
電機工程學系
102
In this thesis, a triple-mode 14-bit 2GS/s or 12-bit 4GS/s reconfigurable current-steering digital-to-analog converter (DAC) is presented. For different DAC applications, triple mode is proposed, which means over-sampling mode, Nyquist mode, and over-Nyquist mode. The target of this work is that using a single DAC chip to fulfill all of the applications and with better performances than any state-of-the-art work. For this target, many techniques are proposed to improve the performances. In current-steering DAC design, current source mismatch is a main problem. Minimum switching dynamic element matching (MSDEM) and data weighted averaging (DWA) are adopted to process the harmonic distortion caused by mismatch. In addition, for over-sampling mode, DWA is used to improve the performance in narrow band. Moreover, for over-Nyquist mode, a novel method is proposed which makes the signal consumption 〈 10dB and spurious-free dynamic range (SFDR) 〉 65 dB up to 3rd Nyquist band. The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.082mm2 of active area. The measurement results show that the DAC achieves 〉60dB SFDR from dc to 0.55GHz at 1.1GS/s and the 14-bit Nyquist band performance is the best in figure of merit (FOM) comparing to state-of-the-art works.
Hsiao, Ming-Kai, und 蕭名開. „12-Bit low power SAR-ADC for ECG application“. Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05793753502319870096.
Der volle Inhalt der Quelle淡江大學
電機工程學系碩士在職專班
99
With the constant improvement on highly advanced technology nowadays, under the development of the microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP) influence, Analog to Digital Converter (ADC) has become a widely used application. The request for ADC specification will therefore be strict, as a result, more research will be conducted aggressively in the industrial and academic field. In order for ADC application become extensively used and correspond to the requirement of the present electronic products, four conditions need to be concerned: Speed, Resolution, Power, and Area. However, under the restriction of the factual conditions, in the process of designing, none of the ADC models was able to entirely correspond to the four conditions, thus trade-off was made for several application. This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system. It is aimed for capturing the probability of arrhythmia through monitoring and recording ECG for a long period of time. Consequently, the power voltage was defined in 1V for low power consumption purpose. The chip was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The sample rate is 600Hz in 150Hz signal bandwidth. Simulation results show that the SNDR and ENOB of the SAR-ADC with an input frequency of 24Hz are 67.53dB and 10.92dB. The power dissipation is 20.28μW under 1V power supply.
Lin, Chi-shen, und 林綮紳. „A 12-bit Power Saving DAC with Clock Controller“. Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7f3sus.
Der volle Inhalt der Quelle國立中山大學
資訊工程學系研究所
102
In this thesis, A 12-bit 1GS/s DAC for wireless communications is proposed. In order to achieve the high performance requirements, the current-steering architecture is the most suitable and widely used in the present design. The segmented current steering architecture that comprises 8MSB’s thermometer code and 4LSB’s binary-weighted is used. In this design, a new technique of the column clock controller (CCC) is proposed to improve the DAC performance. The Column clock controller (CCC) is able to reduce the clock feed-through effect for DAC and reduce power consumption from switching activity. The designed DAC implemented in TSMC 90nm CMOS technology. When the CCC is enabled, the simulation results show that INL is 0.019LSB and DNL is 0.008LSB; When the CCC is disabled, the simulation results show that INL is 0.018LSB and DNL is 0.011LSB. When the CCC is enabled and disabled, the SFDR is 85dB and 82dB respectively. The power consumption is 24mW.
LAI, CHENG-QIAN, und 賴承謙. „Ultra Low Power 12-Bit Analog-to-Digital Converter“. Thesis, 2019. http://ndltd.ncl.edu.tw/handle/yvz8sn.
Der volle Inhalt der QuelleBücher zum Thema "12-bit"
Réunion du BIT/PECTA des planificateurs africains de l'emploi (1988 Kinshasa, Zaire). Le Défi de la planification de l'emploi en Afrique: Rapport de la réunion du BIT/PECTA des planificateurs africains de l'emploi, Kinshasa, Zaïre, 12-15 décembre 1988. Addis Abéba: Programme des emplois et des compétences techniques pour l'Afrique, 1990.
Den vollen Inhalt der Quelle findenMEDICINE KNIFE, THE (The Spanish Bit Saga, No 12). Domain, 1989.
Den vollen Inhalt der Quelle findenZhang, Ligang. A 2V 12-bit pipelined A/D converter using current-mode techniques. 1993.
Den vollen Inhalt der Quelle findenST 2036-4:2015: Ultra High Definition Television — Multi-link 10 Gb/s Signal/Data Interface Using 12-Bit Width Container. 3 Barker Avenue., White Plains, NY 10601: The Society of Motion Picture and Television Engineers SMPTE, 2015. http://dx.doi.org/10.5594/smpte.st2036-4.2015.
Der volle Inhalt der QuelleJohansen, Bruce, und Adebowale Akande, Hrsg. Nationalism: Past as Prologue. Nova Science Publishers, Inc., 2021. http://dx.doi.org/10.52305/aief3847.
Der volle Inhalt der QuelleBuchteile zum Thema "12-bit"
Mulder, Jan, Davide Vecchi, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan und Klaas Bult. „A 12-bit 800 MS/s Dual-Residue Pipeline ADC“. In Nyquist AD Converters, Sensor Interfaces, and Robustness, 13–30. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-4587-6_2.
Der volle Inhalt der QuellePrabhavathi, P., N. B. Mahesha und Subodhkumar Panda. „Design of 12-Bit Cyclic Vernier Ring Time-to-Digital Converter“. In Lecture Notes in Electrical Engineering, 123–31. India: Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1524-0_18.
Der volle Inhalt der QuelleVorenkamp, Pieter, und Raf Roovers. „A 12 bit, 50 MSample/s Cascaded Folding & Interpolating ADC“. In Analog Circuit Design, 89–104. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2602-2_5.
Der volle Inhalt der QuelleKumar, Abhishek, Santosh Kumar Gupta und Vijaya Bhadauria. „A Low Power Approach for Designing 12-Bit Current Steering DAC“. In Lecture Notes in Electrical Engineering, 595–604. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6840-4_49.
Der volle Inhalt der QuelleVinay, B. K., S. Pushpa Mala, S. Deekshitha und M. P. Sunil. „A Design of 12-Bit Low-Power Pipelined ADC Using TIQ Technique“. In Intelligent Computing and Communication, 601–11. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1084-7_58.
Der volle Inhalt der QuelleKoul, Shiban Kishen, und Sukomal Dey. „MEMS 3-Bit and 4-Bit Phase Shifters Using Two Back-to-Back Switching Networks“. In Radio Frequency Micromachined Switches, Switching Networks, and Phase Shifters, 229–43. Boca Raton, FL : CRC Press, Taylor & Francis Group, [2019]: CRC Press, 2019. http://dx.doi.org/10.1201/9781351021340-12.
Der volle Inhalt der QuelleTraynor, Michael. „Yasmin, the nurse who was bullied and who bit back“. In Stories of Resilience in Nursing, 79–83. Abingdon, Oxon ; New York, NY : Routledge, 2020.: Routledge, 2019. http://dx.doi.org/10.4324/9781351050272-12.
Der volle Inhalt der Quelle„An Inherently Monotonic 12 Bit DAC“. In Direct Digital Frequency Synthesizers. IEEE, 2010. http://dx.doi.org/10.1109/9780470544396.ch35.
Der volle Inhalt der QuelleHoskins, Kevin R. „Micropower 12-bit ADCs shrink board space“. In Analog Circuit Design, 761–62. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800001-4.00355-0.
Der volle Inhalt der QuelleHoskins, Kevin R. „Applications versatility of dual 12-bit DAC“. In Analog Circuit Design, 781–82. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800001-4.00364-1.
Der volle Inhalt der QuelleKonferenzberichte zum Thema "12-bit"
Turunen, Vesa, Tero Nieminen, Marko Kosunen und Kari Halonen. „12-bit 2.4 GHz D/A upconverter“. In 2007 European Conference on Circuit Theory and Design (ECCTD 2007). IEEE, 2007. http://dx.doi.org/10.1109/ecctd.2007.4529578.
Der volle Inhalt der QuelleWeidong Yang, Ruzhang Li, Yong Liu, Yonghui Yang und Kaicheng Li. „Investigation into the 12-bit DA converter“. In 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415718.
Der volle Inhalt der QuelleOLCAY, ECE, LIDA KOUHALVANDI und SERCAN AYGUN. „1 5 Bit Stage 12 Bit Pipeline ADC Design with Foreground Calibration“. In Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017. Institute of Research Engineers and Doctors, 2017. http://dx.doi.org/10.15224/978-1-63248-138-2-16.
Der volle Inhalt der QuelleHisano, S., und M. P. Timko. „A complete single supply CMOS 12 bit DAC“. In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56702.
Der volle Inhalt der QuelleMukherjee, Dwip Narayan, Saradindu Panda und Bansibadan Maji. „Design of low power 12-bit magnitude comparator“. In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8073916.
Der volle Inhalt der QuelleTang, Honghui, Haibin Wang, Zhijian Hui, Tao Qin, Xinyi Hu, Younis Ibrahim, Xixi Dai et al. „A Radiation-Hardened 12-bit SAR ADC Design“. In 2018 7th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO). IEEE, 2018. http://dx.doi.org/10.1109/icrito.2018.8748621.
Der volle Inhalt der QuelleGueddah, N., K. Abbes und M. Masmoudi. „Design of a low power 12-bit ADC“. In Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2010. http://dx.doi.org/10.1109/dtis.2010.5487576.
Der volle Inhalt der QuelleTakayama, Ogami, Jun Honjo und Hirose. „12 Bit/25.6M sps Subranging A/D Converter“. In Conference on Precision Electromagnetic Measurements. IEEE, 1988. http://dx.doi.org/10.1109/cpem.1988.671299.
Der volle Inhalt der QuelleCan Peng, Shuang Cui, Chao Wang, Xiao-Tian Yang und Yu-Chun Chang. „A 12-bit cyclic ADC for image sensor“. In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016. http://dx.doi.org/10.1109/icsict.2016.7999025.
Der volle Inhalt der QuelleXingfa Huang, Jiabin Zhang, Ruzhang Li, Kaikai Xu, Zhou Yu, Xin Lei und Kaicheng Li. „A poly-resistor 12-bit D/A converter“. In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734956.
Der volle Inhalt der QuelleBerichte der Organisationen zum Thema "12-bit"
Karnitski, Anton, Christopher Gill, Aliaksandr Zhankevich und Dalius Baranauskas. 12-bit 32 Channel 500MSps Low Latency ADC. Office of Scientific and Technical Information (OSTI), November 2017. http://dx.doi.org/10.2172/1413257.
Der volle Inhalt der QuelleKobayashi, K., A. Ogawa, S. Casner und C. Bormann. RTP Payload Format for 12-bit DAT Audio and 20- and 24-bit Linear Sampled Audio. RFC Editor, Januar 2002. http://dx.doi.org/10.17487/rfc3190.
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